JPH0877072A - Cache memory device - Google Patents

Abstract

PURPOSE: To prevent a cache hit rate from decreasing depending upon an application program and to prevent the execution efficiency of the application program from decreasing at the time of an access conflict. CONSTITUTION: A two-way associative cache memory consists of tag memories 410 and 412 and data memories 417 and 421. An instruction address from an instruction address bus 401 and a data address from a data address bus 402 are distributed to respective ways of the cache memory by registers 403, 404, and 405, and multiplexers 406, 407, 408, and 409. Coincidence circuits 411 and 413 decide whether or not the tag addresses of the distributed addresses are registered in the tag memories 410 and 412. When they are registered, data memories 417 and 421 are accessed by registers 414 and 415, multiplexers 416 and 420, and bus drivers 418, 419, 422, and 423.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache memory device for temporarily holding instructions and data between a central processing unit and a main storage device.

[0002]

2. Description of the Related Art Generally, in a computer system, a cache is used in order to adjust the difference in operating speed between a central processing unit (hereinafter referred to as "CPU") and a main storage device (hereinafter referred to as "main memory"). A memory device is provided.

This cache memory device comprises a memory unit (cache memory) for storing instructions and data, and a control unit for controlling the memory unit. By configuring the memory unit with high-speed elements, the CPU and the main memory are separated. It is designed to adjust for differences in operating speed.

By the way, as one of computer system architectures, there is a Harvard architecture in which a bus is separated into an instruction bus and a data bus.
A cache memory device is also provided in the computer system having the Harvard architecture. Conventionally, the following two methods have been considered as connection methods for the cache memory device in this case.

One is a method of inserting a cache memory device (hereinafter, referred to as "unified cache") shared between instruction access and data access between the bus control unit and the main memory (hereinafter, referred to as "first cache"). 1
Method. ). Here, the bus control unit is a unit that adjusts access from the instruction bus and the data bus.

The other is to provide a dedicated cache memory device (hereinafter referred to as "dedicated cache") corresponding to each of the instruction bus and the data bus in front of the bus control unit (hereinafter referred to as "second cache"). Method.)). That is, in this method, a cache memory device dedicated to instruction access (hereinafter referred to as "instruction cache") and a cache memory device dedicated to data access (hereinafter referred to as "data cache") are provided in front of the bus control unit. .

FIG. 2 is a block diagram showing the configuration of a computer system configured by the first method, that is, a computer system having a unified cache.

In FIG. 2, 101 is a CPU, 102 is an instruction address bus, 103 is an instruction bus, 104 is a data address bus, 105 is a data bus, 106 is a bus control unit, 107 is a unified cache,
108 is an external address bus, 109 is an external data bus,
110 is a main memory.

The operation in FIG. 2 will be described below. CP
When accessing an instruction, the U 101 sends an instruction access request to the bus control unit 106 via the instruction address bus 102. On the other hand, when accessing data, a data access request is sent to the bus control unit 106 via the data address bus 104.

When the bus control unit 106 receives an instruction access request or a data access request, the instruction address bus 102 or the data address bus 104.
The address of the access selected from the external address bus 1
08 to the unified cache 107.

The bus control unit 106
Is an instruction access request and a data access request at the same time.
When issued from the PU 101, one of them is selected. In this case, the other waits until one access ends.

When the accessed data is registered in the memory section of the unified cache 107, that is, in the case of a cache hit, this data is transmitted via the external data bus 109 to the bus control unit 1.
06.

When the bus control unit 106 receives data from the external data bus 109, it receives the data, or if it receives both the instruction access request and the data access request at the same time, it sends the selected access request. Output to the receiving bus.

That is, the bus control unit 10
When the instruction access request is received or selected and the instruction access side access request is issued to the external address bus 108, 6 transfers the instruction from the external data bus 109 to the CPU 101 via the instruction bus 103. .

On the other hand, the bus control unit 106
When the data access request is received or selected and the data access side access request is issued to the external address bus 108, the data from the external data bus 109 is transferred to the CPU 101 via the data bus 105.

The unified cache 107 takes out this data from the main memory 110 when the data accessed by the access request from the bus control unit 106 is not registered in the memory section, that is, in the case of a cache miss, and the external data is fetched. Transfer to the bus control unit 106 through the bus 109. At this time, the unified cache 107 also registers the data on the external data bus 109 in its own memory unit.

The above is the configuration of the computer system provided with the unified cache. According to this structure, the bus control unit 106 outputs the instruction access request and the data access request in a mixed form. As a result, the unified cache 107
Both the command and the data are registered in.

In this case, when the number of frequently used instructions is larger than the number of frequently used data, more instructions are registered in the unified cache 107 than data. On the contrary, when the number of frequently used data is larger than the number of frequently used instructions, the data is registered more than the instructions.

As a result, instructions and data can be registered in the unified cache in accordance with the application program executed by the CPU 101, so that the cache hit rate can be increased.

FIG. 3 is a block diagram showing the configuration of a computer system configured by the second method, that is, a computer system having a dedicated cache.

In FIG. 3, 201 is a CPU, 202 is an instruction cache, 203 is an instruction address bus, 204 is an instruction bus, 205 is a data cache, 206 is a data address bus, 207 is a data bus, 208 is a bus control unit, 209. Is the external address bus, 210
Is an external data bus, and 211 is a main memory.

The operation in FIG. 3 will be described below. CP
When accessing an instruction, the U 201 outputs the address to be accessed to the instruction address bus 203.
The instruction cache 202 determines whether the instruction at that address is registered in the memory unit. If the instruction is registered, ie a cache hit,
The instruction cache 202 transfers this instruction to the CPU 201 via the instruction bus 204. As a result, this instruction is executed by the CPU 201.

If the command is not registered, that is,
In the case of a cache miss, the instruction cache 202 transfers the instruction access request to the bus control unit 208 via the instruction address bus 203. Upon receiving this request, the bus control unit 208 accesses the main memory 211 via the external address bus 209 and fetches the instruction corresponding to the address via the external data bus 210.

After this, the bus control unit 208
Receives the received instruction via the instruction bus 204 from the CPU 2
01 and the instruction cache 202. This allows
This instruction is executed by the CPU 201 and is registered in the memory unit of the instruction cache 202 together with its address.

When the data is accessed, the CPU 201 transfers the address to be accessed to the data address bus 206. The data cache 205 determines whether or not the data at that address is registered in the memory unit. If the data is registered, that is,
In case of cache hit, data cache 205
Transfers this to the CPU 201 via the data bus 207.

When the data is not registered, that is, when there is a cache miss, the data cache 205
Sends a data access request to the bus control unit 208 via the data address bus 206. When the bus control unit 208 receives this request,
The main memory 211 is accessed via the external address bus 209, and the data corresponding to the address is fetched via the external data bus 210.

After this, the bus control unit 208
Sends the captured data to the CP via the data bus 207.
Transfer to U201 and data cache 205. As a result, this data is processed by the CPU 201 and registered in the memory unit of the data cache 205 together with its address.

The above is the configuration of the computer system having the dedicated cache. According to such a configuration,
The CPU 201 can simultaneously access each of the instruction cache 202 and the data cache 205. As a result, even if the instruction access and the data access conflict with each other, it is not necessary to have the other access until the one access ends, so that the access execution efficiency can be improved.

[0029]

According to the first method,
As described above, according to the application program executed by the CPU 101, the unified cache 10
Commands and data can be registered in 7. Thus, according to this method, the unified cache 107
It is possible to increase the cache hit rate when accessing.

However, in this method, when the instruction access request and the data access request conflict with each other, it is necessary to wait the other access until one access ends. As a result, this method has a problem that the execution efficiency of the application program is reduced.

On the other hand, according to the second method, as described above, the CPU 201 can access the instruction cache 202 and the data cache 205 at the same time, so that even if the instruction access request and the data access request conflict with each other. , The execution efficiency of the application program does not decrease.

However, in the second method, since the capacity of the instruction cache 202 and the data cache 205 is fixed, there is a problem that the cache hit rate may decrease depending on the application program to be executed.

That is, the number of frequently used instructions and the number of data frequently differ depending on the application program executed on the CPU 201.

For example, in an application program such as a loop having a small number of instructions, frequently used instructions are slightly processed, and frequently used data are processed in large quantities. When executing such an application program, reducing the capacity of the instruction cache 202 and increasing the capacity of the data cache 205 reduces the number of cache miss occurrences in the data cache 205 and improves the processing efficiency of the CPU 201. Can be increased.

On the contrary, when executing an application program having a large number of frequently used instructions and a small number of frequently used data, the capacity of the instruction cache 202 is increased and the capacity of the data cache 205 is reduced. Therefore, the number of cache misses in the instruction cache 202 can be reduced, and the processing efficiency of the CPU 201 can be improved.

However, in the second method, since the capacity of the instruction cache 202 and the data cache 205 is fixed as described above, the storage capacity of the instruction and the data cannot be adjusted according to the application program. Therefore, this method results in frequent cache misses.

In a large application program,
The number of instructions in a loop that increases the frequency of use of instructions is greatly different in the program, and if the capacity of the instruction cache 202 and the data cache 205 is fixed, it is not possible to respond to changes in the program during execution, and It becomes less efficient.

As described above, in the cache memory device provided in the computer system having the Harvard architecture, the problem that the cache hit rate may be lowered by the application program and the execution efficiency of the application program is lowered when access conflicts occur. A device that can solve the problem is desired.

[0039]

In order to solve the above-mentioned problems, the present invention provides a cache memory device, which is provided with a cache memory, an address distribution unit, a registration determination unit, and an access unit. is there.

Here, the cache memory has a plurality of storage areas that can be accessed independently of each other, and for each storage area, an address storage area for holding the address of the main storage device and the address are stored in that address. It has a content storage area for holding the content stored therein.

The address allocating means has a function of allocating a plurality of addresses for accessing the main memory to a plurality of storage areas. The registration determining means has a function of determining whether or not the address assigned by the address assigning means is registered in the corresponding address storage area. The access means has a function of accessing the corresponding content storage area when it is determined that the address is registered.

[0042]

Operation: It is now assumed that a plurality of addresses are an instruction address and a data address. In this case, these two addresses are appropriately allocated to a plurality of storage areas according to the number of frequently used instructions and the number of frequently used data, for example. As a result, the storage capacity of instructions and data can be changed according to the number of frequently used instructions and the number of data, so that the cache hit rate may decrease depending on the application program executed by the CPU. The problem can be solved.

Since the respective storage areas of the cache memory can be accessed independently of each other, the CPU can simultaneously access the storage area in which the instruction is stored and the storage area in which the data is stored. This allows
Even if the instruction access request and the data access request compete with each other, it is possible to prevent the execution efficiency of the application program from decreasing.

[0044]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the following description, the case where the present invention is applied to a cache memory device provided in a computer system having a Harvard architecture will be described as a representative.

First, before describing the configuration of the cache memory device shown in FIG. 1, the configuration of a computer system having this cache memory device will be described with reference to FIG.

In FIG. 4, 301 is a CPU, 302 is the instruction cache 202 and data cache 205 of FIG.
Common cache, 303 is an instruction address bus, 304 is an instruction bus, 305 is a data address bus,
306 is a data bus, 307 is a bus control unit, 308 is an external address bus, 309 is an external data bus, and 310 is a main memory. The cache memory device of this embodiment corresponds to the common cache 302.

The operation of the above configuration will be described. When accessing an instruction, the CPU 301 of the Harvard architecture configuration outputs the address of the instruction to access to the instruction address bus 303. Similarly, when accessing data, the address of the data to be accessed is transferred to the data address bus 305.

The common cache 302 processes instruction and data access requests in parallel via the instruction address bus 303 and the data address bus 305, and determines whether each address is registered in the memory unit.

If the accessed instruction is registered,
That is, in the case of an instruction cache hit, the common cache 302 transfers this instruction to the CPU 301 via the instruction bus 304. Similarly, when the accessed data is registered in the cache 302, that is,
In the case of a data cache hit, this data is transferred to the CPU 301 via the data bus 306.

If the accessed instruction is not registered, that is, if there is an instruction cache miss, the common cache 302 notifies the bus control unit 307 via the instruction address bus 203 of the cache miss. Upon receiving this notification, the bus control unit 307 accesses the main memory 310 via the external address bus 308, and the external data bus 309
Take in the instructions via.

The instruction fetched by the bus control unit 307 is transferred to the CPU 201 via the instruction bus 304 and executed by the CPU 201. At the same time, this instruction is also registered in the memory unit of the common cache 302.

Similarly, when the accessed data is not registered, that is, when there is a data cache miss, the cache 302 determines that the bus control unit 3
A cache miss in 07 is notified via the data address bus 305. Bus control unit 3
07 receives this notification, and external address bus 308
To access the main memory 310 and fetch an instruction via the external data bus 309.

The data fetched by the bus control unit 307 is sent to the CPU 30 via the data bus 306.
1, and is processed by the CPU 301. At the same time, this data is also registered in the memory unit of the common cache 302.

The above is the outline of the computer system including the cache memory device (common cache) of this embodiment. Next, the cache memory device of this embodiment will be described with reference to FIG. In the following description, a 2-way cache memory (memory unit) is used.
A case where a set associative cache memory is used will be described as a representative, but a set associative cache memory having three or more ways has the same basic configuration.

The number of ways is the number of tag comparators used for tag comparison of addresses during retrieval. In this embodiment, the two ways are called way 0 and way 1. Each consists of a pair of tag memory and data memory.

In FIG. 1, 401 is an instruction address bus. Reference numeral 402 is a data address bus.

Reference numeral 403 is an instruction address register that holds the address of the instruction that accesses the common cache. In the following description, an upper address of this instruction address will be called an instruction tag address IT and a lower address will be called an instruction index address II.

Reference numeral 404 is a data address register which holds the address of the data for accessing this cache. In the following description, the upper address of this data address will be called the data tag address DT, and the lower address will be called the data index address DI.

Reference numeral 405 denotes data D0 designating whether to set way 0 for instruction access or data access.
And a data D1 designating whether the way 1 is set to instruction access or data access /
It is a data switching control register. Each data D0, D1
Is represented by 1 bit, and is set in the register 405 by an application program executed on the CPU, for example.

Reference numeral 406 denotes designated data D0 on the way 0 side held in the instruction / data switching control register 405.
According to the instruction index address II and the data address 40 held in the instruction address register 403.
4 is a low-order address multiplexer for tag 0 that selects one of the data index addresses DI held in No. 4.

Reference numeral 407 denotes designated data D0 on the way 0 side held in the instruction / data switching control register 405.
In accordance with the instruction tag address IT and the data address register 40 held in the instruction address register 403.
4 is a high-order address multiplexer for tag 0 that selects one of the data tag addresses DT held in No. 4.

Reference numeral 408 denotes designation data D1 on the way 1 side held in the instruction / data switching control register 405.
The lower address multiplexer for tag 1 selects either one of the instruction index address II held in the instruction address register 403 and the data index address DI held in the data address register 404 according to the above.

Reference numeral 409 denotes designated data D1 on the way 1 side held in the instruction / data switching control register 405.
In accordance with the instruction tag address IT and the data address register 40 held in the instruction address register 403.
4 is a high-order address multiplexer for tag 1 that selects either one of the data tag addresses DT held in No. 4.

Reference numeral 410 is a tag 0 memory on the way 0 side. When writing data to the way 0, the tag 0 memory 410 uses the index address selected by the tag 0 lower address multiplexer 406 as an address, and the tag 0 upper address multiplexer 407.
The tag address selected by is written.

On the other hand, when reading data from the way 0, the tag address is read using the index address selected by the tag 0 lower address multiplexer 406 as an address.

Reference numeral 411 denotes the tag address selected by the tag 0 upper address multiplexer 407 and the tag 0.
It is a tag 0 matching circuit that determines whether or not the tag address read from the memory 410 matches.

Reference numeral 412 is a tag 1 memory on the way 1 side. When writing data to the way 1, the tag 1 memory 412 uses the index address selected by the tag 1 lower address multiplexer 408 as an address and the tag 1 upper address multiplexer 409.
The tag address selected by is written.

On the other hand, when reading data from the way 1, the tag address is read by using the index address selected by the lower address multiplexer for tag 1 408 as an address.

Reference numeral 413 denotes the tag address selected by the tag 1 upper address multiplexer 409 and the tag 1
It is a tag 1 matching circuit that determines whether or not the tag addresses read from the memory 412 match.

An instruction register 414 holds an instruction to be registered in the common cache. A data register 415 holds data to be registered in the common cache.

Reference numeral 416 denotes designation data D0 on the way 0 side held in the instruction / data switching control register 405.
The multiplexer for data 0 selects any one of the instruction held in the instruction register 414 and the data held in the data register 415 according to the above.

Reference numeral 417 is a data 0 memory. The data 0 memory 417 is written with the selected output of the data 0 multiplexer 416 using the index address selected by the tag 0 address multiplexer 406 as an address when writing data to the way 0. On the contrary, when reading data from the way 0, the registration command or the registration data is read using the index address selected by the lower address multiplexer for tag 0 406 as an address.

Reference numeral 418 is an instruction bus driver for way 0. This bus driver 418 is such that the tag 0 matching circuit 411 determines that the two addresses match. The designated data D0 on the way 0 side held in the instruction / data switching control register 405 designates the instruction access. It is enabled only when the three conditions that the access to the common cache is read are satisfied at the same time.

Reference numeral 419 is a data bus driver for way 0. The bus driver 419 is such that the tag 0 matching circuit 411 determines that the two addresses match. The designated data D0 on the way 0 side held in the instruction / data switching control register 405 designates data access. It is enabled only when the three conditions that the access to the common cache is read are satisfied at the same time.

Reference numeral 420 is designation data D1 on the way 1 side held in the instruction / data switching control register 405.
The data 1 multiplexer selects one of the instruction held in the instruction register 414 and the data held in the data register 415 according to the above.

Reference numeral 421 is a data 1 memory. In the data 1 memory 421, when data is written to the way 1, the selection output of the data 1 multiplexer 420 is written with the index address selected by the tag 1 address multiplexer 408 as an address.

On the contrary, when reading data from the way 1, the registration command or the registration data is read using the index address selected by the tag 1 lower address multiplexer 408 as an address.

Reference numeral 422 is a way 1 instruction bus driver. The bus driver 422 is such that the tag 1 matching circuit 413 determines that the two addresses match. The designated data D1 on the way 1 side held in the instruction / data switching control register 405 designates the instruction access. It is enabled only when the three conditions that the access to the common cache is read are satisfied at the same time.

Reference numeral 423 is a data bus driver for way 1. This bus driver 423 is such that the tag 1 matching circuit 413 determines that the two addresses match. The designated data D1 on the way 1 side held in the instruction / data switching control register 405 designates data access. It is enabled only when the three conditions that the access to the common cache is read are satisfied at the same time.

Reference numeral 424 is an instruction bus. 425 is a data bus.

Here, the tag 410 memory 410 and the data 0
The memory for memory 417 will be collectively referred to as way 0. Further, the tag 1 memory 412 and the data 1 memory 421 are collectively referred to as a way 1.

Further, in the figure, the dotted line represents the control signal from the instruction / data switching control register 405 and the control signals from the tag 0 matching circuit 411 and the tag 1 matching circuit 413. Further, the solid line represents a data signal and the double line represents a bus.

The operation of the above configuration will be described. First, a read operation when the designated data D0 on the way 0 side held in the instruction / data switching control register 405 is set for instruction access will be described.

In this case, the tag 0 lower address multiplexer 406 selects the instruction index address II held in the instruction address register 403. Also, the upper address multiplexer 407 for tag 0
Then, the instruction tag address IT held in the instruction address register 403 is selected.

Thus, from the tag 0 memory 410,
The data corresponding to the instruction index address II selected by the tag 0 lower address multiplexer 406 is read. This data is the tag address registered in way 0.

Further, the data corresponding to the instruction index address II is read from the data 0 memory 417. This data is an instruction registered in way 0. The tag address read from the tag 0 memory 410 is supplied to the tag 0 matching circuit 411 and compared with the instruction tag address IT selected by the tag 0 upper address multiplexer 407. As a result, it is determined whether the two match.

When it is determined that the two match, the way 0
The order is registered in. That is, it is an instruction cache hit. As a result, in this case, the instruction read from the memory for data 0 417 is the way 0 enabled by the designated data D0.
Is transferred to the instruction bus 424 via the instruction bus driver 418.

On the other hand, if it is determined that they do not match, an instruction cache miss occurs. As a result, in this case, the instruction corresponding to the instruction address is fetched from the outside of the cache. Instructions fetched from outside the cache are
At the same time as being transferred to the CPU, it is set in the instruction register 414.

The instruction set in the instruction register 41 is
After being selected by the data 0 multiplexer 416 based on the designated data D0, the data 0 memory 417 is selected.
Is written to. At the same time, the tag address selected by the tag 0 upper address multiplexer 407 is written in the tag 0 memory 410. This means that the cache missed instruction is registered in the common cache.

Next, the instruction / data switching control register 4
A read operation when the designated data D0 on the way 0 side held in 05 is set for data access will be described.

In this case, the tag 0 lower address multiplexer 406 selects the data index address DI held in the data address register 404. Also, the upper address multiplexer 40 for the tag 0
In 7, the data tag address DT held in the data address register 403 is selected.

As a result, from the tag 0 memory 410,
The data corresponding to the data index address DI selected by the tag 0 lower address multiplexer 406 is read. This data is the tag address registered in way 0.

Data corresponding to the data index address DI is read from the data 0 memory 417. This data is the data registered in way 0.

The tag address read from the tag 0 memory 410 is supplied to the tag 0 matching circuit 411 and compared with the data tag address DT selected by the tag 0 upper address multiplexer 407. As a result, it is determined whether the two match.

If it is determined that the two match, the way 0
The data is registered in. That is, it becomes a data cache hit. As a result, in this case, the data read from the data 0 memory 417 is transferred to the data bus 425 via the way 0 data bus driver 419 enabled by the designated data D0.

On the other hand, if it is determined that they do not match, a data cache miss occurs. As a result, in this case, the data corresponding to the data address is fetched from the outside of the cache. The data fetched from the outside of the cache is transferred to the CPU and set in the data register 415 at the same time.

The data set in the data register 415 is selected by the data 0 multiplexer 416 based on the designated data D0 and then written in the data 0 memory 417. At the same time, the tag address selected by the tag 0 upper address multiplexer 407 is written in the tag 0 memory 410. As a result, the cache-missed data is registered in the common cache.

Next, the instruction / data switching control register 4
The write operation in the case where the designated data D0 on the way 0 side held in 05 is set on the data access side will be described.

In this case, the tag 0 lower address multiplexer 406 selects the data index address DI held in the data address register 404. Similarly, upper address multiplexer 4 for tag 0
At 07, the data tag address DT is selected. Further, the data 0 multiplexer 416 selects the data held in the data register 415.

As a result, from the tag 0 memory 410,
The data corresponding to the data index address DI selected by the tag 0 lower address multiplexer 406 is read. This data is the tag address registered in way 0.

The tag address read from the tag 0 memory 410 is supplied to the tag 0 matching circuit 411 and compared with the data tag address DT selected by the tag 0 upper address multiplexer 407. As a result, it is determined whether the two match.

If it is determined that the two match, the way 0
Since the data is registered once in, it becomes a data cache hit. So in this case,
The data selected by the data 0 multiplexer 416 is written in the data 0 memory 417 at a position corresponding to the data index address DI selected by the tag 0 lower address multiplexer 406.

On the other hand, if it is determined that they do not match,
Data cache miss. In this case, the data is
For example, it is written only in the main memory.

The access on the way 0 side has been described above, but the same access as on the way 0 side can be performed on the way 1 side by switching the designated data D1 set in the instruction / data switching control register 405. .

In this case, the tag 1 lower address multiplexer 408, the tag 1 upper address multiplexer 409, the tag 1 memory 412, the tag 1 matching circuit 413, the data 1 multiplexer 420, and the data 1 memory 421 on the way 1 side. , Way 1 instruction bus driver 42
2, the data bus driver 423 for the way 1 respectively includes the lower address multiplexer 40 for the tag 0 on the way 0 side.
6, tag 0 upper address multiplexer 407, tag 0 memory 410, tag 0 matching circuit 411, data 0
The operation corresponding to the data multiplexer 416, the data 0 memory 417, the way 0 instruction bus driver 418, and the way 0 data bus driver 419 is performed.

By changing the values of the designated data D0 and D1 set in the instruction / data switching control register 405 in this way, way 0 and way 1 can be set for instruction access and data access, respectively. . In this case, there are four combinations of instruction access, data access and cache ways 0 and 1 as shown in FIG.

When a plurality of ways for instruction access or data access are designated, the way to register the instruction or data is selected in the same way as in the normal set associative cache.
It is implemented by a replacement algorithm such as Recent Used).

According to this embodiment described in detail above, the following effects can be obtained.

(1) First, according to this embodiment, the cache memory device has a plurality of storage areas (ways 0, 1) that can be accessed independently of each other, and a main memory is provided for each storage area. An address storage area (memory for tag 0 410, memory 412 for tag 1) that holds the address of and a content storage area (memory 417 for data 0, memory 421 for data 1) that holds the content stored at that address An address distribution unit (register 40) that allocates a plurality of addresses (instruction address, data address) for accessing the cache memory and the main memory to the plurality of storage areas.
3, 404, 405, multiplexers 406, 407,
408, 409) and registration determining means (matching circuits 411, 4) for determining, for each storage area, whether the address assigned by the address assigning means is registered in the address storage area.
12), and when the registration determination means determines that the address is registered, the access means (register 414) for accessing the content storage area corresponding to the address storage area determined to have the address registered. , 415, multiplexers 416, 420, bus drivers 418, 4
19, 422, 423), it is possible to prevent a decrease in cache hit rate and a decrease in execution efficiency during access contention.

That is, according to the above configuration, the storage capacity of instructions and data can be changed according to the number of frequently used instructions and the number of frequently used data.
Depending on the application program executed by U, the problem that the cache hit rate may decrease can be solved.

Further, according to the above configuration, since each storage area can be independently accessed, even if the instruction access request and the data access request conflict with each other, the instruction access and the data access can be simultaneously performed. This allows
It is possible to solve the problem that the execution efficiency of the application program is deteriorated at the time of access conflict.

(2) According to this embodiment, since the cache memory of the set associative system having a plurality of ports is used as the cache memory, the cache memory having the above-mentioned structure is separately developed. It is possible to construct a cache memory device without any need.

(3) Further, according to this embodiment, as shown in FIG.
In the instruction cache 202 (or data cache 205) shown in FIG. 1, registers 403, 404, 405 and multiplexers 406, 407, 408, 409, 41 are provided.
The cache memory device can be constructed with a simple configuration in which only 6,420 is added.

Although one embodiment of the present invention has been described in detail above, the present invention is not limited to the above embodiment.

(1) For example, in the above embodiment, the case where the set associative cache memory having two ways is used as the cache memory has been described. However, the present invention may use a set associative cache memory having three or more ways.

(2) Also, in the previous embodiment, one C
The case where the present invention is applied to a cache memory device that is instruction-accessed and data-accessed by a PU has been described. However, the present invention can also be applied to a cache memory device that is instruction-accessed and data-accessed by two or more CPUs.

In this case, by changing the value of the register designating the way for each port during the execution of the access, it becomes possible to transfer the data between the CPUs via the way of the cache.

That is, it is assumed that the cache memory device of the present invention is connected to two CPU0 and CPU1. It is also assumed that the instruction / data switching control register designates way 0 for CPU0 data access. In such a state, it is assumed that the CPU0 updates the data of way0. After that, the instruction / data switching control register rewrites the way 0 to the data access of the CPU 1, so that the CPU 1 can take out the data registered in the way 0.

Thus, according to the present invention, two C
In the PU, it is possible to transfer data via a cache.

(3) Further, in the above embodiment, the case where the set associative cache memory is used as the cache memory has been described. However, the present invention may use a method other than the set associative method, for example, a direct mapping method cache memory.

(4) Furthermore, in the above embodiment, the case where the cache memory is composed of one memory chip having a plurality of ports has been described. However, the present invention may be configured with a plurality of memory chips.

That is, if the cache memory of the present invention has a plurality of storage areas that can be accessed independently of each other and that each storage area has an address storage area and a content storage area, a plurality of storage areas are provided. It may be configured with one memory chip having a port, or may be configured with a plurality of memory chips having one port.

(5) In addition to this, the present invention can of course be variously modified without departing from the scope of the invention.

[0124]

As described above in detail, according to the present invention,
A cache memory having a plurality of storage areas that can be accessed independently of each other, and a cache memory having an address storage area and a content storage area for each storage area, and a plurality of addresses for accessing the main memory. And means for deciding whether or not the address assigned by the address allocating means is held in the address storage area, and means for deciding that the address is held. Since the means for accessing the content storage area is provided, it is possible to solve the problem that the cache hit rate may be reduced by the application program and the problem that the execution efficiency of the application program is reduced due to access conflict. it can.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 Harvard with unified cache
It is a block diagram which shows the structure of the computer system of an architectural structure.

FIG. 3 is a block diagram showing a configuration of a computer system having a Harvard architecture configuration having a dedicated cache.

FIG. 4 is a block diagram showing a configuration of a computer system having a Harvard architecture configuration having a cache memory device according to an embodiment of the present invention.

FIG. 5 is a diagram for explaining the operation of the embodiment of the present invention.

[Explanation of symbols]

 301 ... CPU 302 ... Common cache 303 ... Instruction address bus 304 ... Instruction bus 305 ... Data address bus 306 ... Data bus 307 ... Bus control unit 308 ... External address bus 309 ... External data bus 310 ... Main memory 401 ... Instruction address bus 402 ... data address bus 403 ... instruction address register 404 ... data address register 405 ... instruction / data switching control register 406 ... lower address multiplexer for tag 0 407 ... upper address multiplexer for tag 0 408 ... lower address multiplexer for tag 1 409 ... tag 1 Upper address multiplexer 410 ... Tag 0 memory 411 ... Tag 0 matching circuit 412 ... Tag 1 memory 413 ... Tag 1 matching circuit 414 ... Instruction register 415 Data register 416 ... Data 0 multiplexer 417 ... Data 0 memory 418 ... Way 0 instruction bus driver 419 ... Way 0 data bus driver 420 ... Data 1 multiplexer 421 ... Data 1 memory 422 ... Way 1 instruction bus driver 423 ... Data bus driver for way 1 424 ... Instruction bus 425 ... Data bus

Claims (4)

[Claims] 1. A cache memory device for temporarily holding instructions and data between a central processing unit and a main memory unit, having a plurality of memory regions accessible independently of each other, and each memory region. A cache memory having an address storage area for holding the address of the main storage device and a content storage area for holding the contents stored at that address; and a plurality of addresses for accessing the main storage device, Address allocation means for allocating to a plurality of storage areas, and registration determination means for determining, for each storage area of the plurality of storage areas, whether the address allocated by the address allocation means is registered in the address storage area When the registration determining means determines that the address is registered, it is determined that the address is registered. Cache memory apparatus being characterized in that comprising an access means for accessing the contents storage area corresponding to the address storage area. 2. The address distribution unit, an address holding unit that holds the plurality of addresses, and a distribution information holding unit that holds distribution information indicating how to distribute the plurality of addresses to the plurality of storage areas. And a distribution unit configured to distribute the plurality of addresses stored in the address storage unit to the plurality of storage areas based on the distribution information stored in the distribution information storage unit. The cache memory device according to claim 1. 3. The plurality of addresses are an instruction address given via an instruction address bus and a data address given via a data address bus, and the address distribution means is given via the instruction address bus. Instruction address holding means for holding an instruction address, data address holding means for holding a data address given via the data address bus, and distribution indicating how to distribute the instruction address and the data address to the plurality of storage areas Sorting information holding means for holding information, and an instruction address held in the instruction address holding means and data held in the data address holding means based on the sorting information held in the sorting information holding means Addresses are assigned to the storage areas The access unit is configured to include an instruction holding unit that holds an instruction given via an instruction bus, a data holding unit that holds data given via a data bus, and the distribution unit. Distribution means for allocating the command held in the command holding means and the data held in the data holding means to the plurality of storage areas based on the distribution information held in the information holding means; The distribution means is provided for each storage area of the storage area, and when the address determined by the address allocation means at the time of writing is held by the registration determination means as being held in the address storage area of the own storage area, the allocation means Writing means for writing the command or data distributed by the above into the content storage area of its own storage area; The storage area is provided for each storage area of the storage area, and at the time of reading, when the registration determination means determines that the address assigned by the address assignment means is registered in the address storage area of the own storage area, the own storage area 2. The cache memory device according to claim 1, further comprising: a reading unit that reads out an instruction or data from the content storage area of and outputs to the instruction bus or the data bus. 4. The cache memory is a set associative type memory having a plurality of ports, and the address distribution unit is configured to distribute the plurality of addresses for each way of the cache memory. The cache memory device according to claim 1, wherein: