JPH07248967A - Memory control system - Google Patents

Abstract

PURPOSE:To use many cache memories for a processor which is carrying out the processing of higher priority in a multiprocessor system by changing dynamically the capacity of the cache memory that is allocated to the processor in accordance with the priority of the processing which is carried out by the processor. CONSTITUTION:The priority of a processor 10 and that of a processor 11 are set at '3' and '1' respectively on a priority table contained in a cache controller 30. Under such conditions, a cache memory 40 is preferentially allocated to the processor 10. Then the numbers of cach entries available to both processors 10 and 11 are set at '3' per set for the processor 10 and at '1' per set for the processor 11 respectively. The numbers of cache blocks available to both processors 10 and 11 are proportional to the cache entry numbers. Therefore 3/4 entire capacity of the memory 40 is allocated to the processor 10, and remaining 1/4 capacity is allocated to the processor 11.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control system for a system using a plurality of processors.

[0002]

2. Description of the Related Art In an information processing system requiring high processing performance, in order to meet the demand, a single processor system using only one processor is changed to a multiprocessor system using a plurality of processors. I am doing it. In a multiprocessor system, there are a tightly coupled system that shares memory and thereby exchanges data between processors, and a loosely coupled system that exchanges data between processors by communication without sharing memory. . In a loosely coupled system, each processor has an independent memory, which is disadvantageous in terms of system miniaturization and cost reduction.

In these systems, a cache memory may be used in addition to the main memory in order to improve the performance. In a tightly coupled system, there are a method of having a cache memory for each processor and a method of sharing a cache memory among the processors. In applications where downsizing and cost reduction are important, in order to reduce the number of memory elements to be used, a method of sharing a cache memory in a tightly coupled system is advantageous.

The operation of the system in this case will be described with reference to the system configuration example of FIG. In this figure, 10,
Reference numeral 11 is a processor, 20 is a memory bus, 30 is a cache controller, 40 is a cache memory, and 50 is a main memory. In this example, the number of processors is two, but it is also possible to use three or more processors. The processor 10 and the processor 11 can execute independent processing. Processor 10,
11 accesses the main memory 50 via the memory bus 20. The cache memory 40 has a main memory 50.
The capacity is smaller than that of, but high-speed access is possible. Usually, the cache memory 40 stores a copy of the data in the main memory 50.

When the processor 10 makes a read access to the main memory 50, if the data to be accessed exists in the cache memory 40, the main memory 50.
The cache memory 40 is accessed without accessing the cache memory 40. At this time, the cache was hit. On the contrary, if the data to be accessed does not exist in the cache memory 40, the main memory 50 is accessed. At this time, the cache missed. Since the cache memory 40 can be accessed faster than the main memory 50, the time required for memory access is shortened when the cache hits, and the processing performance of the system is improved. When the cache misses, the data read from the main memory 50 is also written in the cache memory 40. As a result, the cache is hit when the same data is accessed next time.

When data is written, the cache memory 40 is irrespective of whether the cache hits or misses.
And write data to both the main memory 50. This is for maintaining the consistency between the cache memory 40 and the data stored in the main memory 50.

Since the cache memory 40 has a smaller capacity than the main memory 50, it cannot store all the data in the main memory 50. Therefore, when new data is written in the cache memory 40, it may be necessary to overwrite the data. The cache memory 40 is managed in units of a plurality of blocks, and writing of data from the main memory 50 is performed in units of these blocks.

FIG. 2 shows a conventional cache controller 3
An example of the internal configuration of 0 is shown. In this figure, 31 is a tag memory for storing information regarding the data stored in each block of the cache memory 40. A configuration example of the tag memory 31 is shown in FIG. In this figure,
320 is a tag address and 321 is a valid flag. The set of tag address 320 and valid flag 321 is
It corresponds to one block in the cache memory 40. In the following description, this set is called an entry. 32
Is an address comparator for comparing a part of the address 300 input from the memory bus 20 with the tag address 320 in the tag memory 31. 33 is the memory bus 2
It is a selector for switching and connecting the data signal 310 connected to 0, the data signal 311 connected to the cache memory 40, and the data signal 312 connected to the main memory 50. Reference numeral 34 is a cache hit determination signal.

The operation of the system of FIG. 1 using the cache controller 30 of FIG. 2 will be described by taking a read access from the processor 10 as an example. At the time of read access, the processor 10 first accesses the address 3 of the access target to the cache controller 30 via the memory bus 20.
00 is output. The cache controller 30 uses this address 30 in order to determine the cache hit.
0 is decomposed as shown in FIG. The cache hit determination is performed as follows.

(1) Using the value of the index 302 in the access address 300, all the corresponding entries are selected from the tag memory 31. In this example,
Since the value of the index 302 is “000011”, the four entries shown by the thick frame portion 330 in FIG. 3 are selected. In the following description, one index 3
The four entries specified by 02 are called a set.

(2) Using the address comparator 32,
All the tag areas 320 in the four entries selected in (1) are replaced with the tag areas 30 in the access address 300.
Compare with 2. If there is no match, a cache miss will occur.

(3) Check the contents of the valid flag 321 in the entry matched in (2). When the content of this flag is "valid", the cache is hit and the data to be accessed is in the cache memory 40. When the content of this flag is "invalid", a cache miss occurs.

The cache hit determination is performed by the above procedure. When the cache is hit, the cache hit determination signal 34 becomes "hit". At this time, the data signal 311 is connected to the data signal 310 by the selector 33, and the data in the cache memory 40 is read to the processor 10 through this path.
When the cache is missed, the cache hit determination signal 34 becomes "miss", the data signal 312 is connected to the data signal 310 by the selector 33, and the data in the main memory 50 is read to the processor 10 through this path. . The data read from the main memory 50 is
It is also written in the cache memory 40, and at this time, the content of the corresponding entry in the tag memory 31 is also updated. If the content of the valid flag 321 is "invalid" among the four entries specified by the index 302, one entry is updated and the data is stored in the corresponding block of the cache memory 40. Written. When all the valid flags 321 are "valid", it is necessary to select one of them and overwrite it. At this time, as to which entry to be selected for overwriting, "Computer Architecture: Amemiya,
Written by Tanaka (Publishing Office, Ohmsha Co., Ltd., date of issue 1988 8
LRU method, FIFO method, etc. are described in documents such as "March 30th". These methods are considered for a system using a single processor, and in a system using a plurality of processors, giving priority to each processor is not considered.

Further, in the "cache memory control method" of Japanese Patent Laid-Open No. 2-16654, the main memory is divided into a plurality of areas having a fixed size, and the cache memory also has a corresponding size. There is described a method of reducing the frequency of occurrence of cache update when executing a plurality of programs by dividing the program into a plurality of fixed areas.

In the case of the write access, the hit determination and the method of writing to the cache are the same as the read access. However, in the write access, even when the cache is hit, the data is written in the cache memory 40 and the data is also written in the main memory 50.

In this example, since one set consists of four entries, even if the index 302 in the access address 300 is the same, access to four types of addresses with different tag addresses 301 can hit the cache. In this case, the cache is said to be 4-way. The number of ways can take various values other than four. If the other parameters related to the cache are the same, the larger the number of ways, the higher the probability of hitting the cache, and the better the processing performance of the system.

The above description relates to the access from the processor 10, but the same applies to the access from the processor 11.

[0018]

In a multiprocessor system sharing a cache memory, each processor uses the cache memory under the same condition regardless of the priority of the processing being executed. Therefore, depending on the memory access pattern, a large number of cache memories are occupied by a processor executing low-priority processing, and the allocation of cache memory to the processor executing high-priority processing is small. There is a possibility of becoming. In this case, the processor that executes the high-priority processing cannot obtain sufficient processing performance.

[0019]

In order to solve this problem, the present invention stores the identification information of the processor in each entry of the tag memory in addition to the tag address and the valid flag. In addition, a priority table for storing the priority of each processor is provided in the cache controller. From this information, the cache controller checks the priority of the processor being accessed and the usage status of the cache, and controls the cache update method accordingly, so that the processor executing the high-priority processing can obtain many information. Allow cache memory to be allocated.

[0020]

According to the present invention, in a multiprocessor system sharing a cache memory, it becomes possible for a processor executing a high priority process to use a large amount of cache memory.

[0021]

EXAMPLE An example of the present invention will be described with reference to the system configuration example of FIG. In this figure, 10 and 11 are processors, 20 is a memory bus, 30 is a cache controller, 40 is a cache memory, and 50 is a main memory. In this example, the number of processors is two, but it is also possible to use three or more processors. The processor 10 and the processor 11 can execute independent processing. The processors 10 and 11 access the main memory 50 via the memory bus 20. Although the cache memory 40 has a smaller capacity than the main memory 50, it can be accessed at high speed. The normal cache memory 40 stores a copy of part of the data stored in the main memory 50.

FIG. 5 shows an example of the internal configuration of the cache controller 30 used in the present invention. In this figure, 31 is a tag memory for storing information corresponding to each block of the cache memory 40. FIG. 6 shows a configuration example of the tag memory 31 in the present invention. Each entry of the tag memory 31 used in the present invention has a tag address 320, a valid flag 321, and a processor identifier 322 indicating a processor using the entry.
Has an area to store. Reference numeral 32 is an address comparator for comparing a part of the address 300 input from the memory bus 20 with the tag address 320 in the tag memory 31. 33 is a data signal 310 connected to the memory bus 20, a data signal 311 connected to the cache memory 40, and a data signal 312 connected to the main memory 50.
Is a selector for switching and connecting to each other.
Reference numeral 34 is a cache hit determination signal. Reference numeral 35 is a priority table for storing the priority of each processor.

In this example, the cache hit determination uses the same procedure as that described in the conventional example.
Next, a method of updating the cache, which is a feature of the present invention, will be described.

In the priority table 35 in the cache controller 30, the priority of the processor 10 is 3,
A method of allocating the cache memory 40 to each processor will be described by taking the case where the priority of the processor 11 is 1 as an example. Here, it is assumed that the larger the numerical value of the priority table 35, the higher the priority of the corresponding processor.
In this case, the cache memory 40 is the processor 1
It should be assigned to 0 preferentially. This is because the number of cache entries that each processor can use is 3 entries per set by the processor 10.
It is realized by the processor 11 setting one entry per set. Since the number of cache blocks that can be used by each processor is proportional to the number of entries, of the total capacity of the cache memory 40,
3/4 is allocated to processor 10 and the remaining 1/4
Will be assigned to the processor 11. The assignment of the entry is realized by referring to the processor identifier 322 in each entry of the corresponding set when updating the cache and determining the entry to be updated according to this. The procedure for the processor 10 to update the cache is shown in the flowchart of FIG. When updating the cache, it is first checked whether or not an invalid entry exists in the corresponding set (400). If an invalid entry exists, new data is written to this entry (401). If there is no invalid entry, it is checked if there are two or more entries being used by the processor 11 in the corresponding set (410). If there are two or more, one of them is the target of rewriting (41
1). If the number is less than 2, one of the entries being used by the processor 10 is rewritten (41
2). Similarly, the procedure for the processor 11 to update the cache is shown in the flowchart of FIG.

The contents of the processor priority table 35 can be changed even while the system is operating.
In the previous example, when the priority of the processor 11 is changed to 3, the number of entries per set usable by each processor is changed to 2 for both the processor 10 and the processor 11. The procedure for the processor 10 to update the cache in this case is shown in the flowchart of FIG. When updating the cache, first,
It is checked if there is an invalid entry (400). If an invalid entry exists, new data is written to this entry (401). If there is no invalid entry, it is checked whether there are three or more entries in use by the processor 11 in the corresponding set (4
30). If there are three or more, one of them becomes the rewriting target (411). If there are less than two, then one of the entries being used by processor 10 is rewritten (412). Similarly, the procedure for the processor 11 to update the cache is shown in the flowchart of FIG. As a result, the two processors use the entire capacity of the cache memory 40 by 1/2.

Further, as described above, when the priorities of the processors are substantially equal to each other, it is possible to use the conventional method in which the number of entries is not managed for each processor. Furthermore, when the processing priority of a certain processor is very high compared to other processors, it is possible to allocate the entire capacity of the cache memory 40 to that processor.

In the above description, the priority table 35
Although the case where the sum of the numerical values in the above is equal to the number of entries per set of the cache has been described, it is not necessary that this is the case. If they are not equal, a cache having a capacity according to the priority of each processor is assigned to each processor.

In addition to the processor priority, other parameters such as the priority of the process being executed can be used to determine the cache update method.

Further, the valid flag 321 can be omitted by allowing the specific pattern of the processor identifier 322 to express the invalid state of the cache. For example, when the number of processors is 7, processor identifiers “001” to “111” are assigned to each processor and “000” which is not used for processor identification is assigned.
It is possible to configure each entry of the tag memory 31 with only the tag address 320 and the processor identifier 322, as shown in FIG.

Note that these embodiments can also be applied to the control of the secondary cache when some or all of the processors making up the system have the primary cache.

Further, as shown in FIG. 12, the memory bus 2
It is also possible to directly connect the processors 10 and 11 to the cache controller 30 without using 0. In this case, the number of input / output pins of the cache controller 30 increases, but the data transfer bandwidth can be increased.

Further, by consolidating the cache controller 30 and the processors 10 and 11 into one module, it is possible to reduce the power required to drive the signal connecting the two, thereby reducing the system power consumption. Is possible.

Further, when the cache controller 30 and the cache memory 40 are integrated into one module, there are no restrictions on the number of pins of the LSI, so that the number of signal lines for connecting these can be increased.
As a result, the data transfer rate between them can be increased, and the processing capacity of the entire system can be improved.

In the above embodiment, the number of processors is two in order to simplify the description, but the same method can be used when the number of processors is three or more. Is.

[0035]

According to the present invention, in a multiprocessor system sharing a cache memory, a processor executing a high priority process can preferentially use a large number of cache memories.

[Brief description of drawings]

FIG. 1 is a diagram illustrating a configuration example of a multiprocessor system using a cache memory.

FIG. 2 is a diagram showing an example of an internal configuration of a cache controller used in a conventional method.

FIG. 3 is a diagram showing a configuration example of a tag memory used in a conventional method.

FIG. 4 is an explanatory diagram of a method of dividing an access address.

FIG. 5 is a diagram showing an example of an internal configuration of a cache controller used in the present invention.

FIG. 6 is a diagram showing a configuration example of a tag memory used in the present invention.

FIG. 7 is a flowchart showing a cache update method of the processor 10.

FIG. 8 is a flowchart showing a cache updating method of the processor 11.

FIG. 9 is a flowchart showing a cache updating method of the processor 10.

10 is a flowchart showing a cache updating method of the processor 11. FIG.

FIG. 11 is a diagram showing another configuration example of the tag memory used in the present invention.

FIG. 12 is a diagram showing another configuration example of a multiprocessor system using the present invention.

[Explanation of symbols]

10 ... Processor, 20 ... Memory bus, 30 ... Cache controller, 31 ... Tag memory, 32 ... Address comparator, 33 ... Selector, 34 ... Cache hit determination signal, 35 ... Processor priority table, 40 ... Cache memory, 50 ... Main memory, 320 ... Tag address, 32
1 ... Valid flag, 322 ... Processor identifier.

Claims (7)

[Claims] 1. In a system including at least two or more processors, a cache memory shared by them, a main memory, and a control circuit for controlling them, depending on the priority of processing executed by each processor. By dynamically changing the capacity of the cache memory allocated to each processor, it is possible to allocate a large amount of cache memory to the processor that is executing a high priority process. Memory control method. 2. In a system including at least two or more processors, a cache memory shared by them, a main memory, and a control circuit for controlling them, according to the priority of processing executed by each processor. , A memory control method characterized in that the number of cache entries that can be used by each processor can be dynamically changed in order to change the capacity of the cache memory allocated to each processor. 3. In a system in which a plurality of processors share a cache memory, the capacity of the cache memory assigned to each processor can be changed according to the priority of the processing executed by each processor. A cache memory controller characterized in that it has means for storing the priority of the connected processor. 4. A processor module in which the controller and the processor of the cache memory according to claim 3 are integrated into one. 5. In a system in which a plurality of processors share a cache memory, the capacity of the cache memory assigned to each processor can be changed according to the priority of the processing executed by each processor. For this reason, the tag memory is characterized in that for each cache entry, information for identifying the processor using the entry is also stored. 6. A cache memory controller having the tag memory according to claim 5 built therein. 7. A memory module in which the controller of the cache memory according to claim 6 and the cache memory are integrated into one.