JP2001290704A - Device and method for controlling multiprocess - Google Patents

Abstract

PROBLEM TO BE SOLVED: To avoid the decrease of the use efficiency of a cache memory and the decrease of a cache hit ratio by a plurality of processes in which priorities are set. SOLUTION: This controller is provided with a processor (1) managing the plurality of processes in which the priorities are set, a main storage device (6) shared by the plurality of processes, the cache memory (2) where the data of the storage device (6) are copied and which also consists of blocks monopolized by the plurality of processes, and a cache management table (10) representing a process monopolizing blocks in each of a plurality of blocks and also the priority of the process monopolizing the blocks, and in the case a cache error of a new process whose priority is higher than the priority represented by the table (10) takes place, the processor (1) releases the block monopolization by any of blocks whose priority is lower than the priority and sets block monopolization by a new process.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a multi-process control device having a cache memory shared by a plurality of processes.

[0002]

2. Description of the Related Art In computer systems, the operating speed of microprocessors has been increasing day by day. In such a system, an inexpensive and large-capacity main storage device is used. Generally, the main storage device comprises a low-speed memory. A low-speed memory cannot follow the access speed of a microprocessor that operates at a high speed. In order to increase the program execution speed of the microprocessor, a small-capacity high-speed cache memory is provided between the microprocessor and the main storage device.

In a computer system equipped with a cache memory, frequently accessed data and recently used data are stored in the cache memory. As the probability of a cache hit to the cache memory increases, the frequency of access to a slow main storage device decreases. When the frequency of access to the main storage device is reduced, the program execution speed of the microprocessor is improved, and as a result, the efficiency of processing by the computer system is improved.

A data word or an instruction word is stored in the cache memory. Each time an access to the main storage device occurs, it is checked whether desired data (desired instructions) is stored in the cache memory. If desired data (desired instruction) is stored (cache hit),
The data is read. In this case, the read processing for the main storage device is not executed. If the desired data is not stored (cache miss), the data is read from main storage. When the cache memory has a free area, the data read from the main storage device is written to the free area. If there is no free area in the cache memory, replacement with existing information (replacement) is performed.

Here, access of a general cache memory will be described. FIG. 6 shows the concept of general cache memory access. There are various cache memory access methods. Here, the set associative method will be described as an example.

[0006] The computer system 50 shown in the figure.
Is a 4-way set associative system. The system includes a processor (CPU) 51, a cache memory 52, an index unit 53, a comparator 54, a selector 55, a main storage device 56, a registration qualification setting unit 57, a process priority unit 58, A registration eligibility determination unit 59 and a block selection unit 60 are provided. The cache memory 52 includes four blocks. Comparator 54
And the registration qualification setting unit 57 determines whether
It has a step configuration.

[0007] The index section 53 forms a part of the address of the main storage device 56. The index represented by the index unit 53 represents an address (element address) in a block of the cache memory 52.

When main memory data is written (registered) in the cache memory 52, an element address of a block is specified by a part (index) of an address (main memory address) of the main memory. On the other hand, the block selecting means 6
0 selects a block of the cache memory 52 to be accessed. In the block selected by the block selecting means 60, main storage data is registered in the element block indicated by the index. At the time of this registration, a part of the main storage address not used for specifying the element address is stored together with the main storage data. By this storage, the contents of the cache memory 52 and the main storage data are associated one-to-one.

[0009] The area of the cache memory 52 for storing main storage data is called a data section. Similarly, an area in which a part of the main memory address that is not used for specifying the element address is stored is called a tag part.

After the main memory data is registered in the cache memory 52, when an access to the main memory data occurs, an index which is a part of the main memory address is used as an element address. The tag part is specified by the element address. The tag read from the tag section is compared in the comparator 54 with the rest of the main memory address.
If the result of the comparison indicates a match, the data is read from the data portion and transferred to the processor 51 via the selector 55. The time required to read data from the cache memory 52, which can operate at a higher speed than the main storage device, is equal to that of the main storage device 56.
Is significantly shorter than when you access.

In the above-described processing relating to the cache memory 52, the amount of data that can be registered is limited according to the number of blocks in the cache memory 52. That is, the number of registered main storage data having the same contents of a part (index) of the main storage address is limited to the number corresponding to the number of blocks. New main storage data exceeding the number of blocks is replaced with registered main storage data. At this time, in the cache memory, main storage data (low-frequency data) that is used less frequently or main storage data that has not been accessed for a long time (past data) are evicted from the cache memory. It is desirable that the low-frequency data and the past data are left in the cache memory when the data is referred to by a process with a high priority. The priority of a process becomes a problem when, for example, an operating system (UNIX: registered trademark) capable of time-division multiplexing a plurality of processes and performing parallel processing is used. In a multi-process control device equipped with this operating system, the priority of a process is set according to the importance of a process. The execution speed of a process changes according to the priority of the process.

A technique relating to a cache memory in which the priority of a process is considered is disclosed in, for example, Japanese Patent Application Laid-Open No. 9-282226.
No. 6,086,045. This technique will be described with reference to FIG. The registration qualification setting unit 57 of the computer system 50
The range of the priority of the process permitted to register the main storage data is held. The process priority setting unit 58 sets the priority of a process that is to execute main memory access. The registration qualification judging means 59 includes the process priority setting unit 5
Then, the priority set to 8 and the priority held in the registration qualification setting unit 57 are compared to determine a block in which the main storage data is to be written. The determination is performed when the main storage data to be accessed by the process is not registered in the cache memory 52. Block selecting means 60
Selects a block for registering main storage data.

It is assumed that “0”, “2”, “5”, and “7” are set as registration permission priorities in registration qualification setting section 57. The registration permission priority increases as the value decreases. In this case, “0” represents the highest priority.

When the main memory access data is registered in the cache memory 52 (cache hit), the data is read from the cache memory 52 and transferred to the processor 51 via the selector 55 as in a general memory. .

Here, it is assumed that there is no free area in the block of the cache memory 52. That is, when new main storage data is registered, any of the main storage data is evicted from the cache memory 52.

When a process to which the priority "0" is set accesses the access address section (main storage address) 51a, it is searched whether or not the main storage data required by the process is registered in the cache memory 52. . If the main storage data has not been registered, the main storage data is newly registered in the cache memory 52. Prior to the registration of the main storage data, the contents of the registration qualification setting unit 57 and the contents of the process priority setting unit 58 are compared in the block selection unit 60. In this case, the content of the process priority setting unit 58 indicates the priority “0”. The contents of the registration qualification setting unit 57 indicate “0”, “2”, “5”, and “7”. The registration qualification determination unit 59 executes a determination indicating registration permission for all four blocks. The block selecting means 60 selects a block to be registered from the blocks permitted to be registered. In this case, all four blocks are to be selected. The block selecting unit 60 selects a block by focusing on the use frequency and the access frequency in addition to the process priority.

In the block selected by the block selecting means 60, the main storage data is updated, ie, the main storage data is evicted and registered.

If the main memory data required by the process of the priority "3" is not registered in the cache memory 52, the registration qualification judging means 59 determines whether the block having the priority "5" or "7" is set. Perform a determination indicating registration permission. The block selecting means 60 selects a block to be registered from the two blocks permitted to be registered. New main storage data is registered in the selected block.

The above processing is executed to improve the frequency of cache hits for a process with a high priority.

The general technique relating to the operation of the cache memory is described in Japanese Patent Laid-Open No.
0158, JP-A-7-84887, JP-A-9-101916, and JP-A-10-8334
No. 9 discloses this.

[0021]

For example, when a plurality of priorities are set in one block, the main memory data of the process with the higher priority is evicted from the cache memory 52, and the main memory of the process with the lower priority is removed. A situation occurs in which data is registered in the cache memory 52. In this case, a cache miss occurs in a high-priority process, and the execution time of the process is prolonged.

When one priority is set for one block, blocks must be provided in accordance with the number of priorities. As the number of blocks increases, the sizes of the registration qualification setting unit 57 and the comparator 54 increase, and the configurations of the registration qualification determination unit, the block selection unit, and the selector become complicated.

Further, even if an empty area exists in the block,
If the priority of the process is lower than the priority set for the block, the process cannot register the main storage data in the empty area. In other words, the effective use of blocks has been hindered.

When a plurality of processes having the same priority operate, it is expected that the main storage data will be registered in the blocks alternately. In this case, the cache hit rate of the cache memory 52 decreases, and as a result, the execution speed of the process decreases.

An object of the present invention is to provide a multi-process control device and a multi-process control method which can avoid a decrease in the use efficiency of a cache memory and a decrease in a cache hit rate by a plurality of processes for which priorities are set. And

[0026]

Means for solving the problem are described as follows. The technical items appearing in the expression are appended with numbers, symbols, etc. in parentheses (). The numbers, symbols, etc. are technical items that constitute at least one embodiment or a plurality of examples of the embodiments or examples of the present invention, in particular, the embodiments or the examples. Corresponds to the reference numerals, reference symbols, and the like assigned to the technical matters expressed in the drawings corresponding to the above. Such reference numbers and reference symbols clarify the correspondence and bridging between the technical matters described in the claims and the technical matters of the embodiments or examples. Such correspondence / bridge does not mean that the technical matters described in the claims are interpreted as being limited to the technical matters of the embodiments or the examples.

The multi-process control device according to the present invention comprises:
A processor (1) that manages a plurality of processes for which priorities have been set; a main storage device (6) shared by the plurality of processes; data in the main storage device (6) are copied; A cache memory (2) composed of a plurality of blocks occupied by a plurality of blocks, and a cache management table (10) representing, for each of the plurality of blocks, a process occupying the block and indicating a priority of the process occupying the block. The processor (1), when a cache miss of a new process higher than the priority indicated by the cache management table (10) occurs, occupies the block by any process of lower priority than the priority. Release and set block occupancy by new process.

[0028] A further multi-process control device according to the present invention is that, when the processor (1) executes the release of the exclusive use of a block, the contents of the released exclusive use block are maintained, and the exclusive use release block is maintained. A further multi-process control device according to the present invention that updates only the area related to the new registration when a new registration occurs in the processor (1) refers to a block in which the index generated when the processor (1) refers to the cache memory is It comprises a block ID to be specified and an element address to specify a predetermined area in the block.

In a further multi-process control device according to the invention, the priority represents the operation priority of the process.

In a further multi-process control device according to the invention, the priority represents a cache memory access priority of the process.

In a further multi-process control device according to the invention, the priority represents a main storage access priority of the process.

The multi-process processing method according to the present invention comprises:
Priorities are set for a plurality of running processes, the processes occupying the cache memory (2) and the priorities of the processes are registered in the cache management table (10), and a new process for accessing the cache memory (2) occurs. In this case, with reference to the cache management table (10), any process having a lower priority than the priority of the new process is detected, and instead of registration in the cache management table (10) relating to any process. Thus, registration relating to the new process is executed, and the new process occupies the cache memory (2) instead of any of the processes.

In a further multi-process control method according to the present invention, the contents of the registration area of the cache memory (2) occupied by any process are maintained until the contents are updated by new registration by a new process. .

In a further multi-process control method according to the present invention, when an update of the cache management table (10) relating to a new process is executed, data relating to the new process is registered in the cache memory.

[0035]

FIG. 1 shows the concept of a multi-process control device according to the present invention. The multi-process control device 100 shown in the figure includes a processor (CPU) 1, a cache memory 2, an index unit 3, a comparator 4, a selector 5, a main storage device 6, a block ID (IDentifi
cation) unit 7. The processor 1 includes an access address unit 1a.

The processor 1 executes multi-process processing. The access address section 1a is a storage area in which a main storage address (access address) referred to when accessing the main storage device 6 is stored. The upper bits of the access address are supplied to the cache memory 2 and the comparator 4 via the path B1. The lower bits of the access address are supplied to the index unit 3 in the lower order of the path B2. The contents of the block ID section 7 are supplied to the index section 3 via the path B3. The contents of the tag section are supplied to the comparator 4 via the path B4. The data section is connected to the selector via the path B5. The main storage device 6
It is connected to the selector 5 via the path B6. Selector 5
Is connected to the processor 1 via the path B7.

The upper bits of the access address are used to determine whether data stored in the cache memory is valid. The lower bits of the access address are
Used to specify cache memory elements. The lower bits of the access address are
Used as lower data of the index. The content (ID) of the block ID section 7 is used to specify a block in the cache memory 2. The ID is used in the index unit 3 as higher-order data of the index. The index is used to specify a block of the cache memory and its element address.

The comparator 4 compares the contents of the upper bits of the access address with the contents of the tag portion, and notifies the selector 5 of the comparison result. When the selector 5 receives the match notification from the comparator 4, the selector 5 sets the path B5 to valid. When the selector 6 receives the mismatch notification from the comparator 4, the selector 6
Set 6 to valid. The selector 5 outputs the cache memory 2 or the main storage device 6 to the processor 1.

Here, the index according to the present invention will be described with reference to FIG. FIG. 2 illustrates the concept of an index according to the present invention. The figure shows the relationship among the cache memory 2, the access address part 1a, the index part 3, and the block ID part 7 shown in FIG.

The access address section 1a has upper bit 1
b and the lower bit 1c. The cache memory 2
It comprises a tag section 2a and a data section 2b. Index part 3
Consists of upper data 3a and lower data 3b.

An access item composed of a pair of the tag section 2a and the data section 2b is specified by an 11-bit index. The upper three bits of the index are used to specify a block. The lower 8 bits of the address are used to specify an access item. The index is stored in the index section 3. Top data of index 3
“a” corresponds to the content of the block ID section 7. The lower data 3b of the index corresponds to the lower data of the access address section 1a.

When an access to the cache memory 2 occurs, the contents of the lower bit 1c of the access address section 1a and the contents of the block ID section 7 are transferred to the index section 3. The cache memory 2 is accessed with reference to the contents of the index unit 3, that is, the index. The contents of the upper bits 1b of the access address section 1a are compared with the contents of the tag section 2a as tag data.

The multi-process control device 100 according to the present invention
, One process is assigned to one block. That is, an operation situation in which one block is shared by a plurality of processes does not occur.

FIG. 3 shows the configuration of the cache management table 10 according to the present invention. Cache management table 10
Is provided, for example, in the processor 1. The cache management table 10 has a configuration in a case where the cache memory 2 includes eight blocks. First to eighth data 11 to 18 are provided corresponding to the number of blocks. The cache management table 10 includes a flag item 10a, a process ID item 10b, and a cache use priority item 10c.
And a block ID item 10d.

The flag item 10a indicates a block in use. When the content is "1", it indicates that the device is in use. The process ID item 10b indicates a process that is using a block. The cache priority item 10c indicates the priority of the process using the block. The block ID item 10d represents a corresponding block.

The first data 11 represents data relating to block 0. The second data 12 represents data relating to the block 1. The third data 13 represents data on the block 2. The fourth data 14 represents data on the block 3. The fifth data 15 represents data relating to the block 4. The sixth data 16 represents data on the block 5. The seventh data 17 represents data on the block 6. The eighth data 18 represents data on the block 7.

The figure shows a case where the blocks 6 and 7 are not used. For an unused block, the cache priority item 10c includes, for example, “25, which is the lowest priority”.
Represents 5 ".

Here, the operation of the multi-process control device 100 according to the present invention will be described with reference to FIGS. FIG. 4 shows a flowchart according to the present invention.

In FIG. 4, when the execution process is switched while the multitask OS is running, the processor 1
With this control, the context of the running current process is saved in the save area (S1). Next, it is determined by the processor 1 whether or not the process switching accompanying the termination of the current process has occurred (S2). For termination of the current process,
The processor 1 refers to the cache management table 10 and clears the display on the current process (S3). By executing step S3, the block occupied by the current process is released.

Next, the next process to be executed next is selected by the scheduler function of the multitask OS. The processor 1 refers to the cache management table 10 and
The cache use status of the next process is determined (S4). The determination is made with reference to the process ID item 10b. If the next process does not use the cache memory 2, the processor 1 refers to the cache management table 10 and detects an unused cache block (S5). The detection is performed with reference to the in-use flag item 10a. If there is no unused cache block, the processor 1 refers to the cache management table 10 and detects a lower priority than the next process. The detection is performed in the cache priority item 1
0c. When a priority lower than the priority of the next cache is detected, the processor 1 executes a process of releasing a block used by a process with a lower priority set (S6).

After generating the open block, the processor 1 allocates the open block to the next process. That is,
The processor 1 determines an item related to an open block in the cache management table 10, that is, a cache use priority item 1
The processor 1 registers the priority of the next process in 0c, and further registers the data of the next process in the items related to the open blocks, that is, the in-use flag item 10a and the process ID item 10b (S7). Thereafter, the processor 1 stores the value of the block ID item 10d of the cache block used by the next process in the block I.
It is set in the D section 7 (S8). Then, the context related to the next process is restored (S9), and the process ends. During the execution of steps S6 and S7, a process of registering data relating to the next process in the opened block may be executed. In this case, the next process can make a cache hit at the same time when the registration in the cache management table 10 is completed.

If the determination in step S4 is YES, the process proceeds to step S8. If YES is determined in step S5, the process proceeds to step S7.

Further, if a process having a lower priority than the next process cannot be detected in step S6, the use of the cache memory 2 by the next process is avoided. If a process having a lower priority than the next process cannot be detected and a process having the same priority as the next process is detected, a block is used based on information such as access frequency in addition to the priority. The process is determined.

In the present invention, one block is allocated to one process. At this time, the contents of the cache memory 2 are not cleared. When new data is registered in the cache memory 2, only the area related to the registration is updated, and the other area retains past data. Therefore, when a process that has once released a block uses the same block again, there is a possibility that data registered in the past by that block remains. This is because the past registration status remains unless new registration is executed. For this reason, the effect of reducing the frequency of cache misses at the time of resuming the use of the block is also obtained.

As described above, in the multi-process control device according to the present invention, the allocation block is switched in block units in consideration of the priority of the process in accordance with the switching of the execution process. For this reason, the frequency with which the high-priority process uses the cache memory 2 improves, and as a result, the frequency with which a cache miss occurs in the high-priority process decreases.

In the present invention, the priority of a process may be replaced by the priority indicating the access order of the cache memory, the priority indicating the access order of the main storage device, or the like, in addition to the priority of the process itself.

In the present invention, the priority of a process may be appropriately changed according to, for example, the operating rate of a cache memory. In this case, for example, the priority of a process in which cache misses frequently occur is raised, and the priority of a process in which cache misses are small is lowered. In this case, a function of collecting the frequency of cache miss as statistical data is added.

The multi-process control device according to the present invention is not limited to the direct mapping method shown in FIG. 1, but can be applied to, for example, 2-way and 4-way set associative methods.

An embodiment of the 4-way set associative system according to the present invention will be described with reference to FIG. FIG. 5 illustrates the concept of another multi-process control device according to the present invention. The four-way set associative method is applied to the multi-process control device 101 shown in FIG. The multi-process control device 101 includes a processor (CP
U) A first, fourth to fourth cache memories 21 to 24, an index unit 3, a comparator 4, a selector 5, a main storage device 6, and a block ID unit 7. Processor 1
Has an access address section 1a. The comparator 4 has a four-stage configuration corresponding to the first to fourth cache memories 21 to 24.

The processor 1 performs multi-process processing. The access address section 1a is a storage area in which a main storage address (access address) referred to when accessing the main storage device 6 is stored. The upper bits of the access address are supplied to the first to fourth cache memories 21 to 24 and the comparator 4 via the path B1. The lower bits of the access address are supplied to the index unit 3 in the lower order of the path B2. The contents of the block ID section 7 are supplied to the index section 3 via the path B3.
The contents of the tag section are supplied to the comparator 4 via the path B4. The data section is connected to the selector via the path B5. The main storage device 6 is connected to the selector 5 via the path B6. The selector 5 is connected to the processor 1 via the path B7.
Connect to

The upper bits of the access address are used to determine whether the data stored in the cache memory is valid. The lower bits of the access address are
Used to specify cache memory elements. The lower bits of the access address are
Used as lower data of the index. The contents (ID) of the block ID section 7 are used to specify blocks in the first to fourth cache memories 21 to 24. Its ID
Are used as upper data of the index in the index unit 3. The index is used to specify a block of the cache memory and its element address.

The comparator 4 compares the contents of the upper bits of the access address with the contents of the tag portion, and notifies the selector 5 of the comparison result. When the selector 5 receives the match notification from the comparator 4, the selector 5 sets the path B5 to valid. When the selector 6 receives the mismatch notification from the comparator 4, the selector 6
Set 6 to valid. The selector 5 outputs the first to fourth cache memories 21 to 24 or the main storage device 6 to the processor 1.

The first to fourth cache memories 21 to 24
For example, it is appropriately selected according to the process to be executed. The number of cache memories is set in advance according to, for example, the number of processes to be executed. The configuration of the comparator 4 is increased or decreased according to the number of the first to fourth cache memories 21 to 24. Further, the selector responds to the output of the comparator 4 by
The first to fourth cache memories 21 to 24 connected via the path B5 are selected.

The processing for each cache memory of the multi-process control device 101 is the same as the processing described above with reference to FIGS. Here, a process of selecting the first to fourth cache memories 21 to 24 and selecting a cache memory to be connected to the main storage device 6 when a cache miss occurs is newly added. This process is the same as the content executed in the conventional general multi-way set associative system.

The multi-process control device according to the present invention
With the switching of the process that exclusively uses the cache memory, it is possible to avoid a situation where a cache miss frequently occurs in a process with a high priority.

Further, a process in which the exclusive use of the cache memory is once released and the exclusive use of the cache memory is set again causes a cache hit to data registered in the cache memory in the past. At this time, the situation of repeating cache miss is avoided.

When the number of running processes increases,
By adjusting the value indicating the priority, the priority of each process can be made different. In this case, a burden such as an increase in circuit scale does not occur.

When the availability of the cache memory is set for each process, a process occurs in which the cache memory cannot be occupied even though the cache memory is empty. In the present invention, since the order in which the cache memory is occupied is set according to the priority, even if the process has a low priority, the cache memory can be occupied if the cache memory is free, and the execution efficiency can be improved. Can be.

The release of the exclusive use of the cache memory is executed only by the operation of clearing the contents of the cache memory management table. For this reason, the data of the main memory relating to the new process can be registered in the cache memory at the same time as the exclusive release of the cache memory and the exclusive setting. In this case, a cache miss of a new process can be prevented.

[0070]

According to the multi-process control apparatus and the multi-process control method of the present invention, it is possible to avoid a decrease in the use efficiency of the cache memory and a decrease in the cache hit rate due to a plurality of processes for which priorities are set. For this reason, it is possible to avoid a situation where the execution speed of the process with a high priority is reduced due to the processing related to the cache memory.

[Brief description of the drawings]

FIG. 1 is a conceptual diagram of a multi-process control device according to the present invention.

FIG. 2 is a conceptual diagram of an index according to the present invention.

FIG. 3 is a configuration diagram of a cache management table according to the present invention.

FIG. 4 is a flowchart according to the present invention.

FIG. 5 is a conceptual diagram of another multi-process control device according to the present invention.

FIG. 6 is an access conceptual diagram of a general cache memory.

[Explanation of symbols]

 1: Processor 2: Cache memory 2a: Tag section 2b: Data section 3: Index section 4: Comparator 5: Selector 6: Main storage device 7: Block ID section 10: Cache management table

Claims (9)

[Claims] 1. A processor for managing a plurality of processes for which priorities have been set; a main storage device shared by the plurality of processes; data in the main storage device being copied; A cache memory composed of a plurality of occupied blocks; and a cache management table representing, for each of the plurality of blocks, the process occupying the block, and indicating the priority of the process occupying the block. When a cache miss of a new process higher than the priority indicated by the cache management table occurs, the processor releases the exclusive use of the block by any of the processes of the priority and executes the process by the new process. A multi-process control device for setting exclusive use of the block. 2. The multi-process control device according to claim 1, wherein, when the release is executed, the processor maintains the contents of the block whose exclusive use has been released, and the block whose exclusive use has been released. A multi-process control device that updates only an area related to the registration when a new registration occurs in the multi-process control apparatus. 3. The multi-process control device according to claim 1, wherein an index generated when the processor refers to the cache memory includes a block ID specifying the block, and a predetermined ID in the block. A multi-process control device consisting of element addresses that specify an area. 4. The multi-process control device according to claim 1, wherein the priority indicates an operation priority of the process. 5. The multi-process control device according to claim 1, wherein the priority indicates a cache memory access priority of the process. 6. The multi-process control device according to claim 1, wherein the priority indicates a main storage device access priority of the process. 7. A priority is set for a plurality of running processes, the process exclusively occupying the cache memory and the priority of the process are registered in a cache management table, and a new process for accessing the cache memory is generated. In this case, referring to the cache management table, any process having a lower priority than the priority of the new process is detected, and instead of registering any of the processes in the cache management table, A multi-process control method in which registration relating to the new process is executed, and the new process occupies the cache memory instead of any of the processes. 8. The multi-process control method according to claim 5, wherein the contents of the registration area of the cache memory occupied by any of the processes are updated by new registration by the new process. Multi-process control method maintained. 9. The multi-process control method according to claim 7, wherein when updating of the cache management table relating to the new process is performed, data relating to the new process is registered in the cache memory. Multi-process control method.