JP2742245B2 - Parallel computer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-processor parallel computer comprising an arithmetic processing unit comprising a plurality of arithmetic processors, a main storage unit, a communication register unit, and an interconnection network connecting these units. .

[0002]

2. Description of the Related Art In a parallel computer comprising a plurality of arithmetic processors, a storage device having an access time faster than a main storage device, or a storage device having an access throughput higher than a main storage device; Alternatively, by providing a storage device having both advantages, a shared variable for synchronization control, exclusive control, and communication control between the processors is assigned to the storage device, and each arithmetic processor is assigned to the storage device. By accessing,
The processing time of the above control can be reduced. For example, a read / shared variable between two arithmetic processors
When communication is performed via the write processing, the communication processing can be executed at a higher speed through a storage device having a shorter access time than through the main storage device. This storage device is hereinafter referred to as a communication register.

[0003] These synchronous control, exclusive control, and communication control are controls in which parallel execution is not sufficiently performed in parallel processing executed by a parallel computer.
The effect of these controls on overall performance is very large. Therefore, the effect of the communication register configuration aimed at reducing the processing time of such control on the performance improvement of the parallel computer is very large.

[0004] Usually, a communication register is used by dividing the communication register into a set including a plurality of words.
One set is assigned to one process.
However, the process here is one processing unit that is divided into a plurality of units and includes units (called threads) that are executed in parallel. One thread is executed in any of the arithmetic processors, and a plurality of threads are simultaneously executed in parallel by a plurality of arithmetic processors. The usage of a plurality of words in a set is defined by each program.For example, one word is used as a lock flag for exclusive control, and another word is used as a counter for synchronous control. Used. Further, when a process requires only one set of communication register words, a plurality of sets may be assigned to the process.

When a process starts executing, it requests the operating system (OS) to set a communication register. The OS gives a set to the process in response to the request. In effect, we will give that set number to the process. When the process receives the set usage right, it performs various settings and starts parallel execution. After the end of the parallel execution, the OS is notified to that effect and the used set is released.

[0006]

In the above-described conventional parallel computer with a communication register device, the number of words in the communication register is determined by a logical value in order to obtain a high-speed access time and a high throughput performance as compared with the main storage device. Due to restrictions on the circuit configuration, the capacity must be reduced.

However, in a processing environment in which the number of arithmetic processors of a parallel computer is large and a large number of processes are executed in parallel, a large number of communication registers are required. Therefore, if the number of processes to be executed in parallel exceeds the number of sets, the execution of the process is delayed due to the exhaustion of the number of sets. Also, if the process requires multiple sets, the situation is even worse.

One reason why the communication register set is depleted in the highly parallel state is as follows. Each arithmetic processor executes different processes at the same time in parallel by the time-sharing process, but actually, only one process is executed at a certain time. At this time, the other processes are suspended due to waiting for I / O synchronization or synchronization with another processor. When a certain process is suspended, the time sharing process control unit of the operating system switches to another executable process.
However, it is necessary to secure the communication register set area of the suspended process. Of course, it is possible to perform a process of temporarily saving the communication register set area in a memory or the like when the idle process is switched. However, in such a process switching process, the switching overhead may become extremely large. is there.

[0009]

According to the present invention, there is provided a parallel computer comprising:
An arithmetic processing unit including a plurality of arithmetic processors, a main storage device, and a communication register device including a plurality of storage words for performing synchronization control, exclusive control, and communication control among the plurality of arithmetic processors. In a multi-processor parallel computer connected by an interconnection network, each arithmetic processor sends a communication register word in a communication register device from a logical communication register address specified by a communication register word in a program executed by the arithmetic processor. A communication register address conversion table for converting to a specified physical communication register address is provided, and each of the arithmetic processors, when the communication registers are exhausted,
It is characterized in that it has a function of temporarily swapping out a communication register set that is hardly used to a main memory.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 shows a schematic configuration of a parallel computer having a communication register device to which the present invention is applied. 10, 1
1... 1n each arithmetic processor, 2 a main storage device, and 3 a communication register device. 4 is an arithmetic processor 10,
11 ... 1n, an interconnection network connecting the main storage device 2 and the communication register device 3 is shown. Each arithmetic processor 10, 1
When 1... 1n perform main memory access or communication register access, the request is sent to the interconnection network 4, and the interconnection network 4 receives a plurality of requests sent from a plurality of arithmetic processors. The contention is arbitrated, and the request is routed to the main storage device 12 or the communication register device 3 requested by the request. Main storage device 2,
The request arriving at the communication register device 3 is subjected to a read access process and a mosh write access process in each device. In the case of read access, read data is returned to the arithmetic processor via the interconnection network 4 again.

The communication register device 3 includes a communication register composed of a plurality of words and a control unit for controlling access to the communication register. The communication register is assigned an address number continuously from address 0. Hereinafter, the address assigned to this communication register word is called a physical address. The physical address is logically divided into two fields, the upper field is called a physical set number, and the lower field is called an offset within a set. For example, if a physical address having a physical set field of n bits and an offset within the set of m bits is composed of a total of (n + m) bits, the number of physical sets is 2 n and the number of words in the set is 2 m (N +
m) The communication register is composed of the power words. In the communication register access from the arithmetic processors 10 to 1n, by specifying a physical address,
The word of the communication register to be accessed can be determined.

FIG. 3 shows an instruction format of a communication register access instruction. The communication register instruction includes an operation code field 201 and an operand field.
The operand field further includes a first operand field 202 for specifying a scalar register number and a second operand field 203 for specifying a communication register address.
It is composed of In the case of load access, the value stored in the communication register word specified in the second operand field
Transfer to the scalar register specified by. In the case of store access, the relationship between the source and the destination is reversed.

The address specified in the second operand field 203 is called a logical address. Logical addresses can be divided into logical set numbers and offsets within sets. Here, the logical set number has an n'-bit configuration, the offset in the set has an m-bit configuration, and the logical address has a total (n '+ m) -bit configuration. Therefore,
The logical communication register space is such that the number of logical sets is 2 and n '
The number of words in the set and the number of words in the set are 2 to the power of m, for a total of 2
+ M) to form a logical space.

Here, the relationship between the logical communication register address and the physical communication register address will be described. The offset in the set of the logical communication register address and the offset in the set of the physical communication register address are the same m bits, that is, the number of words in the set is the same 2 m words.
The set number is n '> m. That is, the number of sets in the logical communication register address space is larger than the number of sets in the physical communication register address space.

The request flowing through the interconnection network 4 includes an access type field indicating whether the access destination is the main storage device 2 or the communication register device 3, a code field indicating whether the access is a load or a store, and a word to be accessed. And a write data field.
The physical address field is further divided into a set number and an offset within the set, and the set number and the offset within the set for the communication register accessing each are stored. In the case of load access, read data flows as a reply through the interconnection network 4 in the reverse direction.

In the communication register device 3, when a request is received from the interconnection network 4, the contents of the communication register specified by the set number and the offset in the set indicated by the address field and the contents indicated by the code field are set. If the data is stored, the value of the data field is written in the word. If the data is loaded, the contents of the word are written, and this is configured as the data field of the reply and transmitted to the interconnection network 4.

FIG. 1 shows an embodiment of the present invention, and shows a configuration of an address conversion unit provided in each of the arithmetic processors 10 to 1n. The address conversion unit includes a conversion table 301 including a plurality of entry words, a logical set register 302, a logical offset register 303,
Physical set register 304, physical offset register 3
07, decision unit 308, logical communication register address register 309, and physical communication register address register 310
Having. Each entry of the conversion table 301 is a physical address field 3 in which a physical communication register set number is entered.
12. UA field 311 indicating whether a logical address to be accessed is mapped on a physical address
Consists of The UA field 311 has a length of 1 bit, which means that AVAILABLE means that the data is mapped, and that UAVAILABLE means that the data is not mapped.

The address conversion unit includes arithmetic processors 10 to 10
The communication register access issued by 1n is converted from a logical set number to a physical set number. To do so, the entry at the address indicated by the logical set number is selected and its contents are read. The read entry is stored in the physical set register 304.

At this time, the UA field 305
If it is LABLE, the physical set number field 306
However, the physical set number shown is valid. Therefore, by linking this physical set number as the upper field and the offset in the set as the lower field,
The physical address of the communication register is generated. Once the physical address is generated, this access is configured as a communication register access request and sent out to the interconnection network 4 to reach the communication register device 3.

On the other hand, if the UA field 305 is UNAVA
In the case of IABLE, it means that the communication register indicated by the logical address is not mapped on the physical communication register, and thus the determiner 308 notifies the arithmetic processor control unit of this as an interrupt. Upon receiving this interrupt, the arithmetic processor control unit temporarily suspends the process currently being executed, and starts executing an interrupt process for the process.

The interrupt process is a process of swapping the contents swapped out in the main memory without being allocated to any word of the communication register.
At this time, there are several methods of selecting a word to be swapped in. For example, there is a method of selecting a least used word. Further, an extended storage device may be selected as a swap-out destination. This swap-out / swap-in processing is the simplest way for the operating system to perform the processing in software, but a configuration that supports these functions in hardware is also conceivable.

When the swap-in is completed, the physical address value of the swapped-in communication register is updated in the physical address field 312 of the entry indicated by the logical address in the conversion table 301. Thereafter, the interrupt processing ends, and the program is re-executed from the point before the interrupt. The access to the communication register that caused the interrupt is converted again by the address conversion unit. Since the physical address can be obtained by AVAILABLE in the future, the communication register access can be completed.

[0024]

According to the present invention, by adopting the above configuration, it is possible to make the communication register capacity usable as a system larger than the physically prepared communication register capacity. Therefore, it is possible to reduce the hold state of the process input due to the exhaustion of the communication register,
This contributes to improving the system throughput on a parallel computer.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a schematic configuration diagram of a parallel computer to which the present invention is applied.

FIG. 3 is a diagram showing a format of a communication register access instruction used in the present invention.

[Explanation of symbols]

 10-1n Arithmetic processor 2 Main storage device 3 Communication register device 4 Interconnection network 201 Opcode field 202 First operand field 203 Second operand field 301 Conversion register 302 Logical set register 303 Logical offset register 304 Physical set register 305, 311 UA field 306 Physical set number field 307 Physical offset register 308 Judge 309 Logical communication register address register 310 Physical communication register address register 312 Physical address field.

Claims (3)

(57) [Claims] An object of the present invention is to execute an arithmetic processing device including a plurality of arithmetic processors, a main storage device, a synchronization control, an exclusive control, and a communication control among the plurality of arithmetic processors.
In a multiprocessor parallel computer in which a communication register device composed of a plurality of storage words is connected by an interconnection network, a logical communication register specified by a communication register word in a program executed by the arithmetic processor is assigned to each arithmetic processor. A communication register address conversion table for converting an address to a physical communication register address designating a communication register word in the communication register device is provided, and each of the arithmetic processors is almost unused when the communication register is exhausted. A parallel computer having a function of temporarily swapping out a communication register set to a main memory. 2. The parallel computer according to claim 1, wherein the objects to be swapped out are individual communication register words. 3. The parallel computer according to claim 2, wherein a swap-out destination of said communication register is an extended storage device.