JPH04111153A - Information processor - Google Patents

Abstract

PURPOSE:To attain an access to a memory area which is controlled by another processor by making each processor perform the conversion of addresses by mutual reference to a mapping table. CONSTITUTION:The 384K - 512K byte addresses of a memory area are assigned to a processor PC 10b in its active state. Meanwhile the 512K - 640K byte addresses are assigned to a PC 10c in its inactive state. Under such conditions, the address value given from a mapping table MT 12b is outputted to a system bus 23 when the higher 3 bits of the address value are equal to '011' within the MT 12b controlled by the PC 10b. Meanwhile the address value stored in an MT 12c controlled by PC 10c is outputted to the bus 23 when the higher 3 bits of the address value stored in the MT 12b is equal to '100'. In this case, the address value is equal to the value obtained by subtracting the data stored in the MT 12c from the value of the lower 5 bits of the data stored in the MT 12b.

Description

[Detailed Description of the Invention] [Purpose of the Invention (Industrial Application Field) This invention is particularly applicable to information processing systems that require particularly advanced and high performance, such as multiprocessor systems that manage shared memory by multiple processors. It relates to a processing device.

(Prior Art) In general, mutual data communication and management of shared data are one of the major problems in multiprocessor systems. In this type of system, a method is usually adopted in which a specific area is provided in the memory space, and this range is excluded from the memory management target of each processor and treated as a special area. Therefore, this area is generally limited to a small area, and when handling a large amount of data, measures are taken such as increasing memory accordingly.

However, in the case of the above-mentioned method, memory usage efficiency is poor and it is basically unsuitable for sharing a large amount of data. Furthermore, since it is necessary to make each processor aware of a specific area on the memory, there is a drawback that there is a large restriction on the functionality and flexibility of the memory management function that each processor has independently.

(Problems to be Solved by the Invention) As mentioned above, the method of treating a specific area in the memory space as a special area in the conventional multiprocessor system is basically unsuitable for sharing large amounts of data. However, it also had the disadvantage of placing significant restrictions on the functionality and flexibility of the memory management functions that each processor had independently.

Therefore, the present invention provides a high-performance information processing device that allows other processors to arbitrarily access the memory area managed by each processor without being aware of the memory management method of each processor. It is intended to.

[Structure of the Invention] (Means for Solving the Problem) In order to achieve the above object, the information processing device of the present invention includes a method for converting logical addresses output from a plurality of processors into physical addresses. In the apparatus having a mapping table, a mutual reference means is provided for controlling each processor to mutually refer to the mapping table and perform address conversion.

(Operation) With the above-described means, this invention enables address translation without being aware of the other party's memory management system.
This makes it possible to use memory effectively.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 shows an information processing apparatus according to the present invention as an example of a multiprocessor system equipped with, for example, four processors.

Here, each processor is equipped with a mapping table so that each processor can manage its own memory, and by outputting an address to the system bus via this, the memory shared by each processor can be accessed. It has become.

That is, this multiprocessor system includes first to fourth processors 10a to 10d, and each processor 10a to 10d.
The first to fourth selectors 11a to lld provided for each of a to 10d, the first to fourth mapping tables 12a to 12d, and the first to fourth selectors 11a to lld provided for each of the first to fourth mapping tables 12a to 12d. 2nd gate 1
3a to 13d.

14a to 14d, a decoder 15, an avita 16, and a memory 17.

Address lines 21a-21d, data lines and input/output control lines 22a-22d extend from the first to fourth processors 10a-IC1d, respectively. Each of the address lines 21a to 21d is connected to the first to fourth selectors lla to 11d, respectively.

Each of the data lines and input/output control lines 22a to 22d is connected to the system bus 23, respectively.

The first to fourth processors 10a to 10d transmit system bus request signals to the system bus 23 via signal lines 24a to 24d, and in response to this transmission, the aviator 16 sends system bus request signals to the system bus 23 and signal lines 25a. 25d becomes active by receiving a bus acknowledge signal as a request response signal.

Each of the first to fourth selectors lla to lld is connected to address lines 21a to 21d from the respective processors 10a to 10d that manage input to each mapping table 12a to 12d, or an address on the local address bus 26. You are supposed to select one of the lines.

The first to fourth mapping tables 12. g~12
d is the memory 1 used by each processor 108 to 10d.
7 for their own management. Note that the specific configuration of the mapping tables 12a to 12d will be described later.

The first gates 13a to 13d are connected to each mapping table 1.
．． It controls on/off when outputs from 2a to 12d are output to the system bus 23.

The second cages 14a to 14d each have a mapping table 1.
The outputs from 2a to 12d are connected to the above local address bus 2.
This is to control on/off when outputting to 6.

Here, the selectors lla-1], d for selecting inputs to the mapping tables 12a-12d, and the second gates 14a-14d for controlling the output to the local address bus 26 are connected to the system. bus 23
It is controlled by the hash acknowledge signal from the arbiter 16 which is supplied via the arbiter 16. In addition, the system bus 2
3] cells 13a to 13d that control the output to
are controlled by table selection signals supplied from the decoder 15 via signal lines 27a to 27d.

The decoder 15 constantly monitors the addresses on the local address bus 26 and pre-configures each processor 10a to
When the address assigned to the processor 10d is detected, the first gate of the processor is activated so that the address is output onto the system bus 23.

The arbiter 16 receives system bus request signals output from each of the processors 10a to 10d, selects one of the processors that outputs the system bus request signal according to a predefined algorithm, and transmits a bus acknowledge signal to it. It will be sent back. Note that the specific configuration of the arbiter 16 will be described later.

Therefore, among the processors 10a to 10d, only those that receive the pass acknowledge signal from the arbiter 16 are in the active state, that is, they have the right to access the system bus 23. This system bus 2
Only the processor with the exclusive right of 3 can access any device on the system bus 23, such as accessing the memory 17.

That is, in this embodiment, only the processors 10a to 10d that have received the pass acknowledge signal become active and output the address.

And selectors lla to 11 provided in each
'd selects that address and inputs it into the corresponding mapping table 12a to 12d, and also selects each address so that the output from the mapping table 12a to 12 (1) is output on the local address bus 26. Two gates 14a to 14d are controlled.

On the other hand, the processors 10a~] and Od, which do not receive the Hass acknowledge signal, are in a stopped state, and the system Hass 2
3 is released, and each selector selects an address output from another processor on the local address bus 26 to be input into its own mapping table.

FIG. 2 shows each processor 10a in the memory 17.
This shows an example of allocation every ~10d.

In this case, manipulating tables 12a to 12d, which will be described later,
Based on the configuration of , basically, the allocation of each processor to each memory block may be mixed, but here, to simplify the explanation, consecutive areas are allocated to each processor. So, each processor 10
A to 10d can arbitrarily use the memory 17 within each area under its own management system.

Furthermore, when accessing an unallocated area, it can be accessed via a mapping table managed by the processor assigned to the access chain.

Next, each component shown in FIG. 1 will be explained in detail.

FIG. 3 shows the configuration of the mapping tables 12a to 12(H).

That is, each of the mapping tables 12a to 12d has a mapping table storage RAM 121 and a gate 12□ for controlling the setting of table data for the mapping table storage RAM 12+.
, a gate 123 for controlling the output of the address converted by the mapping table storage RAMI 2+.
, and read or write the processor or memory 17
It is constituted by a gate circuit 124 for activating the gate 12° when an iteL is to be performed.

The mapping table storage RAM 12 is provided with a
Address conversion is performed on address 1i-jj, and these are set as addresses hh-i1N for the gate 12. and is output via the address signal line 126. That is, for example, when a processor having a 1M byte address space attempts to manage bytes of memory in one block 4, addresses 12 to 19 output from the processor or mapping table RAM 12. address00=address, and performs address conversion by outputting the data of the corresponding address.
ssll or output as is. in this case,
If the mapping table RAM 121 has a capacity of 256 words, the entire memory space can be mapped.

Gate 12□ is the mapping table RAM 1
2 I1 connected between the data side of I and the data bus 127 and supplied from the processor via the signal line 128.
0 read signal or i10 write signal, the manipulating table RAM 12. This controls the writing or reading of table data to and from the table data.

The table 123 is the mapping table RAM 1.
2, is connected to the data side of , and the signal line 1 from the processor
The gate circuit 124 is activated by the output of the gate circuit 124, which is enabled by a memory read signal or a memory write signal supplied through the gate 29.

Note that the data bus 127 and each signal line, 12
g and 1.2g are both omitted in FIG.

FIG. 4 shows a control diagram for bus arbitration.

That is, the - group bus request signal lines 24a24b,
~ and a group of bus acknowledge signal lines 25a, 25b, ~
is a pair of each processor 10a.
, 10b, ~, and are installed on the system bus 23 by the number of processors (four in this case).

As already explained, the processor or memory 1
When attempting to read or write 7, in this embodiment, the processor first sends a bus request signal to the arbiter 16. At this time,
When bus request signals are sent from multiple processors at the same time, the arbiter 16 selects one of them.
is selected.

Although the algorithm in this case varies depending on the system application, the round-tropin method is adopted in this embodiment. This is a method in which the currently selected item will have the lowest priority next time.

As described above, when a processor is selected by the arbiter 16, the processor is activated, and the selectors and gates included in the processor are also set in the prescribed manner as described above.

Further, in this embodiment, only one processor is selected by the arbiter 16, and at this time, the other processors are inactive, that is, in a stopped state.

FIG. 5 shows the configuration of a decoder section on the local address bus 26.

The decoder 15 constantly monitors the address value on the local address bus 26, and determines whether the address value is the value and activates the gate provided in the corresponding processor if the allocated memory for each processor is within the area. and outputs the address value from the mapping table owned by the processor onto the system bus 23.

Here, the decoder 15 may be constructed of a general logic circuit, but it is also possible to provide another mapping table storage RAM in this part and perform gate control to each processor based on the contents. By doing so, instead of consecutive memory allocation for each processor as shown in FIG. 2, it is also possible to allocate memory in a mixed manner for each block or to change this automatically.

Next, an example of address allocation and operations related to addresses in this embodiment will be described.

FIG. 6 shows the area around the first processor 10a as an example of address signal line allocation around one processor.

Here, let us consider the case where 4 hides are one block and 128 bytes of memory are allocated per processor as shown in FIG. Further, it is assumed that each processor has a logical access range only from address 0 to byte address 128.

First, depending on the selection of the arbiter 16, the first processor 10
If the address a is in the active state, the 17-bit address from address 00 to address 16 output from the processor 10a is divided into the upper 5 bits of the memory block selection address and the lower 12 bits of the intra-block address. The block selection address is input to the first mapping table 12a via the first selector 11a. When accessing the range of the memory area allocated to this processor 10a, it is converted into an 8-bit address arbitrarily mapped within this range and output. This address, for example, the range from byte address 384 to byte address 512, is
It is output onto the local address bus 26 via the second gate 14a.

This address is also monitored by the decoder 15. If this address is assigned to the processor 10a that outputs it, the first gate 13a is opened and the address is output onto the system bus 23 together with the above-mentioned lower intra-block address.

Here, if the memory areas allocated to the other processors 10b to 10d are to be accessed, this is done by setting the relevant addresses in the mapping table 12a in advance. That is, the first gate of the processor assigned to that address is opened by the decoder 15, and the address value on the mapping table managed by that processor is output onto the system bus 23.

On the other hand, values on the local address bus 26 are given to inputs to mapping tables 12b-12d managed by inactive processors 10b-10d, respectively. Therefore, the address is further converted from the values of address12 to address16 (in this embodiment) of the address outputted from the active processor 10a onto the local address bus 26 and outputted onto the system bus 23. .

FIG. 7 shows the operation related to the address described above.

For example, now the second processor 10b is active and is assigned byte addresses ~512 in the memory area 384, and the third processor 10c is inactive and has byte addresses ~640 assigned to the same <512. Assume that a byte address is assigned to .

In this case, the upper three bits of the address value in the mapping table 12b managed by the second processor 10b or rol
lJ, the address value from this table 12b is output onto the system bus 23. However, as shown in the figure, when the upper three bits of the address value in the mapping table 12b are rloooJ, the third processor 1
The address value in the mapping table 12c managed by 0c will be output onto the system bus 23. At this time, the address value is calculated from the value of the lower 5 bits of the data in the mapping table 12b to the mapping table 12c.
This is the value obtained by subtracting the data within.

As mentioned above, addresses can be translated without being aware of the other party's memory management method.

In other words, in a system consisting of multiple processors, it is possible to not only enable each processor to operate with its own memory management function, but also to be able to send and receive data between each other under separate memory management methods. It allows you to access the memory area allocated to the other party without being aware of the method. This allows each processor to use its own memory management method to effectively utilize memory, and eliminates the need for complicated protocol coils for exchanging data between each processor. No problem.

Therefore, a high-performance system can be easily realized.

In addition, in the above embodiment, the case where only address data is simply stored as data on the mapping table has been explained, but in reality, for example, when changing the mapping table, it is stored by another processor. A means for controlling depending on whether or not it is being referenced is required.

That is, according to the present invention, each processor can mutually share the memory area that each processor manages. However, with such a configuration,
While a processor (this is called processor A) or another processor (this is called processor B) is accessing memory and executing a process via a mapping table managed by another processor, processor B If this becomes active and the pine pink table that it manages is rewritten, processor A may no longer be able to access it via this pine pink table.

Therefore, a means for controlling changes in the pine pink table depending on whether it is referenced by another processor is required.

Therefore, in the present invention, this is achieved by providing a control flag on the pine pink table.

FIG. 8 shows an example of the setting format of each data on the above-mentioned mapping table.

In this case, mapping table 12. .about.6 is composed of an address section for storing address data to be converted through this, and a flag section for storing the above-mentioned control flag. The specific setting values in the address section are the same as those shown in FIG. 7 above. A control flag is assigned to each of these set values, that is, to each memory plot.

The flag section further includes a plurality of bits, each of which is assigned to each processor.

Then, the processor or mapping table 12, .
When accessing via, for example, as shown in FIG. 9, the corresponding bit position of the flag section is set to ON state, and when the access is to be terminated, the corresponding bit position is also set to OFF state. This is done by

On the other hand, mapping table 12. ~． If you change
For example, as shown in FIG. 10, the mapping table 12. The processor managing processors 6 to 6 performs the processing after confirming that all flags other than the processor's flags are in the off state.

The above processing is easily realized by the configuration shown in FIG. 3, which allows arbitrary access to the mapping table.

Next, other embodiments (modifications) of the present invention will be described.

FIG. 11 shows an example of a configuration in which, for example, two processors are installed.

Here, only one processor has a mapping table, and since there are only two processors, no arbiter is provided, and HOLD/HLD between processors is provided.
The A signal is used to process the transfer of exclusive rights to the bus.

That is, the second processor 102 or, for example, the memory 10
3, a HOLD signal is first applied to the first processor 101 via the signal line 104. Then, the first processor 101 is brought into a stopped state, and the HLDA signal as a response is sent back via the signal line 105.

As a result, the second processor 102 is activated, the selector 106 is switched, and the signal line for giving an address to the mapping table 107 is transferred from the address line 101a of the first processor 101 to the local address bus of the second processor 102. 102a.

Further, the local address bus 102a is connected to the decoder 1.
08, and whether the address from the second processor 102 should be output directly to the system bus 09 or the first processor outputs it via the mano pink table 1 managed by the first processor 0. Depending on what is to be output, either gate 1]]0 or gate 11] is selectively controlled.That is, the address to be directly output is sent to the system bus 109 via gate]]0, and The address to be output via the mapping table 107 is sent to the system lot 109 through the gate 111.

In this way, in the case of two processors, memory can be shared with a very simple configuration.

Note that 101b and 102b shown in the figure are the first
．． second processor 101.102 to system bus 10
These are the data lines and input/output control lines extending to 9.

It goes without saying that various other modifications can be made without departing from the gist of the invention.

[Effects of the Invention] As described in detail above, according to the present invention, addresses can be freely translated using different memory management methods, without having to be aware of the memory management method used by each processor. , it is possible to provide a high-performance information processing device that allows other processors to arbitrarily access the memory area managed by the processor.

[Brief explanation of the drawing]

1 to 7 show an embodiment of the present invention. FIG. 1 is a configuration diagram of an information processing device exemplifying a multiprocessor system equipped with four processors, and FIG. FIG. 3 is a block diagram showing the configuration of a mapping table, FIG. 4 is a diagram showing a group of control lines related to bus arbitration, and FIG. 5 is a diagram showing a decoder section on the local address bus. FIG. 6 is a block diagram showing an example of the allocation of address signal lines around one processor, FIG. 7 is a diagram showing the operation around addresses, and FIG. The figure shows an example of the setting format of each data on the mapping table,
FIG. 9 is a flowchart shown to explain the operation when accessing via a mapping table managed by another processor, and FIG. 1O is a flowchart shown to explain the operation when changing the mapping table. FIG. 11 is a configuration diagram of an information processing apparatus exemplifying a case where two processors are installed as another embodiment. 10a-10d... 1st to 4th process, Nosa, 1
1a to lld...first to fourth selectors, 12a to 1
2d: first to fourth mapping table, 121
...Matuping table RAM. 12□ 123...gate, 124...gate circuit, 132-13d=first gate, 14a-14d
- second gate, 15... decoder, 16... arbiter, 17... memory, 23... system bus, 26
...local address bus. Applicant's agent Patent attorney Takehiko Suzue

Claims (1)

[Claims] In an information processing device having a mapping table for converting logical addresses output from a plurality of processors into physical addresses, each processor mutually refers to the mapping table to perform address conversion. An information processing device characterized in that it is provided with cross-referencing means for controlling the operations.