JPS62172451A - Data processor - Google Patents

Abstract

PURPOSE:To prevent the lowering of a processing capacity by providing a data cache which stores a part of data provided within a central processor by every block unit, and a reference change information buffer which stores a part of R bits and C bits provided within the central processor. CONSTITUTION:A data cache 6 which stores a part of the data within a main memory data storage part 2 by every block unit,and a reference change information buffer 7 which stores a part of the R bits and the C bits within a main memory key storage part 3 are provided. When an instruction RRB is issued from an arithmetic unit 9, an R and C bit changing means 19 outputs a changing means 19a by detecting a coincidence at a comparator 14 or 15, and makes an R bit 22 in a coincided entry 13 to 0, on the other hand, it sends a C bit 23 and the R bit 22 before a change in the entry 13 to the arithmetic unit 9 through an R and C bit register 17. Therefore,the states of the R bit 22 and the C bit 23 corresponding to a page frame are reflected to the condition code of the instruction RRB. I this way, the lowering of a processing capacity in a virtual memory system can be prevented.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a data processing device using a virtual memory method that manages the correspondence between virtual memory and real memory in units of pages of a fixed size, and particularly relates to a data processing device that uses a main memory The present invention relates to a data processing device that improves the ability to manage reference bits that represent the usage status of page frames in page replacement.

[Prior Art] Conventionally, this type of data processing device has been equipped with a data cache that stores a part of the contents of the main memory, and has a function on the main memory that protects and changes the contents for each page. It is well known to provide main memory keys for recording purposes. The purpose of this main memory key is to protect the data in the main memory and record reference updates, and it is a fixed size (usually 4 bytes) in the main memory.
It is provided corresponding to the page frame.

FIG. 4 is a block diagram showing the configuration of a general main memory key used in this type of data processing device, and in the figure, (30) is the main memory key. (31) is the memory protection key, (32) is the read protection bit, or F bit, (
33) is a reference bit or R bit, and (34) is a change bit or C bit, which constitute a main memory key (30).

On the other hand, in a data processing device (not shown), the operating system activates a paging algorithm at regular intervals for page replacement, and the R bit ( 33), the usage status of the page frame in a certain period of time is managed. Therefore, in response to a page replacement request, the least frequently used page frame is targeted for replacement.

At this time, as an instruction for checking the R bit, the R
The RB (reset reference bit) instruction is used,
This RRB instruction specifies the page frame, reflects the state of the R bit (33) and C bit (34) corresponding to that page frame in the condition code, and sets the R bit (33) to "0". have.

A conventional data processing device that is equipped with a data cache and has a main memory key on the main memory side is configured as described above, and when the data to be referenced exists in the data cache, the main memory is not accessed. ing.

[Problems to be Solved by the Invention] As described above, in the conventional data processing device, when the data to be accessed exists in the data cache, the main memory is not accessed and its R bit (33) and Since the C bit (34) is not updated, the R bit (33) is not correctly reflected in the operating system's paging algorithm, and frequently used page frames may be replaced. There was a problem that processing performance deteriorated.

This invention was made in order to solve the above-mentioned problems, and it is possible that the value of the R bit reflected in the condition code of the RRB instruction correctly reflects the occurrence of a reference to data within the corresponding page frame. The purpose of this invention is to obtain a data processing device that can perform the following functions.

[Means for Solving the Problems] The data processing device according to the present invention includes, in the central processing unit,
A reference change information buffer is provided to store part of the R bit and C bit.

[Operation] In this invention, if the R bit and C bit corresponding to the page frame for which the reference request has been made exist in the reference change information buffer, the R bit and C bit in the reference change information buffer are changed, When replacing an entry in the reference change information buffer, write the R bit and C bit in the reference change information buffer to the main memory key, and write the R bit and C bit corresponding to the page frame newly requested for reference as the main memory key. Loaded from the storage key, the R bit and C bit corresponding to the page frame address specified in the RRB command are loaded into the reference change information (・if it exists in the no.F, its reference change information) (・yF). , if it is not in the reference change information buffer, accesses the main memory key.

[Example] Hereinafter, an example of the present invention will be described with reference to the drawings. 1st
The figure is a block diagram showing an embodiment of this invention, (1)
is the main memory. (2) is a main memory data storage section consisting of a plurality of page frames for storing data, and (3) is a main memory key (30) corresponding to each page frame in the main memory data storage section (2) (Fig. 4). (4) is a main memory control unit that controls the main memory device (1), and these constitute the main memory device (1).

(5) is a central processing unit connected to the main storage device (1) via a bus (10). (6) is a data cache that stores part of the data in the main memory data storage section (2) in block units; (7) is the R bit (33) and C bit ( 34) is a reference change information buffer that stores a part of the memory address, (8) is an address conversion buffer that processes the conversion from a virtual memory address to a real memory address at high speed, and (9) is an arithmetic unit that processes instructions. These constitute the central processing unit (5).

Furthermore, FIG. 2 is a block diagram showing the configuration of the reference change information buffer (7) in FIG.
) is a page frame address register that stores. (1
2) is a buffer storage unit that stores entries (13), and two entries (13) are specified for a part (lla) of a page frame address (8a).

The entry (13) corresponds to the configuration of the page frame address (8a) and is configured as shown in the block diagram of FIG. 3. (21) is the part corresponding to the remaining part (llb) of the page frame address (8a) that is not used to address the buffer storage unit (12), that is, PFA (page frame address); ) is the R bit, (23) is the C bit, and the main memory key (
30) corresponds to the R bit (33) and C bit (34) in (see Figure 4). (24) is a V bit which indicates by an on state that entry (13) is valid.

(14) and (15) are comparators, and the page frame address information, that is, PFA (
21) and the remaining part of the page frame address (1l b), and the comparison target is the same and corresponding entry (1l b).
When the V bit <24) in 3) is on, a coincidence detection signal (14a) or (15a) is output.

(16) represents the R bit (22) and C
selector (17) that selectively outputs bit (23);
is an RC bit register (18) that stores the output signal (16&) from the selector (16) and outputs it to the arithmetic unit (9).
) is an OR circuit that passes the match detection signal (14a) or (15a), and (19) is the entry where the match detection signal (14m) or (15m) via the OR circuit (18) is input and a match is detected. (13) R bit < 22) and C
This is an RC bit changing means for changing bit (23).

Next, the operation of one embodiment of the present invention will be described with reference to FIGS. 1 to 4.

When the arithmetic unit (9) issues a reference request for data in the main memory data storage unit (2), this requested address is converted from a virtual address to a real address in the address translation buffer (8), and this real address The page frame address (8a) inside is stored in the page frame address register (11) in the reference change information buffer (7).

Then, the part (lla) of the page frame address (8a) creates two entries (13) in the buffer storage (12).
) are read simultaneously, and the remaining part (llb) of the page frame address (8a) and P in the two entries (13)
F A (21) and comparators (14) and (1
5). At the same time, the on state of the V bit (24) is also detected, and as a result of this comparison, two entries (
A match is detected in either PFA (21) in 13), and the match detection signal (14a) or (15a) is sent to the OR circuit (
18) to the RC bit changing means (19). As a result, the RC bit change means (19) outputs a change signal (19m), and the entry (1
The R bit (22) and C bit (23) in 3) are changed according to the type of reference request (9a) from the arithmetic unit (9).

Also, if the comparison results in a mismatch in both comparators (14) and (15), one entry (13)
) is selected, and the R bit (33) in the main memory key (30) is transferred from the main memory key storage unit (3) to its entry (13).
and C bit (34) are transferred. In other words, in this case,
If there is one entry (13) with the v bit (24) in the OFF state among the two entries (13), that entry (1
3) is selected, and if there are two, one is selected. Also, if both bits (24) are on,
Transfer is performed by swapping out either one to the main memory key storage section (3). Note that this transfer procedure and control circuit are not shown because it is obvious that the buffer storage unit (12) is of a general set associative type.

On the other hand, when an RRB instruction is issued from the arithmetic unit (9) and a match is detected in the comparator (14) or (15), the RC bit changing means (19) outputs a changing signal (19m). , R bit (22) in matched entry (13)
) is changed to r□, and the C bit (23) in the entry (13) and the R bit (2Z) before the change are sent to the arithmetic unit (9) via the RC bit register (17).

Therefore, the condition code of the RRB instruction includes the R bit (22) ((33) ') and the C bit (
23) The state of ((34)) is reflected. Also, if no match is detected by comparators (14) and (15),
By directly accessing the main memory key storage section (3), the R bit (22) and C bit (23) are read out and reflected in the condition code in the arithmetic unit (9).

[Effects of the Invention] As described above, according to the present invention, a reference change information buffer is provided in the central processing unit, and the occurrence of a reference request for data within a page frame is determined by the R bit reflecting the condition code of the RRB instruction. I configured it so that the page is reflected correctly and the least frequently used page is replaced when replacing the page.
This has the effect of providing a data processing device that can prevent a decline in processing performance in a virtual storage system without impairing the reference request performance improvement effect of the data cache.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of the reference change information buffer in FIG. 1, and FIG. 3 is a block diagram showing the configuration of the entry in FIG. 2. 4 are block diagrams showing the configuration of a general main memory key. (1) Main memory (2) Main memory data storage (3) Main memory key storage (5) Central processing unit (6) Data cache (7 )...Reference change information buffer (8)...Address translation buffer (8&)...Page frame address (9)...Arithmetic unit (9&)...Reference request (11)...Page frame Address register (12)...
・Buffer storage unit (13)...Entry (14),
(15)... Comparator (14m), (15a)... Coincidence detection signal (16)
... Selector (16a) ... Output signal (17
)...RC bit register (19)...RC bit changing means (19a)...Change signal (21)...PFA (portion not used for address of buffer storage section) (22)...Entry R bit (23) in the entry...C bit (24) in the entry...V bit (30)...Main memory key (3
3)...R bit (34) in the main memory key...C bit in the main memory key In the drawings, the same reference numerals indicate the same or equivalent parts. Procedural amendment (voluntary) ■To the call 1. Tun, Moon. Day

Claims (3)

[Claims] (1) A main memory device, a main memory data storage section provided in the main memory device and consisting of a plurality of page frames for storing data, and a main memory data storage section provided in the main memory device to protect and refer to and change the data. a main memory key storage unit storing a main memory key including an R bit and a C bit for recording;
A central processing unit connected to the main storage device, an arithmetic unit provided within the central processing unit for processing instructions, and an arithmetic unit provided within the central processing unit for converting virtual memory addresses to real memory addresses. an address translation buffer that performs this, a data cache that is provided within the central processing unit and stores a portion of the data in block units, and a data cache that is provided within the central processing unit that stores a portion of the R bit and C bit. A data processing device comprising: a reference change information buffer. (2) The reference change information buffer includes an address translation buffer that outputs a page frame address in response to a reference request from the arithmetic unit, a page frame address register that stores the page frame address, and a part of the page frame address. a buffer storage section in which one entry is specified; two comparators that compare portions of the two entries corresponding to the remaining portions of the page frame address, respectively, with the remaining portions of the page frame address; a selector that selects the R bit and C bit of one of the two entries in response to a coincidence detection signal from the device; an RC bit register that stores the output signal of this selector and outputs it to the arithmetic unit; 2. The data processing apparatus according to claim 1, further comprising RC bit changing means for changing the R bit and C bit of one of the two entries in response to the reference request. (3) Each entry in the buffer storage section has a V bit indicating whether or not the respective entry is valid, and only when the V bit of the corresponding entry is on, that is, the entry is valid, the corresponding comparator 3. The data processing device according to claim 2, wherein a coincidence detection signal is output from the data processing device.