JPH0211931B2 - - Google Patents

Description

[Detailed description of the invention]

[Industrial Field of Application] The present invention relates to a buffer storage control method in an information processing system, and more particularly, to a buffer storage control method for managing block addresses of copies of data in a main memory stored in buffer storage using logical addresses. This relates to directory access methods. [Problems to be solved by the prior art and the invention] Generally, in a computer system that executes a program that describes storage space using logical addresses,
Since logical addresses and real addresses do not have a one-to-one correspondence, buffer directories in computers that employ buffer storage for speeding up are managed using real addresses. However, for example, “IBM
TECHNICAL DISCLOSURE BULLETIN
VOL21.No.11 APRIL 1979 PP4541”, register a logical address and a real address as a pair in the directory, first index the directory using the logical address, and when hit, it is assumed that the data is registered in the buffer memory. Processing, if there is a miss, the address conversion table is referenced to find the real address and the directory of the real address is indexed.If there is a hit here, the logical address at that time is registered in the directory, and it is assumed that the data is registered in the buffer memory. Therefore, this method has the disadvantage of doubling the hardware required for the directory.On the other hand, if you want to increase the buffer storage capacity, you can register real addresses in the conventional directory. In this method, in order to speed up access to buffer memory, the operation of converting a logical address to a real address using an address conversion table and the operation of indexing the directory to determine hits and misses are performed in parallel, and the buffer memory is Since access is restricted to addresses within the page below the logical address, increase the buffer storage compartment or
Or, for example, as shown in Japanese Patent Application Laid-Open No. 56-140575 "Cache Storage System," the lower N bits from the address convertible field (virtual page address) of the logical address are used as addresses for directory and buffer storage. is considered. As described above, there is a drawback that complicated control is required. The objects of the present invention are, firstly, to facilitate the increase in buffer storage capacity by registering buffer storage directories with logical addresses;
The third method is to enable high-speed access by directly accessing the buffer memory and buffer directory using logical addresses without going through an address conversion process. It is possible to reduce the frequency of address conversion requests to the conversion means, reduce competition with address conversion requests from the vector data processing means, and enable the scalar data processing means and the vector data processing means to share the address conversion means, thereby reducing the amount of hardware. to do;
The fourth object is to provide an information processing apparatus that realizes a simplified main memory access protection method in a logical address buffer storage method. [Means for Solving the Problems] The present invention provides an instruction issuing means for issuing a vector operation instruction and a scalar operation instruction, a vector data processing means for performing vector operation processing in accordance with the vector operation instruction, and a method for issuing the scalar operation instruction. Therefore, a scalar data processing means that performs scalar arithmetic processing, a main memory device that exchanges vector data and scalar data with the two processing means, respectively, and data loading that is carried out between the two processing means and the main memory device. , converts main memory logical address information generated in response to an operation command from both processing means in response to a store operation into main memory real address information necessary for accessing the main memory device, an address converting means for sending data to an address, connected to the scalar data processing means and the main storage device;
a buffer storage circuit that temporarily stores a plurality of blocks of data in the main storage device in units of block data having a certain bit length; and a buffer storage circuit that is connected to the scalar data processing means and the address conversion means and stored in the buffer storage circuit. Means for registering an address in the main memory of the block data currently being accessed as a logical block address, and further storing an access permission determination bit for determining whether or not access to the block data indicated by the block address information is permitted. Then, when a matching block address is detected by comparing the main memory logical address information sent from the scalar data processing device in response to a load or store operation command with the registered block address of the logical address directory circuit,
access determination means that compares and determines the access permission determination bit read in response to the matching block address and the access mode check bit sent in response to the operation command, and generates a signal indicating whether or not access is permitted; It consists of a logical address directory circuit. [Example] Next, an example of the present invention will be described in detail with reference to the drawings. First, the configuration and operation will be explained using the embodiment of the present invention shown in FIG. Vector data processing commands and scalar data processing commands are transmitted from the command issuing circuit 1 to signal lines 100, 1
01 to the vector data processing circuit 2 or the scalar data processing circuit 3, respectively.
When it is desired to store the processing results of each circuit in the main memory device 8, or when it is desired to load data required by the processing circuits 2 and 3 from the main memory device 8, signal lines 103 and 105 are connected from the respective circuits.
The movement command is sent via the movement command code (not shown).
is output with. The operation command from the vector data processing circuit 2 is
Together with the main memory logical address information output via the address line 104, it is sent to the address conversion circuit 7, where the logical address is converted into a real address. The operation command is sent to the signal line 121, and the address line 1
At 22, the main memory real address is sent to the main memory device 8. If the operation command is a load request, the requested data is sent back to the vector data processing circuit 2 via the data line 102, and if it is a store operation, the data is stored from the vector data processing circuit 2 into the main storage device 8. On the other hand, the operation command from the scalar data processing circuit 3 is sent to the logical address directory circuit 4 and buffer storage circuit 5 together with main memory logical address information outputted via address lines 107 and 108. The logical address directory circuit 4 is
To simplify the explanation of this embodiment, it is assumed that the compartment is composed of a two-level directory storage 41, logical block address comparison circuits 42, 43, and the like. First, the directory memory 41 is read out using the lower bits of the main memory logic block address sent via the address line 108, and the read two-level logic block address section is sent to the comparator circuit 4.
2 and 43, it is compared with the main memory logic block address sent via the address line 107, and if a match is detected, the signal line 119 or 120 is turned on, and the output signal line 12 of the OR gate 44 is turned on.
3, a match signal is output. Here, an embodiment of the block data access permission determination bit, which is a feature of the present invention, will be described. In general, access protection for data stored in main memory is important, for example, in systems that apply the concept of paging to main memory, pages that can only be accessed in privileged mode or pages that can be accessed in slave mode are protected on a per-page basis. A protection bit is provided to distinguish between logical addresses and real addresses, and it is generally possible to check the address conversion table for converting addresses from logical addresses to real addresses during indexing. In the present invention, the logical address directory circuit 4 is positioned before the address conversion circuit 7, and the buffer storage circuit 5 can be accessed using a logical address. It is necessary to detect the address directory circuit 4 during access. When an operation command is issued from the scalar data processing circuit 3, an access mode check bit indicating whether the access mode is privileged mode or slave mode is sent to the directory circuit 4 via the signal line 106.
When the directory memory 41 is accessed using the lower bits of the logical block address sent in response to the operation command, the logical block address of the block data registered in the buffer memory circuit 5 and the register at the first access to the block data are stored. The access permission determination bit is transmitted to the signal line 116,
It is read out from 117. Here, if the logical block address read from the directory memory 41 and the logical block address sent via the address line 107 together with the operation command match, the signal line 119 or
20 is turned on, the signal lines 116 and 117 are selected as input signals to the switching circuit 47, and the access permission determination bit corresponding to the matched logical block address is sent to the access determination circuit 6 via the signal line 118. On the other hand, the access mode check bit signal sent via the signal line 106 along with the operation command is also sent to the access determination circuit 6, where the inverter 61 first takes a negative logic, and the NAND gate 62 outputs the signal line 118. The access permission determination bits and conditions read from the directory storage 41 via the access permission determination bits and conditions are taken in accordance with Table 1.

[Table] However, 〓1〓 indicates privileged mode access, and 〓0〓 indicates slave mode access.
That is, as shown in Table 1, if an attempt is made to access in slave mode a location where the access permission judgment bit for a block registered in the directory indicates privileged mode, the buffer memory must be made inaccessible. , NAND gate 6
2 detects this state and sends a match suppression signal to the NAND gate 45 via the output signal line 124 to suppress the match signal on the signal line 123. The output of the NAND gate 45 is a hit signal via a signal line 113 and a miss bit signal via a signal line 115. That is, when the access determination circuit 6 detects an inaccessible state, the operation command and the AND gate 4 are
6 is established, and a request to load new block data from the main memory device 8 to the buffer memory circuit 5 is first sent to the address conversion circuit 7 via the signal line 111. As explained earlier, the address conversion circuit 7 has an address conversion table and is provided with access protection bits for each page, so it determines whether or not access is possible according to Table 2. .

〔Effect of the invention〕

As explained above, the present invention has the effect that the logical address buffer system can be easily realized with a small amount of hardware by providing the buffer directory storage with access permission determination bits corresponding to logical block addresses.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention;
FIG. 2 shows an example of the format of the operation command code used in the embodiment shown in FIG. 1... Instruction issuing circuit, 2... Vector data processing circuit, 3... Scalar data processing circuit, 4...
Logical address directory circuit, 5...Buffer storage circuit, 6...Access determination circuit, 7...Address conversion circuit, 8...Main storage device, 41...Directory storage, 42, 43...Logic block address comparison circuit, 44...OR gate, 45...
NAND gate, 46...AND gate, 47...
Switching circuit, 51... Buffer memory, 52... Switching circuit, 61... Inverter, 62... NAND gate.

Claims (1)

[Scope of Claims] 1. Instruction issuing means for issuing vector operation instructions and scalar operation instructions, vector data processing means for performing vector operation processing according to the vector operation instructions, and scalar operation processing according to the scalar operation instructions. A scalar processing means that performs processing, a main memory that transfers vector data and scalar data between the two processing means, respectively, and data loading and storage operations that are performed between the two processing means and the main memory. an address converting means for converting main memory logical address information generated together with an operation command from both processing means into main memory real address information necessary for accessing the main memory device; and the scalar data processing means. and a buffer storage circuit connected to the main storage device and temporarily storing a plurality of blocks of data in the main storage device in units of block data each having a certain bit length, and the scalar data processing means and the address conversion means. registering an address in the main memory of block data connected and stored in the buffer storage circuit as a logical block address;
a logical address directory circuit for determining whether data corresponding to a logical address sent from the scalar data processing means together with an operation command exists in the buffer storage circuit; the logical address directory circuit includes a logical block; storage means for storing address information and an access permission determination bit for determining whether or not access to block data in the buffer storage circuit indicated by the block address information is permitted; and a load/store operation command from the scalar data processing device. When a matching block address is detected when comparing the main memory logical address information sent in response to the registered block address of the corresponding logical address directory circuit, the memory address information corresponding to the matching block address is compared. The access determination means compares and determines the access permission determination bit read from the means with the access mode check bit sent in response to the operation command, and generates a signal indicating whether access is permitted or not. Information processing equipment.