JP3256558B2 - Address translation method for electronic computers - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic computer having two types of system buses having different address widths when accessing a memory connected to another bus from a module connected to one bus. Address conversion method.

[0002]

2. Description of the Related Art Generally, an electronic computer having two types of system buses having different address widths is constructed as shown in FIG.

In FIG. 3, reference numeral 1 denotes a first system bus having an address width of, for example, 32 bits;
A second system bus having an address width of bits, 11
Is a CPU, 12 is a main memory, 13 is a bus adapter,
Reference numeral 14 denotes a local memory, and 15 denotes an input / output device (I / O). Here, a case where the input / output device (I / O) 15 accesses a specific storage area of the main memory 12 will be considered.

In this case, an input / output device (I / O) 15
It is started by the CPU 11 via the bus adapter 13.
At this time, a buffer address (a head address of a usable storage space) in the main memory 12 used by the input / output device (I / O) 15 and a buffer length (the storage space of the storage space) are transmitted from the CPU 11 to the bus adapter 13. Size) is notified.

Conventionally, the input / output device (I / O) 15 cannot directly access the main memory 12 due to the difference in the address width between the system buses 1 and 2, so that the bus adapter 13
When the bus adapter 13 receives the activation to the input / output device (I / O) 15 from the CPU 11, the bus adapter 13
O) The input / output device (I / O) 15 has been activated after transferring the buffer area of the main memory 12 used by the device 15 to the local memory 14.

When the input / output device (I / O) 15 is activated, the input / output device (I / O) 15 operates using the buffer of the local memory 14 as a work area. Make a notification. When the bus adapter 13 is notified of the operation completion from the input / output device (I / O) 15, the bus adapter 13 uses the buffer area in the local memory 14 used by the input / output device (I / O) 15 as the main memory. After transferring the data to the memory 12, the CPU 11 is notified of the completion.

As described above, when the input / output device (I / O) 15 accesses the main memory 12, conventionally, data transfer by the bus adapter 13 always occurs twice, which causes overhead. Was.

The bus adapter 13 is connected to an input / output device (I
In the case where the command to the (/ O) 15 is analyzed and, for example, only reading is performed when viewed from the input / output device (I / O) 15, the data transfer can be performed only at the time of activation and the data transfer at the time of completion can be omitted. Even in this case, data transfer by the adapter 13 which causes overhead occurs once. Also, a new overhead for analyzing the command is generated.

Further, the data transfer of the buffer area by the bus adapter 13 is always executed by the buffer length given from the CPU 11 irrespective of the size of the input / output actually executed by the input / output device (I / O) 15. Must. Such useless data transfer,
It causes overhead.

Therefore, recently, an input / output device (I / O)
A configuration is considered in which an address conversion table for converting a 24-bit address from 15 to a 32-bit address for accessing the main memory 12 is provided in the bus adapter 13.

With such an address translation mechanism,
An input / output device (I / O) 15 can directly access a predetermined storage space on the main memory 12. Therefore, as described above, the start information (read / write command, buffer address, buffer length, etc.) necessary for accessing the main memory 12 from the bus adapter 13 to the input / output device (I / O) 15 is stored. In the direct notification method, efficient data access can be realized by eliminating unnecessary data transfer.

However, the input / output device (I / O) 15
In a system in which startup information (read / write command, buffer address, buffer length, etc.) necessary for accessing the main memory 12 is registered in the main memory 12 in advance, the bus adapter 13
Before starting the input / output device (I / O) 15, it is necessary to read start information from the main memory 12. For this reason,
In the case where the above-described address translation mechanism is used in such a system, the input / output device (I / O) 15 first receives the activation and uses the address translation mechanism to start the main memory 1.
2 is read, and then data is input / output to / from the main memory 12 again using the address translation mechanism.

As described above, the access to the main memory 12 twice puts an extra load on the first system bus 11, and is a major cause of lowering the operation performance of the entire system.

[0014]

Conventionally, there has been a drawback that the number of accesses to the main memory for reading the startup information has been increased, thereby reducing the operation performance of the entire electronic computer system.

The present invention has been made in view of the above points, and has an address which enables an input / output device to easily read startup information without accessing a main memory, and which can improve the operation performance of the entire computer system. It is intended to provide a conversion method.

[0016]

An address conversion system according to the present invention comprises first and second system buses having mutually different address widths, and memories respectively connected to the first and second system buses. And an input / output device, and a bus adapter that connects the first and second system buses.
The bus adapter has an internal memory in which activation information for the input / output device registered in the memory is set in advance, and a plurality of storage areas that can be specified by an upper bit address of the second system bus, In each storage area, one of a first address value indicating a storage area of the boot information set on the internal memory and a second address value indicating a predetermined storage space on the memory And address storage means for registering identification information for identifying the first and second address values;
On the basis of the first or second address value read from the storage area addressed by the upper bit address of the second system bus and the value of the lower bit address of the second system bus, Means for generating an address for accessing the memory or the internal memory, and selecting one of the memory and the internal memory as an access destination based on the identification information read from the addressed storage area Means for converting the address of the second system bus into an address for accessing the memory or the internal memory.

In this address conversion method, since the startup information is set in advance in the internal memory of the bus adapter, the input / output device can access the memory connected to the first system bus without accessing the memory connected to the first system bus. The startup information can be read by accessing the internal memory. For this reason, the number of times of data transfer via the first system bus is reduced, and system performance can be improved.

The address storage means stores a first address value indicating a storage area of the start information set in the internal memory, a second address value indicating a predetermined storage space of the memory, and furthermore, these addresses. The identification information for identification is registered, and those address values are read with the upper bit address of the second system bus. In this case, which address has been read is identified by the identification information. Therefore, regardless of which of the first and second addresses is read, the address of the second system bus can be appropriately converted into an address for accessing the memory or the internal memory. Therefore, access to both the memory and the internal memory can be directly performed, and efficient memory access can be realized without unnecessary data transfer.

[0019]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a system configuration of an electronic computer according to an embodiment of the present invention. This computer system has two types of system buses having different address widths as in the conventional system shown in FIG. 3, and includes first and second system buses 21 and 22 and a CPU.
31, a main memory 32, and a bus adapter 33.

The first system bus 21 is a data bus,
It comprises an address bus and a control line, and the address bus has a bus width of, for example, 32 bits.

The second system bus 22 includes a data bus,
It comprises an address bus and a control line, and the address bus has a bus width of, for example, 24 bits.

The CPU 31 controls the overall operation of the computer, and is connected to the main memory 32 and the bus adapter 33 via the first system bus 21. The CPU 31 includes an input / output device (I / O) 38
When the start request is issued, the buffer address (the head address of the usable storage space) of the main memory 32 used by the input / output device (I / O) 38 and the buffer length (the size of the storage space) are transferred to the bus. Notify the adapter 33.

The main memory 32 is a data storage unit having an address space defined by a 32-bit address, and includes a CPU 31 or an input / output device (I / O) 35.
Accessed by In the main memory 32,
Activation information (read / write command, buffer address, buffer length, etc.) for activating the input / output device (I / O) 38 is stored.

The bus adapter 33 connects the first system bus 21 and the second system bus 22 and includes an address conversion mechanism 34, a local memory 35,
An adapter CPU 36 and an adapter internal bus 37 having an address width of 16 bits are provided. Address translation mechanism 34, local memory 35, and adapter CPU
36 are interconnected via an adapter internal bus 37.

The address conversion mechanism 34 converts between a 24-bit address and a 32-bit address between the first system bus 21, the second system bus 22, and the adapter internal bus 37, and converts the 24-bit address. And 1
Conversion with a 6-bit address is performed. The specific configuration of the address translation mechanism 34 will be described later with reference to FIG.

The local memory 35 is a data storage unit having an address space defined by 16-bit addresses, and is normally used as a work area by the adapter CPU 36. In this local memory 35,
The boot information (read / write command, buffer address, buffer length, etc.) specified by the CPU 31 is stored. The adapter CPU 36 controls the bus adapter 33, manages the local memory 35, and the like. An input / output device (I / O) 38 is connected to the second system bus 22 and has a 24-bit address in the main memory 32.
Perform access to. Next, referring to FIG.
A specific configuration of the address translation mechanism 34 will be described.

In FIG. 1, reference numeral 101 denotes an address conversion table. The address conversion table 101 is composed of, for example, a 32-bit × 256-word RAM. The address conversion table 101 includes a first buffer address (16 bits) indicating the storage area of the start information set on the local memory 35 and a second buffer address (32 bits) on the main memory 32 given by the CPU 31. ) Is registered as data, and the storage position of the data indicating these buffer addresses can be specified by an 8-bit address. Also, when reading the data registered in the address conversion table 101, the upper 8-bit address (A) 112 of the 24-bit address (AB) 111 given by the input / output device (I / O) 38 is used. Used as its read address,
As a result, 32-bit data is read from the address conversion table 101.

The address conversion table 101 includes:
Identification information V indicating whether the registered address data is the first buffer address or the second buffer address is registered. The identification information V is provided in the least significant bit of each entry of the address conversion table 101, and the address data registered in the corresponding entry indicates the first storage area on the local memory 35.
Is set to "0" when the buffer address is "2", and is set to "1" when the address data registered in the corresponding entry is the second buffer address indicating the storage area on the main memory 32.

The value of “1” / “0” of the identification information V is set when the adapter CPU 36 registers the first and second buffer addresses in the address conversion table 101. Here, the reason why the identification information V is provided in the least significant bit of each entry is that the least significant bit of the first and second buffer addresses is usually fixed to “0”, and it is not necessary to use the same as an effective address. That's why.

An adder circuit (ADDR) 102 has a first input (IN1) connected to the address conversion table 10 (ADDR).
31 from bit 1 to bit 31 read from 1
Bit data is input as base address 114,
The lower-order 16-bit address (B) 113 of the 24-bit address (AB) 111 is input to the second input (IN2) as an offset address.

The adder (ADDR) 102 adds the base address 114 and the offset address 113 in a state where the digits are aligned, and outputs the 32-bit data resulting from the addition to the error detection circuit 103.

The error detection circuit 103 is for selecting an address output destination according to the value of "1" / "0" of the identification information V. When the identification information V is "1", the adder circuit ( ADDR) outputs 32-bit output data to the first system bus 21 as an address for accessing the main memory 32. When the identification information V is “0”, the error detection circuit 103 uses the lower 16 bits of the 32-bit output data from the adder circuit (ADDR) 102 as an address for accessing the local memory 35. Output to the internal bus 37. In this case, the error detection circuit 103 detects whether or not an overflow has occurred at a 16-bit address for the local memory 35, that is, whether or not a carry has occurred at bit 16, and detects an error when an overflow has occurred. Next, an access operation of the main memory 32 and the local memory 35 by the input / output device (I / O) 38 will be described.

First, the CPU 31 operates the input / output device (I /
O) 38 together with the buffer address and buffer length of the main memory 32 used by the input / output device (I / O) 38
Is supplied to the bus adapter 33. The bus adapter 33 stores, in the empty entry of the address conversion table 101 of the address conversion mechanism 34,
2 is registered. Then, the bus adapter 33 transfers the start information (read / write command, buffer address, buffer length, etc.) from the main memory 32 to the local memory 35 under the control of the adapter CPU 36, and stores it in a predetermined storage area of the local memory 35. . In this case, the value of the buffer address stored in the local memory 35 is not the buffer address of the main memory 32 given from the CPU 31 but the address conversion table 1 in which the buffer address is registered.
It is converted to an entry number of 01. This conversion is performed by the adapter CPU 36.

Thereafter, the adapter CPU 36 registers a buffer address indicating a predetermined storage area of the local memory 35 storing the activation information in a free entry of the address conversion table 101.

As described above, the address conversion table 101
, Two types of address values, a buffer address on the main memory 32 and a buffer address on the local memory 35, are registered. The buffer address on the main memory 32 is represented by 32 bits, and the buffer address on the local memory 35 is represented by 16 bits.

When registering a buffer address on the main memory 32 in the address conversion table 101,
Adapter CPU 36 sets “1” to the V bit of the corresponding entry. On the other hand, the address conversion table 10
When registering the buffer address on the local memory 35 in 1, the adapter CPU 36 sets “0” to the V bit of the corresponding entry.

Next, the adapter CPU 36 notifies the input / output device (I / O) 38 of the erritory number of the address conversion table 101 indicating the buffer address on the local memory 35 and the offset address as a 24-bit buffer address. , Start up. In this case, the upper 8 bits of the 24-bit address are used as the entry number of the registered address conversion table 101, and the lower 16 bits are used as an offset value that makes all “0”.

The activated input / output device (I / O) 38
First, a 24-bit memory address (AB) 111 is supplied to the bus adapter 33 via the second system bus 22 in order to read the activation information. The 24-bit memory address (AB) 111 has the upper 8 bits (A) 1
12 is used as a read address of the address conversion table 101, and the lower 16 bits (B) 113 are used as an offset address. The value of this offset address is all “0”.

The data 114 read from the address conversion table 101 is the buffer address registered in the address conversion table 101 by the bus adapter 33 at the time of startup, and the adapter CPU 36 refers to the V bit to change the buffer address to the main address. It is determined which of the buffer addresses of the memory 32 and the local memory 35 corresponds to the buffer address.

The adapter CPU 36 recognizes that the access is to the main memory 32 when the V bit is "1".
When the bit is “0”, it is recognized that the access is to the local memory 35.

The base addresses from bit 1 to bit 31 read from the address conversion table 101 are added while being digit-aligned with the lower 16 bits (B) 113, and the addition result is sent to the error detection circuit 103. Supplied. In this case, the result of the addition is that when the V bit is "1", all 32 bits are effective addresses,
When the V bit is "0", the lower 16 bits of the 32 bits are the effective address.

When the input / output device (I / O) 38 reads the start information of the local memory 35, the V bit is "0".
R) The lower 16 bits of the 32-bit output from 102 are output to the adapter internal bus 37. At this time, the error detection circuit 103 determines whether or not an overflow has occurred in the 16-bit address of the local memory 35 in the 32-bit output from the addition circuit (ADDR) 102, that is, whether or not the carry to bit 16 exists. When an overflow occurs, an error is detected and adapter C
Notify PU36.

As described above, the local memory 35
The boot information accessed by the bit buffer address and stored in the local memory 35 is passed to the input / output device (I / O) 38.

The input / output device (I / O) 38 recognizes the buffer address of the main memory 32 based on the activation information, and stores the 24-bit memory address (AB) 111 in the second memory.
To the bus adapter 33 via the system bus 22. This 24-bit memory address (AB) 111
The upper 8 bits (A) 112 are used as a read address of the address conversion table 101 and the lower 16 bits (A) are used.
Bit (B) 113 is used as an offset address. The value of this offset address is all “0”.

The read data 114 from the address conversion table 101 is a buffer address on the main memory 32 registered in the address conversion table 101 by the bus adapter 33 at the time of startup, and the adapter CPU 36 sets the V bit to "1". The presence of the buffer address indicates that the buffer address corresponds to the buffer address of the main memory 32.

The base addresses from bit 1 to bit 31 read from the address conversion table 101 are added while being digit-aligned with the lower 16 bits (B) 113, and the addition result is sent to the error detection circuit 103. Supplied. In this case, in the result of the addition, all 32 bits are effective addresses.

The error detection circuit 103 includes an addition circuit (AD
DR) 102 supplies the 32-bit output to the first system bus 21. Thereby, an input / output device (I / O)
38 accesses the main memory 32.

Here, the case where the lower 16 bits (B) 113 of the 24-bit address supplied from the input / output device (I / O) 38 are all "0" has been described.
The value of this offset address is variable within the address range specified by the buffer length given from the CPU 31. As a result, the input / output device (I / O) 38 can access a predetermined address space of the main memory 32.

As described above, in this embodiment, since the start information is preset in the local memory 35 of the bus adapter 33, the input / output device 38 is connected to the main memory connected to the first system bus 21. The access information can be read by accessing the local memory 35 of the bus adapter 33 without accessing the boot memory 32. Therefore, even in a method in which the input / output device (I / O) 38 reads the activation information registered in the main memory 32, the number of times of data transfer via the first system bus 21 is reduced, and the system performance can be improved.

The address conversion table 101 includes:
A buffer address value indicating a storage position of the start information set on the local memory 35, a buffer address value indicating a predetermined storage position in the main memory 32, and a V bit for identifying these addresses are registered. The address value is read by the upper bit address of the second system bus 22, respectively. In this case, which address has been read is identified by the V bit. Therefore, the main memory 32 and the local memory 35
Whichever buffer address is read,
The address of the second system bus 22 is stored in the main memory 3
2 or the local memory 35 can be appropriately converted into addresses for access.

Therefore, access to both the main memory 32 and the local memory 35 can be executed directly, and efficient memory access can be realized without unnecessary data transfer.

Here, the offset address is set to 1
Since it is 6 bits, the buffer length needs to be 64 Kbytes or less. However, if the number of bits of the offset address is increased or if two or more entries of the address conversion table 101 are used, the buffer length of 64 Kbytes is required. Can be handled.

Although the case where the local memory 35 is defined by the 16-bit address has been described, the storage space of the local memory 35 is the same as the 32-bit address of the main memory 32, or an address having an arbitrary number of bits smaller than the 32-bit address. Can be defined as

Further, in this embodiment, the input / output device (I
The access from the (/ O) 38 to the local memory 35 is not particularly limited to read / write. However, assuming that only read from the local memory 35 is permitted,
If the V bit is "0" and the command is a write command, a simple protection circuit can be configured by protecting the information in the local memory 35 as a write error.

[0056]

As described above, according to the present invention, the input / output device can easily read the startup information without accessing the main memory, and the operation performance of the entire electronic computer system can be improved. .

[Brief description of the drawings]

FIG. 1 is a block diagram showing a system configuration of a computer according to an embodiment of the present invention.

FIG. 2 is a block diagram showing an example of a configuration of an address translation mechanism provided in the computer shown in FIG.

FIG. 3 is a block diagram showing a system configuration of a conventional computer.

[Explanation of symbols]

21, 22 ... system bus, 32 ... main memory, 33
... bus adapter, 34 ... address conversion mechanism, 35 ... local memory, 36 ... adapter CPU, 37 ... adapter internal bus, 38 ... input / output device, 101 ... address conversion table, 102 ... adder, 103 ... error detection circuit.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 13/10-13/14

Claims (1)

(57) [Claims] 1. First and second system buses having different address widths, memories and input / output devices respectively connected to the first and second system buses, and the first and second systems In a computer provided with a bus adapter for connecting buses, the bus adapter includes: an internal memory in which activation information for the input / output device registered in the memory is set in advance; A plurality of storage areas that can be specified by an upper bit address, a first address value indicating a storage area of the activation information set in the internal memory, and a predetermined storage area in the memory in each storage area; One of the second address values indicating the space;
Address storage means for registering identification information for identifying the first and second address values; and the second storage area read from a storage area addressed by an upper bit address of the second system bus. Means for generating an address for accessing the memory or the internal memory based on one or a second address value and a value of a lower bit address of the second system bus; and the storage area designated by the address. Means for selecting one of the memory and the internal memory as an access destination based on the identification information read from the memory. The address of the second system bus is stored in the memory or the internal memory. An address conversion method characterized by converting an address for access.