JP2503059B2 - Connection device between different types of buses - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial field of application) The present invention relates to one bus to which a central processing unit and a storage device are connected and the other bus to which a plurality of input / output devices are connected. The invention relates to a connection device between different types of buses.

(Prior Art) Various improvements have been added to the computer system by increasing the storage capacity of the main memory and the like and adding new functions. Along with this, input / output of the input / output control device and input / output channels etc. It is becoming increasingly common to add support for a memory space such as a main storage device and an address conversion function to a system device (hereinafter referred to as an input / output device).

When a new computer system is developed in this way, it is required to connect the I / O device that has been used until now to the system and use it.

FIG. 7 is a diagram showing a conventional connection configuration between a new computer system and an old computer system. In FIG. 7, reference numeral 1 denotes a new computer system, which is a central processing unit (hereinafter referred to as CPU) 2 and a plurality of input / outputs connected to the CPU 2 via a system bus 3. consisting apparatus 4 ₁ to 4 _n and the main memory 5.

On the other hand, the old computer system 6 has CPU 7
It is composed of a plurality of input / output devices 9 _{1 to} 9 _m and a main storage device 10 which are connected to the CPU 7 via an input / output bus 8.

The CPU 2 and the CPU 7 are connected to each other by the adapter device 11.

In the above conventional connection configuration, the input / output command output from the CPU 2 of the new computer system 1 is sent to the CPU 7 of the previous computer system 6 via the adapter device 11,
Performs input and output processing of data by controlling the output device 9 ₁ to 9 _m in the CPU 7, employs an indirect memory access method.

However, in this indirect memory access method, the input / output instruction from the CPU1 cannot be used as it is as the input / output instruction of the CPU7, and the new computer system 1 side has special software for requesting the CPU7 to perform the input / output processing. It will be necessary, and the previous computer system 6 will need other special software to receive and process it. Further, since both systems 1 and 6 are simply connected via the adapter device 11, there is another disadvantage that the scale of the entire system becomes large.

Therefore, an adapter device was added to the new computer system.
Direct connection of previous I / O devices via 11 has been made. Figure 8 shows a direct connection configuration, the previous input and output devices 9 ₁ to 9 _m via the input-output bus 8 is connected to the adapter device 11.

Thus, when directly connecting the previous input / output device, the adapter device 11 mutually converts the input / output control system in the new computer system and the input / output control system in the previous computer system. It is required to add a method conversion function.

In particular, to reduce the load of the CPU2 in the new computer system 1, the input-output device 4 ₁ to 4 _n is the address operation function so as to calculate directly the memory address (channel dynamic address translation function) the device Although it is added to 4 ₁ to 4 _n to directly access the data to the main storage device 5, it is an input / output device of the previous computer system.
9 _{1 to} 9 _m often do not have such a function. Therefore, as described above, the input-output device to the adapter device 11 9 ₁
When directly connecting ~ 9 _m , a channel dynamic address translation mechanism is added to the adapter device 11, and each I / O device 9 ₁ ~
_9m to directly access the memory (hereinafter referred to as the direct memory access method) is performed.

Incidentally, FIG. 9 is a block diagram for explaining a direct memory access method, input and output devices 4 _1, etc. and CPU2 is connected by a program bus 12, a main storage device 5 and output device 4 ₁
Direct memory access bus (hereinafter referred to as DMA bus) etc. 1
Connected at 3.

FIG. 10A is a configuration diagram of the DMA bus 13, which includes a bus use request line 13a, a bus use permission line 13b, an address transmission line 13c, and
It includes a read / write line 13d, a memory response line 13e, a memory access data line 13f and a memory access address line 13g. FIG. 10 (B) is a timing chart at the time of memory access.

Figure 11 shows the contents of the input / output instructions output by CPU2.
Is an input / output command (hereinafter referred to as CF), 15 is a data address (hereinafter referred to as DA), and 16 is a data byte count value (hereinafter referred to as BC).

Now, when CPU2 is sent to the output device 4 ₁ via a program bus 12 to input and output commands shown in FIG. 11, input-output device 4 ₁
Accesses data from the address specified by DA15 of the main memory 5 by the number of words (bytes) specified by BC16.
That is, as shown in FIG. 10 (B), input-output device 4 ₁ performs a bus use request to the CPU2 through the bus request line 13a, C
PU2 is determines that it is possible to bus performs bus grant input and output device 4 ₁ via a bus grant line 13b. As a result, the use of the DMA bus 13 is acquired.

Next, when the address strobe signal is output to the address transmission line 13c, the DA15 is output to the main storage device 5 via the memory access address line 13g. Also, lead /
When the memory response signal to the memory response line 13e and outputs the read / write strobe signal to the write line 13d is sent, output device 4 ₁ writes the read or data data corresponding to the main memory 5 from the address .

(Problems to be Solved by the Invention) As described above, when direct memory access is performed by the input / output device having the channel dynamic address conversion function,
As described above, it is sufficient to simply transfer the DA 15 and the data, and it does not matter which input / output device is being accessed. However, the function is added to the adapter device 11 so that the adapter device 11 can operate a plurality of previous input / output devices.
Since the adapter device 11 cannot recognize from which input / output device the access request is made only by directly accessing the memory by substituting 9 _{1 to} 9 _m , it is possible to operate the input / output devices in parallel. could not.

The present invention has been made in order to solve such a point, and has a function of dynamically allocating a channel, and between different types of buses having a function of surely recognizing which input / output device is an access request. An object is to provide a connection device.

(Means for Solving the Problem) In the heterogeneous bus connection device of the present invention, a system bus to which a central processing unit, a main storage device, and a first input / output device are commonly connected is configured. A second input / output device is connected via a different input / output bus, and an input / output command of the same format as the input / output command to the first input / output device is input via the system bus, and the input / output command is input. Is converted so as to be suitable for the second input / output device and output to the input / output bus.
The I / O command is composed of an I / O command (CF) that indicates the type of command to the I / O device, a data address (DA) that indicates the storage location of the main memory, and a data byte count (BC) that indicates the transfer data amount. It is configured.

Such a heterogeneous bus connection device of the present invention has a system bus interface control unit connected to the system bus, and receives an input / output command to the second input / output device from the system bus interface control unit.

It also has a data buffer divided into a plurality of data blocks, and stores data from the main storage device or data from the second input / output device in this data block.

Further, it has a data block management table for managing this data buffer, and manages the data block by a bank (BNK) indicating the storage position of the data block and a flag indicating the use / non-use of the data block.

Further, it has an address conversion unit for converting the data address (DA) of the input / output command, and the above-mentioned data block management table is provided here. Then, the address conversion unit receives the input / output command, allocates an unused data block by referring to the data block management table, and assigns the bank (BNK) to the data block to the data address of the data block. (DA
(D)) and a new data address (EDA
(D)) is output.

Further, it has a program bus interface (PBI) for outputting the input / output command to the input / output bus, and the input / output command (CF) and the data byte count ( BC) and the new data address (EDA (d)) generated by the address conversion unit described above are output to the input / output bus as a new input / output instruction.

As described above, according to the present invention, the input / output instruction input through the system bus is input / output through the program bus interface unit (PBI) after the data address is converted (EDA (d)) by the address conversion unit. Output to the bus. The data address at this time is a predetermined data block in the data buffer allocated corresponding to this input / output instruction, and data is transferred between different types of buses via this data block.

For this data transfer, a direct memory access interface (DBI) unit for directly outputting the data from the data buffer to the second input / output device and the data from the second input / output device to the data buffer is provided. are doing. In addition, I / O commands (CF,
DA, BC) and the above-mentioned bank (BNK) read data from the main memory and write the data to the data block designated by the bank (BNK), or the bank (BN
The memory access control unit reads data from the data block designated by K) and writes the data in the main memory.

(Operation) As described above, according to the present invention, the input / output instruction to the first input / output device and the input / output instruction to the second input / output device have the same format, and the same format via the system bus. Receive I / O commands. The received input / output instruction is output to the input / output bus via the program bus interface unit (PBI) after the data address is converted (EDA (d)) in the address conversion unit. The data address at this time is a predetermined data block in the data buffer allocated corresponding to this input / output instruction, and data is transferred between different types of buses via this data block.

The second input / output device which has received the input / output command via the input / output bus reads data from the main storage device or writes data to the main storage device via the data block assigned to itself.

According to the present invention, the input / output instruction to the first input / output device and the second input / output instruction
The input / output instructions to the input / output device are the same format, and no special software for converting the input / output instructions is required. Further, since the data block is divided into a plurality of blocks and the unused data block can be used by any input / output device, the input / output operation can be performed in parallel.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of a connection device between different types of buses according to the present invention. In FIG. 1, reference numeral 20 denotes the device of the present invention, which is provided with a system bus interface control unit (hereinafter referred to as SBI unit) 21. The SBI unit 21 receives an input / output command from the CPU 2 (see FIG. 5) via the system bus 3. FIG. 6 is a diagram for explaining an input / output command from the CPU 2, and the command includes an input / output command (CF) 30, a data byte count value (BC) 31 and a data address (DA) 32. When the SBI unit 21 receives the input / output command, it causes the CF30, DA32 and BC31 to access the memory access control unit (hereinafter referred to as MAC) 22.
Transfer to CF30 and BC31 and address translation controller 23
Transfer to The address translation control unit 23, as described later,
After the memory area is controlled to be allocated to any of the I / O devices 9 _{1 to} 9 _m , the address-converted I / O instructions are transferred to the program bus interface control unit (hereinafter referred to as PBI) 2
Transfer to 4. The PBI 24 sends this input / output command to the corresponding input / output device via the program bus 33 and receives an interrupt signal from the input / output device, and the address translation control unit 23
Notify to interrupt.

Further, the heterogeneous bus connection device 20 of the present invention includes a direct memory access interface control unit (hereinafter referred to as DBI) 25. This DBI unit 25 receives a direct memory access from the input / output device, and when reading, a data buffer 26
More relevant data is read and sent to the corresponding input / output device, and in the case of writing, the data from the input / output device is written in the data buffer 26. Further, when the input / output processing of the input / output device is completed and the channel status signal (CSW) is supplied from the input / output device, the DBI unit 25 sends this signal to the address conversion control unit 23 so that the input / output processing is performed. Makes it possible to determine whether or not it has been performed normally.

Now, FIG. 2 is a block diagram of the data buffer 26. That is, the data buffer 26 is provided with a data memory 27, which is divided into four blocks B _{0 to} B ₃ (memory areas), and is formed by a 2-port type memory capable of input / output in both directions. Has been done. Multiplexers 28A, 28 functioning as distribution switches at the ports of each block B _{0 to} B _3.
B is connected.

On the other hand, the address conversion control unit 23 has a data block management table shown in FIG. In this data block management table, table block number 0
3 to ₃ conceptually show each block B _{0 to} B 3 of the data memory 27, and the block bank (BNK) of data is each block B _{0 to} B 3.
_It is used as identification data for identifying ₃ as each memory area, and has a 2-bit configuration. In other words, block B ₀ has “0,0”, block B ₁ has “0,1”, block B ₂ has “1,0”, and block B ₃ has “1,1”. Each corresponds. The data address DA (d) indicates an address for storing the data of each block B _{0 to} B ₃ , and has a 16-bit configuration, for example. Further, the memory area “00000h to 0FFFFh” and the like indicate all addresses from the beginning to the end of each block B _{0 to} B ₃ . Also, the flag is "1" when the memory area (block B _0, etc.) is being used, that is,
The memory area is allocated to any one of the input / output devices, and the flag "0" indicates that the input / output processing is completed and the use of the memory area is canceled.

The heterogeneous bus connection device 20 of the present invention having the above configuration
As shown in FIGS. 1 and 5, the MAC unit 22 and the SBI unit 21
The side is connected to the system bus 3, and the sides of the PBI section 24 and the DBI section 25 are connected to the input / output bus 8. Then, it is connected to a plurality of previous input and output devices 9 ₁ to 9 _m to the input-output bus 8.

The input / output bus 8 is the program bus 33 shown in FIG.
And includes DMA bus 34.

Next, the input / output processing operation of the heterogeneous bus connection device 20 of the present invention will be described.

When the CPU 2 outputs an input / output instruction including CF30, BC31, DA32 (see FIG. 6), the SBI unit 21 receives this input / output instruction via the system bus 3 and sends the CF30, BC31, to the address translation control unit 23. CF30, DA32, and BC31 are simultaneously transferred to the MAC unit 22
Transfer to

Next, the address translation control unit 23 searches for a flag, selects an unused block having the flag “0”, for example, the block B _0, and always starts the access at the start address so that the access is started from the head address of the block B _0. BNK "0,0" corresponding to the data address DA (d) of 0 "is added, and this address EDA (d)
(DA (d) + BNK "0,0" together with CF30 and BC31 in PBI section 24
It is transferred as an I / O instruction whose address is converted to. Figure 4 shows this address-converted input / output instruction. Address EDA with BNK "0,0" added to the first 2 bits.
It consists of (d) and BC31 and CF30. The address translation control unit 23 also transfers BNK “0,0” to the MAC unit 22, and holds the DA 32 and BC 31 transferred from the SBI unit 21 as they are.

Next, the PBI unit 24 sends the transferred I / O instruction to the CPU 2
It is sent to any of the input / output devices specified in step 1, for example, the input / output device 9 _m . The I / O device 9 _m that receives this I / O command starts from the address of block B ₀ specified by DA (d).
Access is started for the number of words specified by BC31. That is, the input / output device 9 _m is BNK indicating the block B ₀ in DA (d).
"0,0" is added and CF30 and BC31 are output to the DBI unit 25.

With this access, the DBI unit 25 reads BNK “0,0” from the data memory 27 of the data buffer 26 if the CF 30 is read.
The corresponding data is read from the address DA (d) of the block B ₀ indicated by and the data is output to the input / output device 9 _m . Further, write data from the input-output device 9 _m to the address of the block B ₀ DA (d) if CF30 is a write. That is, when BNK "0,0" is input to the data buffer 26, the multiplexer 28B selects the block B ₀ , as shown in FIG. 2, so that the DBI unit 25 only has to read or write data. .

Also, the MAC unit 22 is DA32, BC3 transferred from the SBI unit 21.
1 and the BNK “0,
By 0 ", and stores the data read from the main memory 5 if read address of the block B ₀ DA (d), also address of the block B ₀ if writing DA
The data is read from (d) and written in the main storage device 5. Also in this case, the multiplexer 28A automatically selects the block B ₀ with the BNK "0,0".

When another input / output instruction is output from the CPU2, BNK "0,1", "1,0" or "1,1" is similarly added to DA (d) by the address translation control unit 23, Other blocks B ₁ , B ₂ , B ₃
Is assigned to another I / O device, the address is converted, and the I / O command including BNK is sent to the corresponding I / O device. Therefore, in this embodiment, the blocks B ₀ to
The number of B _3, i.e., it is possible to allocate four memory areas to the input and output device can be operated in parallel to four input-output device.

It goes without saying that the identification data may be any data as long as it can identify each memory area.

(Effects of the Invention) As described above, in the present invention, the input / output instruction to the first input / output device and the input / output instruction to the second input / output device have the same format. Therefore, no special software for converting input / output instructions is required.

Further, in the present invention, when an input / output command is received, an unused data block is searched for and the data block is allocated for data transfer. Then, upon receipt of another I / O command, it similarly looks for an unused data block and allocates that data block for data transfer. Therefore, if there is an unused data block, another input / output instruction can be executed, and the input / output operation can be performed in parallel. Therefore, even an input / output device before having no channel dynamic conversion function can be operated in parallel in a computer system having an input / output operation including the function.

[Brief description of drawings]

FIG. 1 is a block diagram of a heterogeneous bus connection device according to the present invention, FIG. 2 is a configuration diagram of a data buffer according to the present invention, and FIG. 3 is a diagram showing a data block management table of the present invention.
FIG. 4 is a diagram showing I / O instructions whose addresses have been converted, FIG. 5 is a diagram showing a connection configuration of a direct memory access system using the apparatus of FIG. 1, and FIG. 6 is an input / output of the CPU shown in FIG. FIG. 7 is a diagram showing instructions, FIG. 7 is a diagram showing a connection configuration of an indirect memory access system, FIG. 8 is a diagram showing a connection configuration of a conventional direct memory access system, and FIG. 9 is a diagram explaining a direct memory access system, 10 (A) and 10 (B) are diagrams showing the structure of the DMA bus and the timing chart of the direct memory access method shown in FIG. 9, and FIG. 11 is a diagram showing input / output instructions of the CPU shown in FIG. is there. _{2 ...... CPU, 9 1 ~9 m} ...... previous input device, 21 ...... SBI unit, 22 ...... MAC unit, 23 ...... address conversion control unit, 24 ...... PBI unit, 25 ...... DBI unit, 26 …… Data buffer, 28A, 28B …… Multiplexer, B _{0 to} B ₃ …… Block.

Claims (1)

(57) [Claims] 1. A second input / output device is connected to a system bus to which a central processing unit, a main storage device, and a first input / output device are commonly connected, via an input / output bus having a configuration different from that of the system bus. While connecting, an input / output command of the same format as the input / output command to the first input / output device is input through the system bus, and the input / output command is converted to be compatible with the second input / output device. And an output command to the input / output bus, wherein the input / output command indicates an input / output command (CF) indicating a type of command to the input / output device and a storage position of the main storage device. A heterogeneous bus connecting device composed of a data address (DA) and a data byte count (BC) indicating a transfer data amount, which is connected to the system bus and receives an input / output command to the second input / output device. System Bus An interface control unit, a data buffer that is divided into a plurality of data blocks, and stores the data from the main storage device or the data from the second input / output device in the data blocks, and the storage of the data blocks in the data buffer. A data block management table for managing the data block by a bank (BNK) indicating the position and a flag indicating the use / non-use of the data block is provided, and when the input / output command is received, the data block management table is referred to and the An address for allocating a data block to be used, and adding the bank (BNK) that spans the data block to the data address (DA (d)) of the data block and outputting it as a new data address (EDA (d)). A conversion unit, and among the input / output instructions input via the system bus, Output command (CF) and the data byte count (BC),
And a program bus interface unit (PBI) that outputs the new data address (EDA (d)) as a new input / output instruction to the input / output bus, and data from the data buffer to the second input / output device. A direct memory access interface (DBI) unit for directly outputting the data from the second input / output device to the data buffer, and an input / output command input via the system bus (the above-mentioned
CF, DA, BC) and the bank (BNK) to read data from the main memory and write the data to the data block specified by the bank (BNK), or the data block specified by the bank (BNK) And a memory access control unit for reading data from the memory and writing the data in a main storage device.