JPH04348442A - Address converter - Google Patents

Abstract

PURPOSE:To constitute a conversion index buffer with a small hardware quantity by outputting a physical address when the channel identifier of an I/O device requesting an I/O and the channel identifier included in an address conversion index buffer are matched. CONSTITUTION:A calculator contains an I/O device 31, an I/O device channel 24, a main storage 23, a CPU 21, and an address converter 20 which converts the logical address outputted from the device 31 into a physical address used for access given to the storage 23. In this case, the converter 20 is provided with an address conversion index buffer containing a channel identifier, a logical address, and a physical address corresponding to the logical address and a desiding means. Then the physical address of conversion index buffer is outputted to the storage 23 when the device 31 has an access to the storage 23 and the coincidence is decided between the logical address of the device 31 and the logical address included in the conversion index buffer and also between the channel indentifiers of the device 31 and the buffer respectively.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device for controlling data transfer between an I/O (Input/Output) device and a storage device in an information processing system, and particularly to an address translation device.

0002

2. Description of the Related Art Conventionally, there has been a so-called address conversion technique in which a logical address output by a CPU is converted into a physical address, which is an actual memory address, and a main storage device is accessed.

[0003] In such a system, it is known to provide an address translation means so as to perform address translation on the address output by the I/O device.

[0004] As an example of such data transfer, DM
There is an A.

However, if the conversion table is referred to each time DMA is performed, the reduction in transfer speed due to the overhead may become so large that it cannot be ignored.

Therefore, as shown in FIG.
There is a technique described in Japanese Patent Laid-Open No. 193961, in which a conversion index buffer 29 is provided corresponding to the O device channel 24.

[0007] In FIG. 3, a logical address 26 output from the CPU 21 is converted into a physical address 27 through an address translation device 22, and the main storage device 23 is accessed.

The conversion index buffers 29-1 to 29-n are
One channel is provided for each channel number of each I/O device channel 24-1 to 24-n.

On the other hand, the first I/O device 31-1 to the nth I/O device 31-1 to
When the O device 31-n accesses the main memory, the I/O device 31 outputs the I/O output address 25, which is a logical address, and the first conversion index buffer 29 in the DMA address conversion device 20. −1 to nth conversion index buffer 2
The data corresponding to the logical page address and physical page address in 9-n is converted into a DMA physical address 18.

When there is no logical page address in the conversion index buffer, the I/O output page address 12 is
The address is output to a DMA page conversion table 7, and converted into a physical page address 15 using this table.

[0011]

[Problems to be Solved by the Invention] The above-mentioned conventional technology
Since a conversion index buffer is provided for each channel of the O device, there is a problem in that a multi-channel system requires a large amount of hardware for the conversion index buffer.

An object of the present invention is to provide an address translation device in which a translation index buffer is configured with a small amount of hardware.

[0013]

[Means for Solving the Problems] In order to solve the above problems, the present invention provides a plurality of I/O (Input/O
At the time of data transfer between the above-mentioned I/O device and the above-mentioned storage means performed within an information processing system having an output) device, a plurality of I/O device channels, a storage means, and a central processing unit (CPU), In an address translation device having a conversion means for converting a logical address output by the I/O device into a physical address for accessing the storage device, a channel identifier of the I/O device, the logical address, and the An address translation index buffer having the above-mentioned physical address corresponding to the logical address, and a determining means are provided, and the above-mentioned determining means has a channel identifier of the I/O device requesting I/O and the above-mentioned physical address corresponding to the logical address. When the above channel identifier matches, the physical address is output.

[0014]

[Operation] The I/O device accesses the storage means, matches the logical address in the output address of the I/O device with the logical address in the conversion index buffer, and converts the channel identifier of the I/O device. When the determination means determines that a match with the channel identifier in the index buffer is obtained, the physical address of the conversion index buffer is output to the storage means.

[0015]

[Embodiment] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 shows a block diagram of an information processing system to which the present invention is applied.

[0017] This system includes a CPU 21 and a CPU 21.
and an address translation device 22 that performs address translation between main storage devices 23, a main storage device 23 that is a storage means, a DMA address translation device 20 that is an address translation device according to the present invention, and an I/O device 24-1. ~24-n and I/O
It has device channels 31-1 to 31-n, a DMA page conversion table 7, and a bus occupancy control device 6.

FIG. 1 shows a DMA, which is an address translation device.
Address translation index buffer 1 in address translation device 20
FIG. 2 is a diagram showing an address multiplex/hit determination circuit 2 which is a determination means therefor.

The DMA address translation device 20 has channel numbers 8-1 to 8-m as channel identifiers, I/O page addresses 9-1 to 9-m as logical addresses, and physical page addresses 10- as physical addresses. address translation index buffers 1-1 to 1-m having V bits 1 to 10-m and V bits 11-1 to 11-m;
It has an MA page conversion table read circuit 51, a clear circuit 5, and an update pointer 54.

Of the I/O output addresses 25 output by the I/O device 31, the I/O page address 12 is applied to the address multiplex/hit determination circuit 2.

Here, this I/O page address 12 and the first I/O page address 9-1 to the m-th I/O page in the first address translation index buffer 1-1 to the m-th address translation index buffer 1-m are used. A comparison is made with addresses 9-1 to 9-m.

This comparison is made between the occupancy permission channel number 14 output from the bus occupancy control circuit 6 and the channel number 8-1 held by the address conversion index buffers 1-1 to 1-m.
.about.8-m is performed for the matching conversion index buffer.

When these match and the values of V bits 11-1 to 11-m of the address translation index buffer are 1, it is determined that there is a hit, and the physical page address 17 of the translation index buffer that has been hit is First I/O device 31
The in-page address 13 outputted by the −1 to n-th I/O devices 31-n is combined by the adder circuit 3, and outputted from the output circuit 4 to the main storage device as a DMA physical address 18.

If the above-mentioned match is not obtained in all conversion index buffers, it is determined that there is a miss, and the DMA
The page conversion table 7 is referred to and the physical page address 17 corresponding to the I/O page address 12 is output.

The operation when no hit occurs in the conversion index buffers 1-1 to 1-m will be described.

In that case, it is necessary to retrieve the contents of the DMA page conversion table 7 from the main memory.

Therefore, the miss-hit signal 50 is outputted from the address multiplex/hit determination circuit 2 of FIG. 1 to the DMA page conversion table read circuit 51, and this circuit
A page conversion table access request signal 52 is output.

[0028] As a result, the DMA page conversion table 7
is accessed, and a physical page address 17 is generated from the I/O page address 12. At this time, the update pointer 28 provided in the DMA conversion device 20
Activate any one of 0-1 to 30-m. The update pointer 28 is a loop counter and loops through the values 1 to m.

When the pointer signal 30 becomes active, the conversion index buffers 1-1 to 1-m receive the physical page address 15 from the DMA page conversion table 7 and the I/O page sent from the I/O via the bus 25. address 12
, an occupancy permission channel number 14 indicating the channel number of the master I/O is set in each field, and 1 is set in the V bit 11.

After this processing, the value of the update pointer 28 is incremented. The update pointer 28 wraps around the number of conversion index buffers (m) as the maximum value.

The number m of conversion index buffers and the first I/O device channel 24-1 to the nth I/O device channel 24-n
It is not necessary to match the number of channels n, and it is sufficient to provide as many conversion index buffers as determined by the constraints on the amount of hardware. According to this embodiment, even in a multi-channel system, the amount of hardware can be reduced. Therefore, the data transfer time can be reduced by using the address translation index buffer.

On the other hand, if it is necessary to reset the DMA page conversion table, it is necessary to disable the conversion index buffer after the setting.

In this case, the address of the clear circuit 5 is set to CP.
By performing access 19 from U, 0 is written to the V bits of all conversion index buffers.

This ensures consistency of the conversion index buffer with the DMA page conversion table.

In the above embodiment, a conversion index buffer is provided for each channel, but the present invention is not limited to this, and a conversion index buffer may be provided for each I/O device.

As described above, according to the present invention, DMA processing can be performed using an address translation index buffer with a small amount of hardware.
This has the effect of reducing data transfer time.

Furthermore, the V bit clear circuit guarantees consistency of the conversion index buffer with the DMA page conversion table, so even when multiple application programs using different DMA maps are run at the same time, the conversion index buffer will not be mistaken. This has the effect that there is no need for additional conversion.

Furthermore, since the clear circuit simultaneously disables all conversion buffers, initialization after resetting the address conversion table can be performed at high speed.

[0039]

[Effect of the invention] Since it is configured as described above,
According to the present invention, it is possible to provide an address translation device in which a translation index buffer is configured with a small amount of hardware.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a translation index buffer section and a hit determination section in a DMA address translation device according to an embodiment of the present invention.

FIG. 2 is a block diagram of a computer system according to an embodiment of the present invention.

FIG. 3 is a block diagram of a system according to the prior art.

[Explanation of symbols]

1-1 to 1-m...DMA address conversion index buffer, 2
...Address multiplex/hit determination circuit, 5...V bit clear circuit, 7...DMA page conversion table, 20
...DMA address translation device.

Claims (6)

[Claims] Claim 1: Multiple I/O (Input/Output)
) device, a plurality of I/O device channels, storage means,
When data is transferred between the I/O device and the storage means in an information processing system having a central processing unit (CPU), a logical address output by the I/O device is used to access the storage means. an address translation index buffer having a channel identifier of an I/O device, the logical address, and the physical address corresponding to the logical address; provide means,
The address translation device is characterized in that the determining means outputs the physical address when the channel identifier of the I/O device requesting I/O matches the channel identifier in the address translation index buffer. . 2. Data between the I/O device and the storage means performed in an information processing system having a plurality of I/O devices, a plurality of I/O device channels, a storage means, and a CPU. The logical page output by the above I/O device during transfer
In an address translation device having a translation means for converting a page address to a physical page address for accessing the storage means, a channel identifier, the logical page address, the physical page address, and the contents of the buffer are stored. An address translation index buffer having valid information indicating validity, a determining means, and an addition circuit are provided, and the determining means includes a channel identifier of an I/O device requesting I/O and the address translation index buffer. Outputs the physical page address when the above channel identifier matches,
The addition circuit receives the physical page address and the I/O address.
An address translation device characterized in that it generates a physical address for accessing the storage means by adding an intra-page address output from an O device. 3. Means for rewriting the address translation index buffer, wherein the rewriting means requires the above-mentioned channel identifier matching, logical page address matching, and validity information to be values indicating validity. 3. The address translation device according to claim 2, wherein if there is no address translation index buffer that satisfies the above conditions, the channel identifier, logical page address, and physical page address are rewritten, and the validity information is set to a value indicating validity. 4. The address translation device according to claim 3, further comprising an update pointer for specifying an address translation index buffer to be rewritten. 5. The address translation device according to claim 2, further comprising a clear circuit for invalidating valid information in all said address translation index buffers using a symbol from the CPU. 6. An information processing system comprising the address translation device according to claim 1, 2, 3, 4 or 5.