JP3124778B2 - Address translator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device for controlling data transfer between an input / output (I / O) device and a storage device in an information processing system, and more particularly to an address conversion device.

[0002]

2. Description of the Related Art Conventionally, there has been a so-called address conversion technique in which a logical address output from a CPU is converted into a physical address which is an actual memory address to access a main storage device.

In such a system, it is known to provide an address conversion means for performing an address conversion even on an address output from an I / O device.

As one example of such data transfer, DM
There is A.

However, if the conversion table is referred to each time the DMA is performed, the reduction in the transfer speed due to the overhead may become too large to ignore.

Therefore, as shown in FIG. 3, n I / Os
Corresponding to O device channel 24 provided translation lookaside buffer 29 there is a technique described in JP-A No. 1 -193961 called.

[0007] The logical address 26 output from the CPU 21 in FIG. 3 is converted to a physical address 27 through the address conversion device 22 and accesses the main storage device 23.

The conversion index buffers 29-1 to 29-n are:
One channel number is provided for each I / O device channel 24-1 to 24-n.

On the other hand, the first I / O devices 31-1 to nI /
When the O device 31-n accesses the main memory, the I / O device 31 outputs the I / O output address 25, which is a logical address, and outputs the first translation index buffer 29 in the DMA address translation device 20. -1 to n-th conversion index buffer 2
The data is converted to the DMA physical address 18 by the data corresponding to the logical page address and the physical page address in 9-n.

When there is no logical page address in the translation index buffer, the I / O output page address 12 is
The data is output to the DMA page conversion table 7 and is converted into the physical page address 15 by using this table.

[0011]

The above prior art is based on I / O
Since a conversion index buffer is provided for each channel of the O device, there is a problem that the amount of hardware required for the conversion index buffer increases in a multi-channel system.

An object of the present invention is to provide an address translation device in which a translation look-aside buffer is configured with a small amount of hardware.

[0013]

In order to solve the above-mentioned problems, according to the present invention, there are provided a plurality of I / O (Input / Output) devices, a plurality of I / O device channels, storage means, and a central processing unit. An I / O device performed in an information processing system having a device (CPU), and a logical address output by the I / O device when data is transferred between the storage means, for accessing the storage means. In an address translation device having translation means for translating into an address,
An address conversion index buffer having a channel identifier of an I / O device, the logical address, and the physical address corresponding to the logical address; and a determination unit, wherein the determination unit is configured to request an I / O request. When the channel identifier of the O device matches the channel identifier in the address translation look-up buffer, the physical address is output.

[0014]

The I / O device accesses the storage means, matches the logical address in the output address of the I / O device with the logical address in the translation look-up buffer, and converts the logical identifier into the channel identifier of the I / O device. When the determination unit determines that the match with the channel identifier in the index buffer is obtained, the physical address of the conversion index buffer is output to the storage unit.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 shows a block diagram of an information processing system to which the present invention is applied.

This system comprises a CPU 21 and a CPU 21
And an address translation device 22 that performs address translation between the main storage devices 23, a main storage device 23 that is a storage unit, a DMA address translation device 20 that is an address translation device according to the present invention, and an I / O device 24-1. ~ 24-n and I / O
It has device channels 31-1 to 31-n, a DMA page conversion table 7, and a bus occupation control device 6.

FIG. 1 shows a DMA which is an address translation device.
Address translation look-up buffer 1 in address translation unit 20
FIG. 3 is a diagram showing an address multiplex / hit determination circuit 2 which is a determination means of the present invention.

The DMA address translator 20 includes channel numbers 8-1 to 8-m as channel identifiers, I / O page addresses 9-1 to 9-m as logical addresses, and physical page addresses 10- as physical addresses. Address conversion look-up buffers 1-1 to 1-m having 1 to 10-m and V bits 11-1 to 11-m;
It has an MA page conversion table read circuit 51, a clear circuit 5, and an update pointer 54.

The I / O page address 12 of the I / O output address 25 output from the I / O device 31 is applied to the address multiplex / hit determination circuit 2.

Here, the I / O page address 12
Is compared with the first I / O page address 9-1 to the m-th I / O page address 9-1 to 9-m in the first address conversion index buffer 1-1 to the m-th address conversion index buffer 1-m. Done.

This comparison is made between the occupation permitted channel number 14 output from the bus occupation control circuit 6 and the channel number 8-1 stored in the address conversion index buffers 1-1 to 1-m.
.About.8-m.

If these match and the value of the V bits 11-1 to 11-m of the relevant address translation index buffer is 1, it is determined that a hit has occurred, and the physical page address 17 of the hit translation index buffer and First I / O device 31
The in-page address 13 output from the -1 to n-th I / O devices 31-n is combined by the adder circuit 3 and output from the output circuit 4 as a DMA physical address 18 to the main storage device.

If the above match is not obtained in all of the conversion look-up buffers, it is determined that there is a miss, and the DMA is determined.
The physical page address 17 corresponding to the I / O page address 12 is output with reference to the page conversion table 7.

The operation when no hit is found in the conversion index buffers 1-1 to 1-m will be described.

In this case, it is necessary to bring the contents of the DMA page conversion table 7 from the main memory.

Therefore, a mishit signal 50 is output from the address multiplex / hit determination circuit 2 of FIG. 1 to the DMA page conversion table read circuit 51, and this circuit
An A page conversion table access request signal 52 is output.

Thus, the DMA page conversion table 7
Is accessed, and a physical page address 17 is generated from the I / O page address 12. At this time, the update pointer 28 provided in the DMA conversion device 20 indicates the pointer signal 3
Activate any one of 0-1 to 30-m.
The update pointer 28 is a loop counter, and loops the values of 1 to m.

The conversion look-up buffers 1-1 to 1-m receiving the activation of the pointer signal 30 send the physical page address 15 from the DMA page conversion table 7 and the I / O page sent from the I / O via the bus 25. Address 1
2. The occupation permission channel number 14 indicating the channel number of the master I / O is set in each field, and 1 is set to the V bit 11.

After this processing, the value of the update pointer 28 is incremented. The update pointer 28 wraps around with the number (m) of the conversion index buffers as the maximum value.

The number m of conversion look-up buffers, the first I / O device channel 24-1 to the n-th I / O device channel 24-n
Need not be equal to the number n of channels, and the conversion index buffer may be provided by an amount determined by the restriction of the amount of hardware. Therefore, according to this embodiment, even in a multi-channel system, a small amount of hardware is required. Thus, the data transfer time can be reduced by the address conversion look-up buffer.

On the other hand, when it is necessary to reset the DMA page conversion table, it is necessary to invalidate the conversion index buffer after setting.

In this case, the address of the clear circuit 5 is
By performing access 19 from U, 0 is written to the V bits of all the conversion look-up buffers.

As a result, the consistency between the conversion index buffer and the DMA page conversion table is guaranteed.

In the above embodiment, the conversion index buffer is provided for the channel. However, the present invention is not limited to this. The conversion index buffer may be provided for the I / O device.

As described above, according to the present invention, with a small amount of hardware, the DMA by the address translation look-aside buffer is used.
The data transfer time can be shortened.

Further, since the V bit clear circuit guarantees the consistency between the conversion index buffer and the DMA page conversion table, the conversion index buffer is incorrect even when a plurality of application programs using different DMA maps are run simultaneously. There is an effect that no conversion is performed.

Further, since the clear circuit invalidates all the conversion buffers at the same time, initialization after resetting the address conversion table can be performed at high speed.

[0039]

[Effect of the Invention] Since the configuration is as described above,
According to the present invention, it is possible to provide an address translation device in which a translation index buffer is configured with a small amount of hardware.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a translation index buffer unit and a hit determination unit in a DMA address translation device according to one embodiment of the present invention.

FIG. 2 is a block diagram of a computer system according to one embodiment of the present invention.

FIG. 3 is a block diagram of a system according to the related art.

[Explanation of symbols]

1-1 to 1-m... DMA address conversion look-up buffer, 2
... Address multiplex / hit determination circuit, 5 ... V bit clear circuit, 7 ... DMA page conversion table, 20
... DMA address converter.

──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Kazushi Kobayashi 1 Horiyamashita, Hadano-shi, Kanagawa Hitachi, Ltd. Kanagawa Plant (72) Inventor Takanori Ishikawa 5-2-1 Omika-cho, Hitachi City, Ibaraki Prefecture Hitachi Process Computer Engineering Co., Ltd. (56) References JP-A-64-32366 (JP, A) JP-A-1-102667 (JP, A) JP-A-2-310648 (JP, A) 4-120650 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) G06F 12/08-12/12 G06F 13/10-13/14 G06F 13/20-13/378

Claims (6)

(57) [Claims] An I / O (Input / Output) device, a plurality of I / O device channels, storage means, and a central processing unit (CPU). At the time of data transfer between the O device and the storage means,
An address translation device having translation means for translating a logical address output by the I / O device into a physical address for accessing the storage means, comprising: a channel identifier of the I / O device; the logical address;
An address translation index buffer having the physical address corresponding to the logical address; and a judging unit, wherein the judging unit comprises: a channel identifier of an I / O device requesting I / O; And the I / O device outputs
Logical address and the address translation index buffer
When the above logical address matches, the logical address
An address translation device for outputting a physical address in the address translation look-up buffer corresponding to the address . 2. An I / O device implemented in an information processing system having a plurality of I / O devices, a plurality of I / O device channels, a storage means, and a CPU, and data between the storage means. during the transfer, the address translator having a conversion means for converting the logical rear de <br/> less that the I / O device outputs the object rear dress for accessing said memory means, and channel identifier A logical page address included in the logical address, a physical page address included in the physical address, and an address translation index buffer having valid information indicating the validity of the contents of the buffer, a determination unit, and an addition circuit, The determination means determines that the channel identifier of the I / O device requesting the I / O matches the channel identifier in the address translation look-up buffer , and that the I / O device Is output
Logical page address included in the logical address
Logical page address in the address translation index buffer
Address conversion index buffer
And the adder circuit outputs the physical page address and the I / O
An address translation device, wherein a physical address for accessing the storage means is generated by adding an in-page address output from the O device. 3. A rewriting means for rewriting an address translation index buffer, wherein said rewriting means has a value indicating that said channel identifier coincides, said logical page address coincides, and said validity information is valid. If the address translation lookaside buffer to meet the requirements does not exist, the address translation lookaside buffer
Rewritten channel identifier and the logical page address and the physical page address of the internal, the address translation lookaside buffer
3. The address translation device according to claim 2 , wherein the validity information in the address is a value indicating validity. 4. The address translation device according to claim 3, further comprising an update pointer for designating an address translation index buffer to be rewritten. 5. The address translation device according to claim 2, further comprising a clear circuit for invalidating valid information of all of said address translation look-up buffers in accordance with a symbol from a CPU. 6. An information processing system comprising the address translation device according to claim 1, 2, 3, 4, or 5.