JPH06187286A - Bus conversion adapter - Google Patents

Abstract

PURPOSE:To attain the high speed of a system bus by providing an address conversion means that a bus conversion adapter accesses on the DMA (direct memory access) map table placed on a main storage and eliminating an address conversion in the transfer on a system bus, in a computer system having a bus hierarchy structure. CONSTITUTION:Bus conversion adapters 105, 106 connect a high order system bus 104 with plural I/O buses 107, 108 which are different in specifications and perform a bi-directional address conversion between the address space of these two kinds of buses 107, 108. When DMA requests are given from the I/O devices 109, 110, bus conversion adapters 105, 106 convert a logical address into a physical address after permissions are given for the DMA requests, and the bus conversion adapters themselves become the DMA master of a system bus 104 and request bus rights.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus conversion adapter for connecting two different buses in a computer system having a bus hierarchical structure, and an address conversion method and DM.
A method for controlling A (Direct Memory Access).

[0002]

2. Description of the Related Art In a computer system in which a CPU, a main storage device and an I / O (Input / Output) device are connected to a system bus, an address translator is located between the system bus and the main storage device, An example is known in which address translation is performed for access from an I / O device to a main storage device.

At this time, the address conversion for converting the logical address output from the CPU or I / O device into the physical address is
A DMA map table is placed in a high-speed memory that is provided alongside the address translation device or in the main storage device itself, and that memory is accessed.

Since a large capacity of hardware is required when a high-speed memory is installed side by side in the address translation device, a DMA map table is placed in the main storage device in order to solve the problem of mounting hardware components. It has become to.

FIG. 2 shows an example of the configuration of a conventional computer system in which a DMA map table is placed in the main storage device. Here, the address translation device 203 is the I / O device 1.
When the DMA request from 09 is received, the main storage device 10
The DMA map in 2 is drawn to perform address conversion, and the main storage device 102 is accessed.

Further, the frequency of memory access is reduced to reduce D
As means for increasing the speed of MA, for example, Japanese Patent Laid-Open No. 1-10
As described in Japanese Patent No. 2667, I
A translation lookaside buffer (TLB) is provided for each / O channel device, and if the TLB device has a required physical address, it is used.

On the other hand, in a computer system which requires higher speed performance, a bus hierarchical structure is provided, an I / O device having a relatively slow transfer performance is placed in a lower bus, and a transfer speed is set in an upper system bus. Connect only fast devices,
It is improving the overall performance.

[0008]

FIG. 1 is an example of a computer system having a bus hierarchy structure. The lower bus outputs a logical address for designating the start address of DMA I
An I / O bus to which an I / O device is connected, a higher-order bus is a system bus, and a bus controller (BC) 103 is connected.

The main memory device 102 is a bus controller (BC).
CPU 101 and system bus 10 with 103 as an intermediary
4 and all of them operate in the physical address space, no address translation is required for transfer between devices connected to the system bus and bus control device.
Achieves high-speed performance.

In such a computer system, a bus conversion adapter 10 for connecting two different buses.
5 and 106 have different upper bus address space and lower bus address space, it is necessary to internally provide an address conversion mechanism between these buses.

On the other hand, when the DMA map table is placed in the main memory to facilitate the rewriting of the data in the table or to reduce the resources of the hardware, the bus conversion adapter itself activates the DMA. , DMA
A means to refer to the map table is needed.

[0012]

[Means for Solving the Problems] The bus conversion adapter includes:
I / O bus control means for arbitrating DMA requests issued from I / O devices on the I / O bus, and address translation means for translating a logical address on the I / O bus into a physical address to be output to the system bus. , DMA issuing means for issuing a DMA request to the system bus is provided.

A map address for setting an access destination address to a table position corresponding to an address output by the I / O device in the DMA map table for the means for enabling DMA to the main memory device in the bus conversion adapter. A synthesizing means is provided.

The address translation means is provided with a TLB, and a page number in a logical address, a page frame number of a physical address corresponding to the page number, and a flag (V flag) indicating that this page frame number is a valid value.
Remember the contents of. When the page number of the DMA logical address does not match the content of TLB, and TL
When the V flag of B indicates invalidity (at the time of TLB mishit), a means for detecting that and activating DMA read and outputting the address for accessing the DMA map area of the main memory is provided.

Further, when an error occurs on the system bus during the DMA map access, means for reporting the error to the I / O device which issued the DMA request is provided.

[0016]

The bus control of the system bus is performed by removing the I / O device having low transfer performance from the system bus, placing it on the I / O bus connected by the bus conversion adapter, and providing the address conversion means in the bus conversion adapter. Since the address conversion means can be eliminated from the device, the high speed performance of the system bus can be further improved.

By providing the bus conversion adapter with means for activating a DMA read at the time of a TLB miss, even in a computer system having a bus hierarchy structure, D
The MA map table can be located in main memory. Therefore, there is a problem in mounting the hardware parts on the DMA.
The storage element for the map table can be eliminated.

Further, a system bus error at the time of DMA map access is prevented from occurring when I / O which is a DMA master on the I / O bus.
By providing a means for reporting to the O device, there is no problem in operation even if the DMA is activated for the DMA map access.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows an example of the configuration of a computer system to which the present invention is applied.

This system includes a CPU 101, a main storage device 102, a system bus control device 103, a system bus 104, bus conversion adapters 105 and 106, an I
I / O buses 107 and 108 and I / O devices 109 and 110
It consists of and. A channel number is assigned to the I / O device connected to each I / O bus, and the bus conversion adapters 105 and 106 specify the channel number and DM
Give A permission. The I / O buses 107 and 108 have different specifications.

Of these, 105 and 106 are examples of the present invention.

The bus conversion adapters 105 and 106 are I
A buffer for holding the DMA logical address and data output from the / O device is provided internally. After the addresses (and write data) output by the I / O devices 109 and 110, which have been granted the DMA request, are prepared in the buffer, the addresses are converted into physical addresses in the system bus address space. The bus conversion adapter itself becomes the DMA master of the system bus and requests the bus right.

By providing such means, even if the transfer performance of the I / O device is slow, the transfer is performed to the upper system bus in accordance with the specifications of the high-speed system bus, so that the performance of the entire system is improved. You don't have to drop it.

The address of the system bus 104 is
Since it is a physical address and the CPU 101 also outputs the physical address, the system bus control device 103 has no address conversion means. I / O buses 107 and 108 are DMA
Since a logical address is sometimes output, the bus conversion adapter 1
Address conversion circuits are provided at 05 and 106. Therefore, the transfer on the system bus does not require address conversion processing, which is useful for improving the performance of the system bus.

FIG. 3 shows the relationship between the system bus and the address spaces of the I / O bus 1 and I / O bus 2. CPU
When an apparatus on the system bus 104 including the bus 101 and the bus conversion adapters 105 and 106 accesses an address corresponding to the I / O space 1 of the system bus, the address conversion circuit converts the address into the address of the I / O bus 1. It This address conversion is realized by a small-scale address conversion table in the bus conversion adapter because only a few bits of the address are replaced with a fixed value corresponding to one to one.
The same applies to access to the I / O space 2.

On the other hand, the I / O device 109 on the I / O bus 1
When the address corresponding to the DMA window of the I / O bus 1 is accessed (DMA is performed), the address conversion circuit accesses the DMA map table to correspond to the main storage space in the system bus address space. Converted to an address. The same applies to the I / O bus 2. In this case, D of each of I / O buses 1 and 2
The DMA map tables corresponding to the MA windows may be the same, or separate DMA map tables may be prepared as shown in FIG.

The operation procedure of address conversion during DMA in the bus conversion adapter will be described with reference to FIGS. 4 and 5.

FIG. 4 is a diagram showing the details of the address conversion circuit and the DMA control unit in the bus conversion adapter 105.
The bus conversion adapter 106 has the same function.

The bus conversion adapter 105 has the channel number 2a of the I / O device, the page number 2b in the DMA logical address, the page frame number 2c of the corresponding physical address, and this page frame number is a valid value. A TLB 1 having a plurality of data having a set of flags (V flags) 2d indicating that there is, a TLB hit determination circuit 4, an output address selector 5 to the system bus, a transfer mode selector 6, and a DMA map pointer 7. , I
/ O bus control unit 14, DMA sequencer 15, I / O
DM that stores the address and data output by the O device
A buffer 3 (for address) and 10 (for data)
And a clear circuit 13 for invalidating all V flags in the TLB 1.

In addition, as shown in FIG.
A DMA map table area 9 is placed in 02, and the start address can be indicated by the value set in the DMA map pointer 7.

First, in the I / O bus controller 14, I
A DMA request from the / O device is accepted, and if there are a plurality of DMA requests, arbitration is performed. Each I / O device is distinguished by a channel number, and the I / O bus controller 14 selects one channel number and gives a DMA permission. The I / O device of the channel number given the DMA permission outputs addresses (and write data), which are stored in the DMA buffers 3 and 10.

When the I / O bus controller 14 confirms that the transfer up to this point is normally performed on the I / O bus, it activates the DMA for the DMA sequencer 15 and accepts the received I / O. Convert control signals on the bus to control signals on the system bus. At the same time, the address set in the DMA buffer 3 is converted into the physical address 8 for main memory space access.

Channel number 2 of I / O device in TLB1
a and the page number 2b, the channel number 17 to which the DMA permission is given, and the page number 3a in the address output by the I / O device are the same, and the V bit 2d of the TLB is 1 (valid). , TLB hit determination circuit 4
The TLB hit signal 18 output from the signal becomes 1.

As a result, in the output address selector 5 to the system bus, the TLB1 corresponding to the page number is
The address 8 is selected by combining the PFN (page frame number) 2c of the above and the offset value 3b in the address output by the I / O device.

In parallel with the address conversion, the activated DMA sequencer 15 takes the bus right of the system bus and outputs the address 8 converted into the physical address.

On the other hand, there is no channel number in TLB1 that matches the channel number 17 given the DMA permission,
Even if the channel number 2a matches, the page number 2b and I
If the page number 3a in the address output by the / O device does not match or the V bit 2d of TLB1 is 0 (invalid), the TLB hit signal 18 output from the TLB hit determination circuit 4 becomes 0.

In this case, the DMA in the main storage device 102
The map table 9 is accessed, and the PFN corresponding to page number 2b is newly set in TLB1. Therefore, in the output address selector 5 to the system bus, the value D in the DMA map pointer register 7 and the page number 3a in the address output by the I / O device are combined.
The address 11 for MA map access is selected. Further, the transfer mode selector 6 also selects the mode 12 when reading the DMA map table.

At this time as well, since the DMA request is issued to the system bus as in the case of the TLB hit, when the bus right is obtained, the address 1 for the DMA map access is obtained.
1 is output. Further, the I / O bus control unit 14 uses the DMA
The I / O device in the middle is kept in the wait state without sending a signal indicating the end of transfer. This is because when an error occurs in the system bus during DMA map access, a bus error is reported to the I / O device and the process ends.

DMA map access is completed normally, and TL
When a valid value is set in B1, the I / O bus controller 1
4 again activates the DMA sequencer 15.
At the same time, since the TLB hit signal 18 also becomes 1, the output address selector and the transfer mode selector are switched,
D originally requested by the I / O device for the system bus
Automatically issue MA requests.

Next, the processing for updating the contents of the DMA map table 9 will be described.

When the DMA map table 9 in the main memory is updated and the mapping between the logical address and the physical address is changed, all the contents of TLB1 in the bus conversion adapter 105 must be invalidated. Where the CPU
When the clear circuit 13 is operated by the access 16 from 1 to invalidate all the V flags 2d, the subsequent DMA
The address conversion is performed by accessing the DMA map table 9 on the main memory. If the DMA is performed once, the PFN of the physical address corresponding to the channel number is set in TLB1, so that the page number of the logical address output next by the I / O device is updated for the channel number. DM on main memory until
It is not necessary to access the A map table.

When updating the DMA map table 9, if a new DMA map table 9B is created in another area on the main memory as shown in FIG. 5 before the TLB1 is invalidated, the DMA map pointer Only by rewriting the value of register 7 from value A to value B, DMA map table 9A
To 9B can be updated.

Next, a case where it takes time to perform the DMA transfer on the I / O bus will be described.

The bus conversion adapter 105 accepts the DMA in the I / O bus control unit 14, confirms that there is no error in the transfer from the I / O device, and then activates the DMA sequencer 15 to start the system. Issue a DMA request to the bus. Therefore, if the transfer on the I / O bus takes a long time, such as burst write, after confirming that the transfer on the I / O bus can be completed without error even after the address conversion is completed, To make a DMA request.

However, at the time of TLB miss, I / O
The bus control unit 14 performs DMA before the end of transfer on the I / O bus.
The sequencer 15 is activated to issue a DMA request for DMA map access so that the DMA request can be immediately issued on the system bus when the transfer on the I / O bus is completed successfully. After TLB1 is set to a valid value, I
The data for DMA access from the I / O device is buffer 10
If all are set, the DMA request is issued again to the system bus.

The above is an example in which the DMA map table is placed in the main storage device, but the same address conversion means can be used even when the DMA map table is placed in a separately prepared memory on the system bus. In this case, DM
The value set in the A map pointer 7 is only the address for accessing the memory, not the main memory. Explaining in FIG. 5, the substance of the DMA map table area in the main memory space is not in the main memory device but in another memory, and the concept is the same.

Further, this address conversion means can be applied to the address conversion from the system bus to the I / O bus described above.

If the system bus 104 has a split bus specification in which address transfer and read data reception are separated during read access transfer, the device which initiated read access releases the bus right after the address is output and is accessed. When the read data output is ready on the device side, the accessed device acquires the bus right and continues the read access transfer.

If the system bus 104 has such a split bus specification, the bus conversion adapters 105, 10
After receiving the address, 6 can make a DMA access to the address conversion table (other than the DMA map table) prepared in the main memory 102 to obtain the address for accessing the I / O device. it can.

The address conversion processing at this time can be realized by providing the same address conversion means as shown in FIG. 4 corresponding to the bus conversion control from the system bus to the I / O bus. Further, an error at the time of DMA access to the address conversion table is performed by the error reporting means of the system bus.

Since the bus conversion adapter for connecting the two buses having different specifications is provided with the address conversion means as described above, the address conversion means is not required for the transfer on the system bus, so that the high speed of the system bus can be achieved. The performance can be improved.

[0053]

As described above, according to the present invention,
Since the address conversion means in the bus conversion adapter has a method of automatically activating the DMA read when the TLB miss hits, the address conversion (DMA map) table is placed in the main memory even in the computer system having the bus hierarchical structure. be able to.

Further, an error on the system bus at the time of accessing the DMA map is transmitted to the D / I bus of the I / O bus by the bus conversion adapter.
By providing means for reporting to the I / O device which is the MA master, there is no problem in operation even if the DMA is started by the system bus for the DMA map access.

As a result, the address conversion (DM
By arranging the A map table, the address conversion (DMA map) table can be configured without being limited by the hardware amount, and therefore the switching of the address conversion (DMA map) table can be speeded up.

Also in a computer system having a bus hierarchical structure, it is possible to eliminate the storage element for the address translation (DMA map) table, which is a problem in hardware implementation.

Further, by providing the address conversion means in the bus conversion adapter, the address conversion means can be eliminated from the bus control device of the system bus, so that the high speed performance of the system bus can be further improved.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration example of a computer system using a bus conversion adapter that is an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration example of a conventional computer system.

FIG. 3 is a diagram showing a relationship between address spaces of a system bus and an I / O bus in FIG.

FIG. 4 is a diagram showing an address conversion system of a bus conversion adapter which is an embodiment of the present invention.

FIG. 5 is a diagram showing a configuration example of a DMA map table in a main storage device.

[Explanation of symbols]

1 ... Address translation lookaside buffer (TLB), 2a ... I /
Channel number of O device, 2b ... Page number part of logical address, 2c ... PFN (page frame number) of physical address corresponding to page number part of logical address, 2d ...
Valid information (V flag) of contents of TLB, 3a ... I / O page number part of logical address output from I / O device, 3b ... I / O
Offset value in address output by O device, 4 ... TL
B hit determination circuit, 5 ... Output address selector to system bus, 6 ... Transfer mode selector, 7 ... DMA map pointer, 8 ... DMA physical address combining 2c and 3b, 9 ... DMA map table, 10 ... DMA buffer ( (For data), 11 ... Address for DMA map access, 12 ... Transfer mode output to system bus during DMA map access, 13 ... V flag clear circuit, 14
... I / O bus controller, 15 ... DMA sequencer, 104
System bus connected to a plurality of I / O buses by a bus conversion adapter, 105, 106 ... Bus conversion adapter according to one embodiment of the present invention, 107, 108 ... I / O bus having different specifications from the system bus .

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Masatsugu Shinozaki 810 Shimoimaizumi, Ebina City, Kanagawa, Ltd. Inside the office system design and development center, Hitachi, Ltd. (72) Koichi Okazawa, 292 Yoshida-cho, Totsuka-ku, Yokohama Hitachi, Ltd. Microelectronics Device Development Laboratory

Claims (10)

[Claims] 1. A memory for storing programs and data of a main CPU, which is connected to two buses having different specifications, from an I / O device on one bus to another bus (hereinafter referred to as a main storage device). DMA (Direct M
In a computer system having a bus hierarchical structure in which a plurality of lower-order buses are connected by connecting a plurality of bus conversion adapters having means for enabling emory access) to a higher-order bus, the address space of the upper-order bus and the lower-order bus A bus conversion adapter that performs mutual address conversion between the above address spaces. 2. A memory for storing programs and data of a main CPU, which is connected from two I / O devices on one bus to two buses having different specifications (hereinafter referred to as a main memory device). DMA (Direct M
In a computer system having a bus hierarchical structure in which a plurality of lower-order buses are connected by connecting multiple bus conversion adapters having a means for enabling emory access) to the upper-order bus, Address conversion to the address space of the bus conversion adapter is performed using the conversion table in the bus conversion adapter, and the address conversion from the address space of the lower bus to the address space of the upper bus is performed by the upper bus connected to the bus conversion adapter. A bus conversion adapter characterized by performing access by accessing a DMA map table in a memory accessed through the lower bus. 3. A memory for connecting a program and data of a main CPU, which is connected from two I / O devices on one bus to each other, connected to two buses having different specifications (hereinafter referred to as a main memory device). DMA (Direct M
In a computer system having a bus hierarchical structure in which a plurality of lower-order buses are connected by connecting multiple bus conversion adapters having a means for enabling emory access) to the upper-order bus, Address translation to the address space of the lower bus and address translation from the address space of the lower bus to the address space of the upper bus, both addresses in the memory accessed through the upper bus or the lower bus connected to the bus conversion adapter. Bus conversion adapter characterized by accessing a conversion table. 4. A computer system having a bus translation adapter according to claim 1, 2 or 3, wherein an I / I for address translation in the bus translation adapter is provided.
An address conversion table (D that associates the address output by the O device with the address for accessing the main storage device)
(MA map table) and an address conversion table that associates an address output from a device connected to the upper bus with an address for accessing an I / O device connected to the lower bus in a main storage device. Address conversion method. 5. An address translation system according to claim 4,
A bus conversion adapter internally having an address conversion index buffer (TLB) having a part of the data stored in the DMA map table and valid information indicating the validity of the contents of the buffer is provided, and a logical address is used for designating the head address of the DMA. In a computer system for connecting an I / O device using the D., the access destination address is set to the D address for the means that enables DMA to the main storage device in the bus conversion adapter.
The bus conversion adapter is provided with map address composition means for setting a table position corresponding to an address output by the I / O device in the MA map table, and the bus conversion adapter receives the DMA request from the I / O device and stores it in the main memory device. On the other hand, when the content of the address conversion TLB is invalid while the DMA request is issued, the content of the DMA request is changed by using the map address composition means and the means for enabling the DMA. A bus conversion adapter comprising means for switching from a request from an I / O device to a DMA map table access request, and the means. 6. The address translation system according to claim 4,
A bus conversion adapter internally having an address conversion index buffer (TLB) having a part of the data stored in the DMA map table and valid information indicating the validity of the contents of the buffer is provided, and a logical address is used for designating the head address of the DMA. In a computer system for connecting an I / O device using the D., the access destination address is set to the D address for the means that enables DMA to the main storage device in the bus conversion adapter.
A map address synthesizing unit for setting a table position corresponding to an address output by the I / O device in the MA map table is provided, and the bus conversion adapter receives the DMA request from the I / O device and converts the address. When the content of the TLB is invalid, a DMA map table access request is issued by using the map address composition means and the means enabling the DMA before the conditions for DMA transfer from the I / O device are satisfied. And a bus conversion adapter including the means. 7. An address translation system according to claim 4,
I / that uses a logical address to specify the start address of DMA
In a computer system to which an O device is connected, an access destination address is set to the D address for the means that enables DMA to the main storage device in the bus conversion adapter.
A map address synthesizing unit for setting a table position corresponding to an address output by the I / O device in the MA map table is provided, and when the DMA request from the I / O device is received, the map address synthesizing unit and the A DMA physical address corresponding to the DMA logical address output from the I / O device is read from the DMA map table in the main memory by using means for enabling the DMA, and the DMA physical address is used in the main memory device. The bus conversion adapter is characterized by performing the above access and executing the DMA of the I / O device. 8. A means for reporting an error to an I / O device which is a DMA master when an error occurs on a system bus during access to a DMA map table according to claim 5, 6 or 7. A bus conversion adapter characterized in that 9. A computer system having a bus hierarchy structure, comprising the bus conversion adapter according to claim 1, wherein an I / I for address conversion in the bus conversion adapter is provided.
An address conversion table (D that associates the address output by the O device with the address for accessing the main storage device)
An MA map table) and an address conversion table that associates an address output by a device connected to the upper bus with an address for accessing an I / O device connected to the lower bus, in a memory other than the main storage device. Address conversion method characterized by. 10. An address conversion system according to claim 9, comprising a part of data stored in said DMA map table,
A computer system having a bus translation adapter internally having an address translation lookaside buffer (TLB) having valid information indicating the validity of the contents of the buffer, and connecting an I / O device using a logical address for designating a head address of DMA , The access destination address to the means for enabling DMA to the main storage device in the bus conversion adapter,
The bus conversion adapter is provided with a map address synthesizing unit for setting a table position corresponding to an address output from the I / O device in the MA map table, and the bus conversion adapter receives a DMA request from the I / O device and sends it to the upper bus. When the content of the address conversion TLB is invalid while the DMA request is issued by using the map address composition means, the content of the DMA request from the I / O device to the main memory device is DMA mapped. A bus conversion adapter comprising means for switching to an access request to a memory in which a table is placed.