JPH02116945A - Connecting device for different kinds of buses - Google Patents

Abstract

PURPOSE:To execute the parallel operation by sending out an address of a memory area allocated by an input/output instruction from a CPU as an input/ output instruction to an input/output device. CONSTITUTION:When an input/output instruction is received from a CPU through a system bus 3, a system interface control part SBI part 21 transfers it to a memory access control part MAC part 22, and simultaneously, transfers it to an address conversion control part 23, and executes an allocation control of a memory area. Thereafter, the input/output instruction which is brought to address conversion is transferred to a program bus interface control PBI part 24, sent out to the corresponding input/output device, and also, an interruption signal is received, and informed to the address conversion control part 23. Also, a direct memory access interface part DBI part 25 is provided and a direct memory access from the input/output device is received, the data concerned is read out of a data buffer 26 and sent out to the corresponding input/ output device, and also, the data from the input/output device is written in the buffer 26.

Description

Detailed Description of the Invention (Industrial Field of Application) The present invention provides interconnection between one bus to which a central processing unit and a storage device are connected and the other bus to which a plurality of input/output devices are connected. The present invention relates to a device for connecting different types of buses.

(Prior Art) Computer systems have undergone various improvements such as increasing the storage capacity of main storage devices and adding new functions. 2. Description of the Related Art Increasingly, system devices (hereinafter referred to as input/output devices) are provided with memory space support such as a main storage device, address conversion functions, and the like.

When a new computer system is developed in this way, it is required to connect and use the input/output devices that have been used up until now.

FIG. 7 is a diagram showing a conventional connection configuration between a new computer system and a previous computer system. In FIG. 7, l indicates a new computer system, and this computer system 1 includes a central processing unit (hereinafter referred to as CPU) 2, and a system bus 3 connected to this CPU 2.
It consists of a plurality of input/output devices 41 to 4o and a main storage device 5, which are connected via.

On the other hand, the previous computer system 6 includes a CPU 7 and a plurality of input/output devices 9. connected to the CPU 7 via an input/output bus 8. 9m and a main storage device 10.

Further, the CPU 2 and the CPU 7 are connected to each other by an adapter device 11.

In the conventional connection configuration described above, input/output commands output from the CPU of the new computer system 1 are sent to the adapter device 1.
1 to the CPU 7 of the previous computer system 6, and the CPU 7 outputs the data to the input/output devices 91-9. It uses an indirect memory access method that controls data input and output processing.

However, with this indirect memory access method, input/output commands from CPU 1 cannot be directly used as input/output commands for CPU 7, and the new computer system 1 requires special software that requests input/output processing from CPU 7. , and other special software is required on the previous computer system 6 side to receive and process this. Also, both systems 1.
6 is merely connected via the adapter device 11, another drawback arises in that the scale of the entire system increases.

Therefore, we installed adapter device 1 for the new computer system.
Direct connection of previous input/output devices via 1 is provided. FIG. 8 shows a direct connection configuration, in which the adapter device 11 is connected to the previous input/output devices 91-9. is connected.

In this way, when connecting the previous input/output device directly, the adapter device 11 is used to mutually convert the human output control method in the new computer system and the input/output control method in the previous computer system. It is required to add a system conversion function.

In particular, in order to reduce the load on the CPU 2 in the new computer system 1, an address calculation function (channel dynamic address conversion function) is added to the input/output devices 41 to 4n so that the input/output devices 41 to 4n can directly calculate memory addresses. 4o, so that data can be accessed directly from the main storage device 5, but the input/output devices 91 to 9.4 of the previous computer system. often do not have this functionality. Therefore, as mentioned above, the adapter device 1
1, input/output devices 91-9. When connecting directly, a channel dynamic address conversion mechanism is added to the adapter device 11, and each input/output device 9, to 9. A method of directly accessing memory (hereinafter referred to as a direct memory access method) is being practiced.

By the way, FIG. 9 is a block diagram for explaining the direct memory access method, in which the CPU 2 and the input/output device 41 etc. are connected by the program bus 12, and the main storage device 5 and the input/output device 43 etc. are connected to the direct memory access method. They are connected via a bus (hereinafter referred to as DMA bus) 13.

FIG. 10(A) is a configuration diagram of the DMA bus 13, including a bus use request line 13a, a bus use permission line 13b, an address sending line 13c, a read/write line 13d, and a memory response line 1.
It includes a 3e1 memory access data line 13f and a memory access address line 13g. FIG. 10(B) is a timing chart during memory access.

FIG. 11 shows the contents of the input/output commands output by the CPU 2, where 14 is the input/output command (hereinafter referred to as CF), 15 is the data address (hereinafter referred to as DA), and 16 is the data byte count value (hereinafter referred to as CF). BC).

Now, when the CPU 2 sends the input/output command shown in FIG. 11 to the input/output device 41 via the program bus 12, the input/output device 4. accesses data by the number of words (bytes) specified by BCl2 from the address specified by DA15 of the main memory device 5.

That is, as shown in FIG. 10(B), the input/output device 4. sends a bus use request to the CPU 2 via the bus use request line 13a.
When the CPU 2 determines that the bus can be used, it grants permission to the input/output device 4 to use the bus via the bus permission line 13b.

This acquires the use of the DMA bus 13.

Next, when the address strobe signal is output to the address sending line 13c, the memory access address line 13g
The DA15 is output to the main storage device 5 via the DA15. Further, when a read/write strobe signal is output to the read/write line 13d and a memory response signal is sent to the memory response line 13e, the input/output device 4I reads data corresponding to the address from the main memory 5 or Write data.

(Problem to be Solved by the Invention) As described above, when performing direct memory access with an input/output device having a channel dynamic address conversion function, as described above, it is necessary to simply transfer data to the DA15. Often, it does not matter which input/output device is being accessed. However, by adding this function to the adapter device 11, the adapter device 11 replaces a plurality of previous input/output devices 9. ~9. If the adapter device 11 simply performs direct memory access on behalf of the user, the adapter device 11 cannot recognize which input/output device is making the access request, and therefore the input/output devices cannot be operated in parallel.

The present invention has been made to solve these problems, and has a channel dynamic address conversion function as well as a function to reliably recognize which input/output device an access request is from. The purpose is to provide a connection device.

(Means for Solving the Problems) The heterogeneous bus connection device of the present invention is divided into a plurality of memory areas, and data read from a storage device and data to be written to the storage device are temporarily stored in one of the memory areas. Allocate one of the memory areas to the corresponding input/output device by an input/output instruction from the storage unit and the central processing unit, and send the address of the allocated memory area and its identification data to the input/output device. and an address translation control unit that sends out an address as an address translation control unit.

(Operation) When the central processing unit receives an input/output command containing a data address of a storage device from the device, the address conversion control unit allocates one of the memory areas of the storage unit to the corresponding input/output device, and converts the address of this memory area. and the identification data of the area are sent to the input/output device as an input/output command.

The input/output device starts accessing the storage device based on the input/output command sent after address translation. In this case, one of the memory areas is specified by the identification data.

Therefore, a plurality of input devices can be operated in parallel in correspondence with respective memory areas.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of a device for connecting different types of buses according to the present invention. In FIG. 1, reference numeral 20 denotes the device of the present invention, which is equipped with a system bus interface control section (hereinafter referred to as SBI section) 21. This SBI unit 21 receives input/output commands from the CPU 2 (see FIG. 5) via the system bus 3. FIG. 6 is a diagram explaining input/output commands from the CPU 2, and the commands are input/output commands (CF).
30, a data byte count value (BC) 31 and a data address (DA) 32.

When the SBI unit 21 receives an input/output command, it sends the CF30 and D
A32 and BC31 are connected to a memory access control unit (hereinafter referred to as M
(referred to as AC) 22, and at the same time CF30 and BC3.
1 is transferred to the address conversion control unit 23. As will be described later, the address conversion control unit 23 performs control to allocate a memory area to any of the input/output devices 91 to 9°, and then
The input/output command whose address has been converted is transferred to the program bus interface control unit (hereinafter referred to as FBI) 24.

The FB I 24 sends this input/output command to the corresponding input/output device via the program bus 33, receives an interrupt signal from the input/output device, and executes the address conversion control unit 23.
Notify interrupt to.

Further, the heterogeneous bus connection device 20 of the present invention includes a direct memory access interface control unit (hereinafter referred to as DBI) 2.
5. This DBI unit 25 receives direct memory access from an input/output device, reads out the corresponding data from the data buffer 26 in the case of reading, and sends it to the corresponding input/output device, and in the case of writing, receives the data from the input/output device. This D
When the input/output processing of the input/output device is completed and a channel status signal (CSW) is supplied from the input/output device, the BI section 25 sends this signal to the address conversion control section 23 to ensure that the input/output processing is performed normally. Have the students decide whether or not it was done.

Now, FIG. 2 is a configuration diagram of the data buffer 26. That is, this data buffer 26 includes a data memory 27, and this data memory 27 has four blocks B. ~B3
It is divided into two (memory areas) and is formed from a two-port type memory that can input and output in both directions. Multiplexers 28A and 28B as distribution switches are connected to the ports of each block 80-B.

On the other hand, the address translation control section 23 includes a data block management table shown in FIG. In this data block management table, table block number 0
3 are each block B of the data memory 27. A block bank (BNK) of data is used as identification data for identifying each block 80 to B as each memory area, and has a 2-bit configuration.

In other words, block B. ro, OJ, block B1
ro and IJ correspond to block B2, rl and OJ correspond to block B2, and rl and IJ correspond to block B3, respectively.

In addition, data address DA (d) is for each block B0~
B, indicates the address where the data is stored, for example, 10
It has a bit configuration. Furthermore, the memory area r ooo
ooh~0FFFFhJ etc. are each block B. - All addresses from the beginning to the end of B3 are shown. Also,
Flag "1" indicates that the memory area (block 80, etc.) is in use, that is, the memory area is allocated to any input/output device, and flag rOJ indicates that the input/output processing has finished and the memory area is being used. indicates that it has been released.

As shown in FIGS. 1 and 5, the connection device 20 between different types of buses according to the present invention having the above-mentioned configuration has an upper 2B
It is connected to the I section 2 side side 1 side stem bus 3, and the PBI section 24
and is connected to the DBI section 2 side 5 side output bus 8.

A plurality of previous input/output devices 91 to 9 are connected to this input/output bus 8.

Note that the input/output bus 8 is a program bus 33 shown in FIG.
and a DMA bus 34.

Next, the input/output processing operation of the heterogeneous bus connection device 20 of the present invention will be explained.

CPU2 is CF30. When an input/output command (see FIG. 6) including BO31 and DA32 is output, the SBI unit 21 receives this input/output command via the system bus 3, and outputs the input/output command to the CF30.
．． At the same time as transferring BO31 and DA32 to the address conversion control unit 23, DA32 and BO21 are sent to the MAC unit 2.

Next, the address translation control unit 23 searches the flag, selects an unused block of the flag rOJ, for example, block B0, and selects this block B. data address DA (d)
Add BNK ro and OJ corresponding to the address DA (d) and BNKro and OJ to CF30 and BO.
21 and is transferred to the PBI unit 24 as an input/output command with the address translated. Figure 4 shows the input/output instruction with this address converted, with BNKro and OJ in the first two bits.
Address DA (d) with BO21 and C
It consists of F30. In addition, this address conversion control unit 23 transfers BNK ro and OJ to the 2nd part of the MAC part, and also transfers DA32 and B which have been transferred to the 2nd part of the PBI part.
Keep O21 intact.

Next, the PBI unit 24 converts the transferred input/output commands into C
Any input/output device specified by PU2, for example,
Send to input/output device 9m. The input/output device 9 that received this input/output command. is block B0 specified by DA(d)
Access is started from the address for the number of words specified in BO21. That is, input/output device 9. is DA (d) to block B. Add BNK ro, OJ indicating CF30. The BO31 is output to the DBI section 25.

Through this access, the DBI unit 25 reads the corresponding data from the address DA (d) of the block B0 indicated by BNK ro and OJ from the data memory 27 of the data buffer 26 if the CF 30 is reading, and sends this data to the input/output device 91. Output data. Also, if CF30 is written, the above block B is written. address DA (d)
The data from the input/output device 91 is written to. That is, B.N.
When Kro and OJ are input to the data buffer 26, the second
As shown, multiplexer 28B is connected to block B0
, the DBI section 25 only needs to read or write data.

Further, the MAC unit 22 also receives the DA32. BNK ro and OJ transferred from the BO 31 and the address conversion control unit 23 transfer the data read from the main storage device 5 to the block B in the case of reading.
0 address DA(d), and if it is a write, this block B. The data is read from the address DA (d) and written into the main memory device 5. In this case also BN
Multiplexer 28A is connected to block B at K ro and OJ.
0 is automatically selected.

When other input/output instructions are output from the CPU 2, the address conversion control unit 23 similarly outputs BNKro, IJ, rl.
, OJ or rl, IJ is added to DA(d) and other blocks B +, B 2. B s is assigned to another input/output device and the address is converted to BN.
An input/output command containing K is sent to the corresponding input/output device. Therefore, block B in this embodiment. Since the number -B3, that is, four memory areas can be allocated to the input/output devices, the four input/output devices can be operated in parallel.

Of course, the identification data may be any data that can identify each memory area.

(Effects of the Invention) As explained above, according to the present invention, a storage section is divided into a plurality of memory areas, and one of the memory areas is allocated to a corresponding input/output device according to an input/output command from the CPU, and Since the address of the memory area and its identification data are sent as an input/output command to the corresponding input/output device, even if the input/output device does not have the channel dynamic conversion function, The apparatus can be operated in parallel in a computer system comprising the apparatus.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a connection device between different types of buses according to the present invention, FIG. 2 is a configuration diagram of a data buffer according to the present invention, and FIG.
4 is a diagram showing a data block management table of the present invention, FIG. 4 is a diagram showing address-converted input/output instructions, and FIG. 5 is a diagram showing a connection configuration of a direct memory access method using the device of FIG. 1. 6 is a diagram showing the input/output instructions of the CPU shown in FIG. 5, FIG. 7 is a diagram showing the connection configuration of the indirect memory access method, and FIG. 8 is a diagram showing the connection configuration of the conventional direct memory access method. FIG. 9 is a diagram explaining the direct memory access method, FIGS. 10 (A) and (B) are diagrams showing the configuration of the DMA bus and a timing chart of the direct memory access method shown in FIG. 9, and FIG. 9 is a diagram showing input/output instructions of the CPU shown in FIG. 2...CPU, 9I~91...Previous input device, 2
1... SBI section, 22... MAC section, 23... Address conversion control section, 24... PBI section, 25... D
BI section, 26...Data buffer, 28A, 28B.
...Multiplexer, B, -B, ... block. Patent applicant Oki Electric Industry Co., Ltd.

Claims (1)

[Claims] Connecting a bus to which a central processing unit and a storage device are connected to another bus to which a plurality of input/output devices are connected, and receiving an input/output command including a data address of the storage device. A connection device between different types of buses that allows the corresponding input/output device to directly access the storage device, the device being partitioned into a plurality of memory areas, and containing data read from the storage device and data to be written to the storage device. a storage unit in which data is temporarily stored in any of the memory areas; and a storage unit that allocates any of the memory areas to the corresponding input/output device upon input of the input/output command, and an address of the allocated memory area and the memory. A device for connecting different types of buses, comprising: an address conversion control section that sends area identification data to the corresponding input/output device as an input/output command.