JPS5848160A - Multiprocessor system - Google Patents

Abstract

PURPOSE:To constitute a multiprocessor system having a high-performance interprocessor communication function, by provicding a communicating means for transmitting and receiving communication data through an interface to and from the central processing unit of another processor. CONSTITUTION:When decoding a communication instruction, a CPU14 sends communication data to an interface control part (ICL)13 through a memory controller (MCU)12 to support communication transmission to a processor 20. The ICL13 transfers data contents to the ICL23 through a path 150. Then, the ICL23 sends data, sent from the ICL13, to a CPU24, which once receiving the communication data, causes an interruption to software to bring the communication data under software control. The communication from the CPU24 to the CPU14 is carried out similarly.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multiprocessor system in a data processing apparatus.

Conventionally, as a means to improve the performance and reliability of a data escape system, a multiprocessor system configured with a plurality of processors has been realized.

The following two types of configurations of this multiprocessor system are known.

One is a tightly coupled multiprocessor system in which multiple processors access a common main memory (hereinafter referred to as main memory) and the system runs on one operating system. It is an independent, loosely coupled multiprocessor system.

There is also a system configuration in which each processor in a loosely coupled multiprocessor system is configured as a tightly coupled multiprocessor system.

Loosely-coupled multiprocessor systems have advantages over tightly-coupled multiprocessor systems, such as being able to construct larger systems, making system expansion easier, improving system reliability, and being able to combine different types of processors. A loosely coupled multiprocessor system requires a communication function between processors, but the conventional communication between processors only involves communication between the input and output channels of each processor. Caram to Canne
l) (hereinafter referred to as C'rC) via the adapter m1ll!
A configuration has been adopted to do so.

However, in the configuration via a CTC adapter, the throughput of data transfer of the input/output interface of the input/output channel is small, and the performance improvement for communication from one processor to another processor is sufficient to improve the performance of the source processor. There is a drawback that this cannot be achieved due to the overhead caused by the creation of input/output instructions by the operating system and the overhead caused by the processing of the receiving software.

SUMMARY OF THE INVENTION An object of the present invention is to provide an i-multiprocessor system that solves the above-mentioned drawbacks and is equipped with a high-performance inter-processor communication function.

The system of the present invention includes a main memory, a memory control device, and a central storage system that accesses the main memory via the memory control device. Multiple processors with and interface control unit! Consisting of 4 sets each! In a multi-processor system in which the processors run on independent operating systems and have a data transfer interface between the interface control units of each processor, at least one program processor of the plurality of processors operates on one of the main memories. means for allocating a section as a shared memory for access from the central processing unit and the interface control section; means for the processor to control data transfer between the main memory and the shared memory; means for controlling data transfer to and from a shared memory between processors via the interface; and communication means for communicating between the central processing unit and the central processing units of the other processors via the interface. configured.

Next, the present invention will be explained in detail with reference to Kaiten.

Referring to FIG. 1, one embodiment of the present invention includes a processor 1
0 and 201 Peripheral control unit (hereinafter referred to as PCU) 80, 82
,84. and 85. i and peripheral equipment (hereinafter referred to as PER) 8
1, 83 and 86. The processor 10 has a main memory (hereinafter referred to as MM) 11. Memory control unit (hereinafter referred to as MCU) 12. Interface control unit (hereinafter referred to as I)
CL) 13, a central processing unit (hereinafter referred to as CPU) 14, and an input/output channel control unit (hereinafter referred to as 10C). fiIOcl 5 is a channel control device (CMC)
) 15G and channel equipment CHI 51-158. The processor 20 costs M¥21.
MCU22゜ADP2B with register 27, CPU
24. It consists of a shared memory 26 allocated to a part of the 10C 25 and MM21.

When accessing a part of the main memory 11 as a separate memory space for the shared memory 26, the register 27 in the MCU 22 is used. Next, this access control will be explained with reference to FIG.

Referring to FIG. 2, the MM 21 is divided into a shared memory section 26 and a main memo section 29 used for the original software processing within the processor 20, and the shared memory section 26 is allocated to a lower address area. . The register 27 is set with the start address of the memory section 29)
, CPU24. connected to MC022. The following address modification is performed by the access commands for MM21 from I0C25 and ICL23, and MM21 is accessed.

In the case of access to the shared memory 26 from the request source, the content a of the address 28 from the request source is
It is used as the address of M21 to access MM21. In other words, the shared memory 26 is accessed using addresses starting from address 0 of the content KjJIMM 21 of the address 252.

At this time 1. An exception occurs when address a exceeds the maximum address m of the shared memory 26, and accesses of jD and MM2i are inhibited.

When a command accesses the main memory section 29, the contents of the register 27 are added to the address a, and the MM 21 is accessed based on the addition result 253.

Therefore, the main memory address seen from the software is the same regardless of the presence or absence of the shared memory c26.

Further, in the case of this embodiment, the CPU 24 command allows access to both the shared memory 26 and the main memory 21;
Only access commands to the shared memory 26 are possible from the ADP 23, and if this condition is violated, access to the gMM 21 is inhibited and an error δ status is reported to the request source.

l0C25 is CHC25o and multiple 0CH251°...
, 258, and PHB is connected via each CHK/riPC.
83 is a disk device), and two aisles on this disk device are commonly accessed by the processors 10 and 20.

In such a system where files are shared among nine different processors, processors 10 and 20 are exclusive with respect to shared file access.

Rounding that requires control - communication functionality between both processors is required. In addition, data transfer and communication between both processors is required to centralize console input/output, jeep output, and centralize power data in order to centrally operate the system.

Data transfer and communication operations between both processors via the shared memory 26 in this embodiment 91 will be described in detail.

The processor 10 executes a data transfer instruction between the MMII of its own processor and the shared memory 26 in the MM21. By executing this instruction, the software of each processor transfers data and communicates with each other via the shared memory.

This command has the format shown in Figure 3.

The instruction 300 consists of 3 words WO~2, 0P3
00A is the instruction; - code, PR030'OB is the processor number where the shared memory is located, MADR8300D is the address on the main memory, CMAD88300F)
is the shared memory 26] address and 'rALLY
sOoc indicates the amount of transferred data.

When transferring data from the main memory 11 to the shared memory 36, the data at the main memory address indicated by MADR8300D is transferred to the shared memory address indicated by CMADR8300E by the number of bytes specified by TALLY300C.

When transferring from the shared memory 26 to the main memory 11,
The shared memory address data indicated by reverse KCMADR830011 is transferred to the main memory address indicated by MADR8300D by the number of bytes specified by TALLY300C.

Next, the operation of this instruction in processor 10 will be explained in detail.

Here, the processor number of each processor is assigned in advance to the expansion jumper designation for each processor, and the processor number of the processor 20 is set in PR0300B of the instruction shown in FIG.

The CPU 4 reads the instruction from the MMII, and if the instruction=-do is a transfer instruction between the main memory and the shared memory area,
Set the real address of MMIl and shared address 26 to j112.
Instructions MADR8300D and 0MA11830 shown in the figure
I made 0B and 6 g, and together with TALLY300C, it was the first
The data is transferred to the ICLI 3 shown in the figure via the MCU 14, and data transfer is requested.

When transferring from MMI 1 to the shared memory 26, the address of the shared memory 26 and the contents of TALLY30QC are
The data is sent from the LI 3 via the path 150, instructs to write to the shared memory 26, and the data is read from the MMII and sequentially transferred to the ICL 23.
L23- sequentially writes data sent from ICLI3 into shared memory 2d using the shared memory address sent from ICLI3 as a starting address.

Also, ICLI3 and 23 are TALLY300 for each transfer.
The value of C is subtracted in units of transferred data amount, and when the value becomes zero, the transfer is terminated.

In the case of a transfer instruction from the shared memory 26 to the MMII, the IC
LI3 is the address of the shared memory 26 and TAL as above.
After sending the contents of LY300C to ICL23, ICL2
Wait for data to be sent from 3. IeL23'
□ reads data from the shared memory 26 and sequentially passes pass 1.
50 to ICLI3. ICLI 3 sequentially writes this data to the MMII address specified by MAD 8300D. This transfer operation is executed until the value of TALLY becomes zero.@MMl When the 9 data transfer operation from 1 to the shared memory 26 or from the shared memory 26 to MM-11 is completed, ICLI3 transfers the data to CPU1.
Upon this notification, the CPU 14 completes the command and proceeds to the next command.

May/memory 29 in MM21 in processor 20
Data transfer between the CPU 24 and the shared memory 26 is executed by specifying the processor number of the processor 20 using the instruction PR0300B.

In the case of a transfer command from the main memory 29 to the shared memory 26, the CPU 24 reads the contents of the main memory access starting from the address indicated by MADR8300D, and sends the shared memory access command to the shared memory 26 at the address indicated by CMADB8300B. I will write next time.

The transfer operation continues until the number of bytes indicated by TALLY300e has been transferred.

In the case of a transfer command from the shared memory 26 to the main memory 29, data is read from the address of the shared memory 26 by the shared memory access command indicated by CMADR8aooB, and data is read from the address of the shared memory 26 by the main memory access command.
Data is written to the address of main memory 29 indicated by R8300D.

When the data transfer of the number of bytes indicated by 'I'ALLY300C is completed, the CPU 24 terminates the instruction and executes the next instruction.

Also, as a means of communication between the processors, the CPU 14 and the CPU
There is a communication command for directly communicating data between U24 and U24, and this command has the format shown in FIG.

Referring to FIG. 4, the instruction 400 consists of two words, and PR0400B indicates the processor number of the communication destination.
Q400C is the processor number of the communication request source, CM
D400D indicates a communication command, and CDAT person 400B indicates communication data.

The communication operation from the CPUI 4 to the CPU 24 is as follows. When CPUI 4 decodes Jin's communication command, %C
U12t-to-ICLI3-t''40 in Figure 4
- Send communication data indicated by OB~400PX Jt, P
Instructs the processor indicated by R0400B to escape communication. In the case of this real m+-, PR0400B indicates the processor number of processor 200.

ICLI 3 transfers the contents indicated by 400C to 400B to ICL 23 via path 150.

When this communication is received, an interrupt is generated to the software, and the overconfidence data is placed under software control (CP
Communication from U24 to CPU I4 is also executed in a similar manner.

As described above, data transfer and communication between both processors can be realized at high speed by the data transfer command and the communication command.

The first embodiment is an example of a loosely coupled multiprocessor system consisting of two processors), and even in systems with a large number of processors, the present invention allows effective communication between the processors.

Referring to FIG. 4, the second embodiment of the present invention includes four processors 80.4G, 50. and 60,
Each processor has MM31.41°51, Kiyo and 61. M
CU12.42,52. and 62. CPU34,44
,54. and 64° and 1.0C35,45,55
, and 65. , and an ICL 33°43.53 . between each processor. and 63, respectively.

Further, a shared memory 66 is allocated to the processor 500MM61.

As shown in the first embodiment, each processor transfers data between the main memory of its own processor and the shared memory of another processor or its own processor.

When communicating using the shared memory 6°6 within the processor 60, the processor 30 can communicate between one ICL 33 and another ICL
63 - via a bus 7031 - the processor 40 connects one ICL 43 to another ICL 63 - via a leap path 706
The processor 50 connects the open ICL 53 and other ICs via the
Pa between L63 (705t-via Pousey?6
0 transfers data between the shared memory 66 in its own processor MM61- and the main memory area via MCυ62.

In addition, if -fF is depleted, the processor 60 becomes inoperable due to a failure, etc.], and if the processor 60 is disconnected from the system and the system is configured with only the remaining processors 3G, 4G, and sO, the processor 50 By allocating a part of the MM 51 in the processor as a shared memory and using this shared memory, communication between each processor is executed.

Also, each MM in the other processors 30 and 40
It is possible to allocate part of 311 and 41 as shared memory.

Furthermore, the data transfer commands related to the MM and shared memory shown in this embodiment are shown for the case where the data transfer is completed as one command, but when data is transferred between the MM and the shared memory on another processor, - There is also a method of ending the instruction operation when the data transfer instruction from the CPU to the ICL is completed and starting the execution of the next instruction. In this case, the instruction execution time of the CPU is shortened), and the instruction execution time of data transfer is further improved.

In addition, the communication command is specified by the communication destination processor number t indicated by PR0400B).
Communication can be performed between any processors by identifying the processor number with L and making a communication request to the specified processor in the same manner as in the embodiment of the first magazine.

The present invention has the advantage that communication data can be transferred to other processors at high speed, and highly efficient processing with high performance and little communication overhead can be performed.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the first embodiment of the present invention, FIG. 2 is a diagram for explaining a part of the main memory that is accessed as the -St shared memory, and FIG. 3 is a diagram showing the main memory and the four shared memories. FIG. 4 is a diagram showing the format of a communication command, and FIG. 5 is a diagram showing an actual mt example of [2] of the present invention.゛ From Figure 1 to Figure 5, 10.2G, s6゜4
0.50.60...Processor, 11,21゜31.44,51.61・◆...Main memory, 1
2゜22.32, 42, 52.62... Memory control device, 13, 23, 33, 43. ! ! 3.63...
・Interface control unit, 14, 24, 34, 44° 54.64...Central processing unit, 15, 25.3
5゜45.55,615...Input/output channel control device, 26, 66・Song/shared memory, 151,15
8,251゜258... Song channel device, 27...
...Register, 28...Address, 29...
... Main memory, 250-253 ... Address information, 300.400 ... 6m1 instruction, 100
~103.1! So, 201~2G4゜250~25$
7,301-304,401-404゜501-504
,601~604.700~706...half 1 figure puoi-

Claims (1)

[Scope of Claims] A main memory, a memory control device, and a central processing unit that accesses the main memory via the memory control device, respectively;
and a plurality of processors having an interface control section, each of the processors running on an independent operating system, and having a data transfer interface between the interface control sections of each processor, At least one of the plurality of processors has a means for allocating a part of the main memory as a shared memory and accessing it from the central processing unit and the interface control unit; means for controlling data transfer between the main memory and the shared memory of another processor by fully controlling the interface; and means for controlling data transfer between the main memory and the shared memory of the other processor; A multiprocessor system comprising: communication means for transmitting and receiving communication data to and from a central hjl device via the interface.