JPS599324Y2 - multiprocessor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multiprocessor system comprising a plurality of processor units.

Conventionally, by arranging multiple processor units, transferring predetermined data between each unit, and executing unique arithmetic processing in each unit,
Multiprocessor units are used that are capable of processing highly sophisticated calculations at high speed.

However, since a plurality of interface sections are used to transfer data between processor units, the connection relationship between each unit becomes complicated.

The present invention was devised to solve these drawbacks, and its purpose is to provide a multiprocessor system in which data can be transferred between processor units overnight through simple connections. be.

Hereinafter, the present invention will be explained in detail based on the illustrated embodiments.

The figure is a block diagram showing one embodiment of the present invention.
A processor unit (hereinafter referred to as a mask processor) 1 and a second processor unit (hereinafter referred to as a slave processor) 2 are coupled by a single interface section 3.

In the figure, the mask processor 1 is, for example, a μPD 78.
0 (manufactured by NEC), 16-bit address bus output A.

-A15, 8-bit data bus input/output D.

-D7, interrupt signal INT, data read signal output RD, input/output request signal output IORQ, data write signal output WR, etc., and address bus output AO A
The device number of the slave processor 2 given by the lower 8-bit address signal in 15 is coded and output as a chip select signal CS on the condition that the input/output request signal IORQ is outputted in the coder 4.

The master processor 1 has signal input/outputs other than those mentioned above, but those not used in this embodiment can be found in the "μCOM-82 User's Manual" published by NEC Corporation (material number IBM-616). Since it is described in B) and is well known, the explanation here will be omitted.

Next, the slave processor 2 is configured by, for example, μPD8049 (manufactured by NEC Corporation) and has two input/output ports PI and P2 with an 8-bit structure, and data is transferred from the input/output port PI to the mask processor side. output the desired data.

Then, when a signal is input to the terminal TO, the transmission stops for the entire transmission.

In addition, the input/output port P2 outputs a strobe signal STB for storing the transfer data in the interface section 3, an acknowledge signal ACK indicating that transfer data from the master processor side has been received, and an interrupt signal INT for the mask processor 1. do.

Note that these signals STB, ACK, and INT are outputted via the input/output expansion unit 5.

When slave processor 2 receives interrupt signal INTs, it performs interrupt response processing to read data transferred and stored from mask processor 1 to interface section 3.

The interface unit 3 has a programmable operation mode and is a programmable peripheral interface (for example,
It is configured by NEC's μPD 8255) and has three programmable input/output ports (PA, PB, PC) as shown in Table 1 below, among which the input/output port (PA) is
is used as a transfer data input/output port in mode 2, that is, as a bidirectional input/output port, and a part of the board PC is in mode 2 status as a signal input/output port that controls overnight transfer. used in the state.

Table 2 shows the input/output signals of PA-PC in mode 2.

In addition, this interface section 3 receives an overnight write signal W.
Port 1-PA is selected by setting both signals A1 and AO to "0".

However, in this embodiment, address signals A1 and Ao of the mask processor 1 are input.

On the other hand, mode 2 is selected by setting an 8-bit control word from mask processor 1.

In this case, the transfer data from the mask processor 1 including the control word is written all at once by the write signal WR.
The transfer data from slave processor 2 and the status status of interface section 3 are all read out by data read signal RD.

Here, the signals OBF, ACK, IBF, in Table 2,
Of STB and INTR, signal INTR is not used.

Further, the signal IBF is a signal indicating that the transfer data from the slave processor 2 is stored in the input/output port PA and has not yet been read out from the mask processor 1. When data reading is completed, it returns to the ゛゜0゛ level.

Then, this signal IBF at the ゜゜0'' level is input to the terminal TO of the slave processor 2, and thereby the slave processor 2 stops sending the transfer data to the input/output port -PA.

Further, the signal OBF is a signal indicating that the transfer data from the mask processor 1 is stored in the input/output port PA, and this signal OBF is given to the slave processor 2 as an interrupt signal INTs.

For detailed operation of this interface section 3, please refer to "How to use μPD 8255" published by NEC Corporation.
(Document No. IEM-587A) and is well known, so the explanation here will be omitted.

Furthermore, in the above structural description, the overline attached to the signal name indicates that it is significant at the "O" level.

In the above structure, in the initial state, the input/output port PA and part of the PC of the interface section 3 function as mode 2 bidirectional human output ports. Control word is set.

Next, when mask processor 1 wants to transfer data to the slave processor side, address bus output (Ao = A
ts), the input/output device number of the slave processor 2 is sent to the decoder 4, the chip select signal CS is outputted from the decoder 4, and this chip select signal CS is supplied to the interface section 3, and the address signals AI and AO are set to "0". Supplied to the interface section 3.

Then, the transfer data is sent to the data path output (Do'=D7), and then the data write signal WR is supplied to the interface section 3.

As a result, all transfer data from the mask processor 1 is stored inside the interface unit 3.

Then, a signal OBF is output from the interface section 3, and this signal OBF is supplied to the slave processor 2 as an interrupt signal INTs.

As a result, the slave processor 2 reads the transfer data from the mask processor 1 stored in the interface section 3 through interrupt response processing.

After this, the interface section 3 sends an acknowledge signal ACK via the input/output port P2 and the input/output expansion unit 5.
(a signal indicating that transfer data has been received) is sent back to the interface section 3.

As a result, the sending of the signal OBF from the interface section 3 is stopped, and one data transfer process is completed.

Next, when the slave processor 2 sends data to the mask processor side, the slave processor 2 sends the data to be transferred to the data path output from port P1,
Next, in order to store this data in the interface section 3, a strobe signal STB is applied to the interface section 3 via the port P2 and the input/output expansion unit 5.

Then, the data transferred from the slave processor 2 is stored in the interface unit 3.

At this time, when the transfer data is stored in the interface section 3, a signal IBF indicating that the stored contents have not yet been read out from the mask processor 1 is sent to the interface section 3.
is returned to the terminal TO.

As a result, slave processor 2 stops sending the transfer data from port PI and sending the strobe signal STB from port P2.

Thereafter, the interface section 3 outputs an interrupt signal INT for the mask processor 1 to read the transfer data stored in the interface section 3 in response to an interrupt.
2 and the input/output expansion unit 5.

Then, the mask processor 1 outputs a readout signal RD in response to the interrupt signal INT on the slave processor side.

This data read signal RD has A1="0", AO="
0" and CS2 are input to the interface section 3 together with the signals of "0".

As a result, the data stored in the interface section 3 is read by the mask processor 1.

At this time, when the data stored in the interface section 3 is read by the mask processor 1, the signal IBF output from the interface section 3 becomes "0", so the slave processor 2 stops sending out the interrupt signal INT. .

As described above, according to the present invention, data transfer between two processor units can be performed by a single interface section, and the coupling relationship between each unit can be simplified.

In the above embodiment, an example in which the present invention is configured with two processor units has been described, but a structure including a larger number of processor units can be implemented in the same manner.

However, in this case, it is necessary to prioritize interrupt signals from the slave side.

[Brief explanation of the drawing]

The figure is a block diagram showing one embodiment of the present invention. 1...Mask processor, 2...Slave processor, 3...Interface section, 4
・・・・・・Tecoder, 5：Input/output expansion unit.

Claims (1)

[Claims for Utility Model Registration] A multiprocessor device that performs overnight data transmission between a first processor and a second processor and predetermined arithmetic processing based on the transmission data, comprising a register for storing transmitted data. , a programmable peripheral interface capable of bidirectionally switching the data transmission direction is arranged between the data buses of the first processor and the second processor, and data from the first processor to the second processor is transmitted from the first processor to the second processor. By causing the stored data to be stored in the register by a data write signal issued, and providing the second processor with a signal indicating that the data has been stored in the register, which is issued from the programmable peripheral interface, as an interrupt signal, The second processor receives the data in response to an interrupt, and the data transmitted from the second processor to the first processor is stored in the register in advance, and then an interrupt signal is given to the first processor. A multiprocessor device configured to receive a data read signal in response to an interrupt by providing it to the programmable peripheral interface.