JPS61296459A - Data processor - Google Patents

Abstract

PURPOSE:To prevent the processing speed of a CPU from reduction due to direct memory access (DMA) transfer and to check the generation of a data transfer error by executing the DMA transfer of data between a buffer and a bubble memory through the 2nd bus. CONSTITUTION:Data are read out from the bubble memory 3 by setting up addresses in a common memory 6 for storing the read data in a DMA transfer control circuit 5. The data are successively read out from the memory 3 and DMA-transferred to the specified addresses in the memory 6 through a local bus 8. When the data in the memory 6 are written in the bubble memory 3, the addresses storing the data are set up in a DMA circuit 5. A CPU 1 sets up the writing data addresses, the number of data and a writing instruction in a controller 4. Consequently, data are successively read out from the memory 6 and DMA-transferred to the addresses of the bubble memory 3 which are specified by the CPU 1 through the local bus 8.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention generally relates to a data processing device, and more particularly to a data processing device equipped with a bubble memory.

[Conventional technology]

FIG. 2 is a block diagram showing the configuration of a conventional data processing device, particularly a data processing device incorporating a bubble memory.

In FIG. 2, 1 is a CPU, 2 is a main memory in which, for example, RAM is used, 3 is a bubble memory, 4 is a bubble memory controller that controls the driving of the bubble memory 3, and 5 is the main memory 2 and the bubble memory 3. Direct memory e-access (T) IRECT MEMORY that controls direct transfer of input/output data between
ACC'ESS) (hereinafter referred to as "DMA") transfer control circuit, and the DMA transfer control circuit 5 is to be driven based on the command output from the CPU 1. The memory controller 4 and the DMA transfer control circuit 5 are connected via a CPU bus T, respectively.

Next, the operation of the data processing apparatus having the above-described configuration will be described below. When reading data stored in the bubble memory 3, the DMA transfer control circuit 5 is sent from the CPU 1 via the CPU bus 7 to set the address of the main memory 2 where the data is to be stored in the DMA transfer control circuit 5. A predetermined signal is output. When an address is set in the DMA transfer control circuit 5, the CPU 1 sends the address, number of data, and read command of the data to be read from the bubble memory 3 to the bubble memory controller 4 via the CPU bus 7. output a predetermined signal. As a result, the data stored in the bubble memory 3 is sequentially read out and DMA transferred by the DMA transfer control circuit 5 to the address in the main memory 2 designated by the CPU 1. On the other hand, when writing data stored in the main memory 2 to the bubble memory 3, the CPU 1 sends a signal to the CPU bus to set the address of the main memory 2 where the data is stored in the DMA transfer control circuit 5. A predetermined signal is output to the DMA transfer control circuit 5 via 7. When the address is set in the DMA transfer control circuit 5, the CPU 1 sets the address of data to be written to the bubble memory 3, the number of data, and a write command in the bubble memory controller 0-4 via the CPU bus T. Output a predetermined signal. As a result, the data stored in the main memory 2 is sequentially read out,
The DMA transfer control circuit 5 performs DMA transfer to the specified address of the bubble memory 3 via the CPU bus 7.

[Problem that the invention seeks to solve]

A conventional data processing device with a built-in bubble memory is configured as described above, and the data stored in the bubble memory 3 is directly DMA-transferred to the main memory 2 by the DMA transfer control circuit 5, and during the DMA transfer period, Since the CPU 1 is held, a problem arises in that the processing speed of the CPU 1 decreases in data processing apparatuses in which the bubble memory 3 is frequently accessed. Another problem is that once the data transfer is started, if the bubble memory 3 is not sequentially accessed within a certain period of time, a transfer error will occur.

This invention was made to solve the above-mentioned problems, and it is possible to prevent a decrease in CPU processing speed due to DMA transfer, and also to prevent data transfer errors from occurring. The purpose is to obtain a data processing device.

[Means for solving problems]

The data processing device according to the present invention includes a buffer connected to a first bus, and the buffer, the data transfer control means, and the bubble memory controller are connected to each other via a second bus that is not connected to the CPU. It is something that is connected.

[For production]

In the data processing device of the present invention, since the DMA transfer of data between the buffer and the bubble memory is performed via the second bus, the CPU operates without being held during the DMA transfer; Data transfer errors will no longer occur.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a data processing device according to an embodiment of the present invention. In FIG. 1, 1 is a CPU, 2 is a main memory in which, for example, RAM is used, 3 is a bubble memory, 4 is a bubble memory controller that controls the driving of the bubble memory 3, and 5 is a bubble memory 3 and a common memory. The DMA transfer control circuit 5 controls direct transfer of input/output data between the CPU 1 and the CPU 1. The DMA transfer control circuit 5 is driven based on a command output from the CPU 1. 6 is a common memory that stores bubble memory data. The aforementioned CPU 1, main memory 2, bubble memory controller 4, DMA transfer control circuit 5, and common memory 6 are connected via a CPU bus 7, respectively. Bubble memory controller 4, DMA
The transfer control circuit 5 and the common memory 6 are connected to each other via a local bus 8 which is not connected to the CPU 1.

Next, the operation of the data processing apparatus having the above-described configuration will be described below. When reading data stored in the bubble memory 3, the address of the common memory 6 where the data is to be stored must be set in the DMA transfer control circuit 5 (from the CPU bus 7 to the DMA transfer control circuit via the CPU bus 7). 5. When the address is set in the DMA transfer control circuit 5, the CPU 1 sends the address of the data to be read from the bubble memory 3, the number of data, to the technical full memory controller 4 via the CPU bus γ. A predetermined signal is output to set a read command.As a result, the data stored in the bubble memory 3 is sequentially read out, and the address of the common memory 6 specified by the CPU 1 is transferred from the DMA transfer control circuit 51/I: DMA transfer is performed via the local bus 8.On the other hand, when writing data stored in the common memory 6 to the bubble memory 3, the address of the common memory 6 where the data is stored is sent to the DMA transfer control circuit 5. In order to set the address, a predetermined signal is output from the CPU 1 to the DMA transfer control circuit 5 via the CPU/
The PU 1 outputs a predetermined signal to the bubble memory controller 4 via the CPU bus 7 to set the address of data to be written into the bubble memory 3, the number of data, and a write command. As a result, the data stored in the common memory 6 is sequentially read out, and DMA-transferred by the DMA@transmission control circuit 5 to the address of the bubble memory 3 designated by the CPU 1 via the local bus 8.

In addition, in the above embodiment, the common memory 6 and the bubble memory 3
Although the DMA transfer control circuit 5 is used as means for controlling direct data transfer between the DMA transfer control circuit 5 and the DMA transfer control circuit 5, a simple presettable address counter may be used instead of the DMA transfer control circuit 5. Further, in place of the common memory 6 used in the above embodiment, a first-in-first-out register (FIFO) for transferring data between the epUl and the bubble memory controller 4 can be used.

〔Effect of the invention〕

As described above, according to the present invention, since the DMA transfer of data between the buffer and the bubble memory is performed via the second bus, it is possible to prevent a decrease in the processing speed of the CPU due to the DMA transfer. This has the effect of providing a data processing device that can perform the above operations and prevent the occurrence of data transfer errors.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a data processing apparatus according to an embodiment of the present invention, and FIG. 2 is a block diagram showing the configuration of a conventional data processing apparatus. In the figure, 1 is the CPU, 2 is the main memory, 3 is the bubble memory, 4 is the baffle memory controller, and 5 is the DMA.
Transfer control circuit, 6 is common memory, 7 is CPU bus, 8
To! The same reference numerals in each figure indicate the same or corresponding parts. Patent applicant: Mitsubishi Electric Corporation 1] 1 Agent: Patent attorney 1) Hiroshi Sawa...1
(2 others) Figure 1 7: CPU bus 8: Local bus

Claims (1)

[Claims] A bubble memory controller that controls driving of the CPU and the bubble memory, and a data transfer control means that controls direct transfer of input/output data performed via the bubble memory based on command output from the CPU, connect a first bus. In the data processing apparatus, a buffer connected to the first bus is provided, and the buffer, the data transfer control means, and the bubble memory controller are connected to a second bus, which is not connected to the CPU. A data processing device characterized in that it is connected via a bus.