JPS6336356A - Message transferring system - Google Patents

Abstract

PURPOSE:To attain high speed transfer by making message transfer through a storing means that connects the body of a device and an interface. CONSTITUTION:Control information is transferred by direct control of microprocessors in the body 10 of the device and an interface 20 through the first or second storing means 31, 32. On the other hand, the third storing means 34 used for DMA transfer between memories in the body 10 of the device and the interface 20, the first DMA controller 12 that performs DMA transfer between the third storing means 34 and the first memory 31 and the second DMA controller 22 that makes DMA transfer between the third storing means 34 and the second memory 32 are provided and data are transferred from each microprocessor independently through the third storing means 34 by control by the first and second DMA controllers 12, 22. Thereby, messages can be transferred without using a common memory, and the transfer speed can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a message transfer method between an input/output interface equipped with a microprocessor and an information processing device main body.

(Prior Art) Conventionally, message transfer between an input/output interface (interface board) such as a communication interface equipped with a microprocessor and an information processing device (host device) is generally performed via a shared memory. It was a target. However, in this method, a part of the memory space of the interface and the main body of the device is used as (the area of) the shared memory for transfer, so there is a problem that the memory space becomes small. Additionally, when transferring messages via shared memory, shared memory access must be arbitrated between the interface and the device itself.
There was also a problem with slow transfer speeds.

(Problems to be Solved by the Invention) As mentioned above, in the past, messages were transferred between the input/output interface and the information processing device main body via shared memory, so there was little memory space that each could freely use. In addition, there was a problem in that high-speed transfer was difficult because arbitration of shared memory access was required.

The present invention has been made in view of the above circumstances, and its object is to provide a message transfer method that allows message transfer between a device main body and an input/output interface to be performed at high speed without using a shared memory.

[Structure of the Invention (Means and Operations for Solving Problems) This invention provides a first storage means for temporarily storing control information to be transferred from the information processing device main body to the interface, and a first storage means for temporarily storing control information to be transferred from the interface to the device main body. A second storage means for temporarily storing information is provided, and control information is stored in the first storage means by direct control of each microprocessor in the device body and the interface.
Alternatively, while transferring via the second storage means, a third storage means provided for DMA transfer between each memory in the device main body and the interface, and DMA transfer between the third storage means and the first memory. a first DMA controller;
A second DMA controller is provided to perform DMA transfer between the third storage means and the second memory, and data is transferred via the third storage means independently from each of the microprocessors under the control of the first and second DMA controllers. This makes it possible to transfer messages without using a shared memory, and since there is no shared memory access, there is no need for arbitration, and the transfer speed can be improved.

(Embodiment) FIG. 1 is a block diagram showing an embodiment of an information processing apparatus to which the present invention is applied. In the figure, 10 is an information processing device main body, and 20 is an input/output interface such as a communication interface that is connected to the device main body 10 and exchanges messages with the device main body 10. Device body 10
is a microprocessor 1 that controls the entire device main body 10.
1, a DMA controller 12 and a memory 13. Microprocessor 11, DMA controller 1
2 and memory 13 are interconnected by a system bus 14.

In addition, the input/output interface 20 includes a microprocessor 21 and a DMA controller 22d, similar to the device main body 10.
5 and a memory 23. microprocessor 2
1. The DMA controller 22 and memory 23 are interconnected by a local bus 24. Device body 10
System bus 14. Between the local bus 24 of the input/output interface 20, there is a buffer for temporarily storing control information, which will be described later, transferred from the device main body 10 to the input/output interface 20, such as a FIF○ (first in first out) register 31, and an input/output buffer. FIFO register 32 that temporarily stores control information transferred from the output interface 20 to the device main body 10, occurrence of interrupt, DMA
A command/status register 33 including a command register used to instruct the start of an operation and a status register indicating the status of input/output operations, and a DMA register section 34 are connected. This DMA register section 34
is a storage means that temporarily stores DMA transfer data, such as a DMA register, and a DM that requests data transfer in response to data transfer (data set) to this register, or data read/data extraction from this register.
It includes a request signal output section (none of which is shown) that outputs an A transfer start request signal.

FIG. 2 shows a message format applied to the information processing apparatus shown in FIG. This message consists of a 1-byte command/response identifier CM (first byte), 2-byte length information + EiLI (second and third bytes), a parameter section PARM containing address information, etc., and a data section DATA. Length information Ll indicates the lengths of the parameter section P A RM and the data section DATA. Generally, the information from the first byte to the parameter section PARM is called control information.

Next, the operation of one embodiment of the present invention will be explained.

In this embodiment, the procedures for transfer from the device main body 10 to the input/output interface 20 and from the input/output interface 20 to the device main body 10 are the same. Therefore, taking the transfer from the device main body 10 to the input/output interface 20 as an example, a) a case of message transfer of only control information, and b) a case of message transfer including data.
Each will be explained.

a, υ Message transfer of only Hill information a-1 First, the microprocessor 11 of the device main body 10 issues the command /'
The status register portion of the status register 33 is read via the system bus 14, and the FIFO register 31
Check if is empty.

The microprocessor 11 of the a-2 device main body 10 is an FI
When it is detected that the F○ register 31 is empty, control information to be transferred to the input/output interface 20 is written to the FIF○ register 31 via the system bus 14.

a-3 The microprocessor 11 of the device main body 10 sets an interrupt command in the command register portion of the command/status register 33, and outputs the input/output interface 2.
Generates an interrupt to 0.

The microprocessor 21 of the a-4 person output interface 20 receives an interrupt from the command/status register 33, and transfers the control information (written by the microprocessor 11 of the device body 10 from the FIF○ register 31) to the local bus 24. Load via.

b. Message transfer including data part-1 First, the microprocessor 11 of the device main body 10,
The status register portion of command/status register 33 is read via system bus 14 to check whether FIFO register 31 is empty and whether DMA controller 12 is ready.

The microprocessor 11 of the b-2 device main body 10 is an FI
When it is detected that the FO register 31 is empty and the DMA controller 12 is in a ready state, the DMA controller 12 is set up in accordance with the transfer data.

By this set-up, a transfer start address indicating the start position of the area of the memory 13 to be read accessed is set in an address counter, and a transfer data length is set in a transfer length counter (none of which is shown).

b-3 Control information is transferred according to the steps a-2 to a-4 described above.

When the microprocessor 21 of the b-4 output interface 20 reads the control information from the FIFO register 31, it sets up the DMA controller 22 in accordance with the control information. By this cell 1-up, a transfer start address indicating the start position of the area of the memory 23 to be write accessed is set in an address counter, and a transfer data length is set in a transfer length counter (both not shown).

The microprocessor 21 of the b-5 person output interface 20 sets a DMA transfer start command in the command register portion of the command/' data status register 33,
Generates a DMA transfer start request signal to the device main body 10.

b-6 The DMA controller 12 of the device main body 10 receives a DMA transfer start request signal from the command/' data register 33, reads data from the memory 13, and transfers the same data to D to □i A via the system bus 14. A data transfer operation is performed to set the register 29 section 34.

D by the DMA controller 12 of the b-7 device main body 10
When data is occupied in MA1929 section 34, DMA1
From the 929 section 34, the DM of the input/output interface 20
A DMA transfer start request signal to the A controller 22 is generated.

When the DMA controller 22 of the b-8 person output interface 20 receives the DMA transfer start request signal from the DMA 1929 unit 34, it retrieves data from the DMA 1929 unit 34 and stores the same data in the memory 23 via the local bus 24.
Performs data transfer operations that occupy the area.

When data is taken out from the DMA register section 34 by the b-9 person output interface 20 and the \AA controller 22, the data is sent from the register section 34 to the DM of the device main body 10.
A (next) DMA transfer start request signal to the A controller 12 is generated.

By repeating steps b-6 to b-9 from b-10 onwards, the data of the specified length valve is transferred between the memory 13 of the device main body 10 and the memory 23 of the input/output interface 20. The end of the data transfer is instructed by the DMA controller 12.22 (a signal output when the count of a transfer length counter (not shown) reaches 0).

Note that in the actual droplet example described above, a case has been described in which a register is used as a storage means for temporarily storing DMA transfer data, but it is also possible to use a buffer memory.

[Effects of the Invention] As described in detail above, according to the present invention, the following effects can be achieved.

(1) Message transfer between the information processing device main body and the input/output interface is carried out by a storage device connecting the device main body and the interface (i.e., a storage device used for control information transfer, and a storage device used for DMA transfer of the data section). Unlike the conventional system which uses a shared memory, there is no possibility that the memory space of the main body of the apparatus and the input/output interface will be reduced.

(2) Because (1) above eliminates the need for arbitration between the device itself and the interface for memory access,
High-speed transfer becomes possible.

(3) Since the data part can be transferred independently from the microprocessor by the DlvlA controller,
The burden on the microprocessor can be reduced.

(4) Message transfer can be performed in both directions simultaneously.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of an information processing apparatus to which the present invention is applied, and FIG. 2 is a diagram showing a message format applied to the information processing apparatus of FIG. 10... Information processing device main body, 41.21... Microprocessor, 12.22... DMA controller,
13.23...Memory, 31.32...FIFO register, 33...Command/status register, 3
4...DMA register section. Applicant's representative Patent attorney Takehiko Suzue Figure 1 Figure 2

Claims (1)

[Claims] an information processing device body including a first microprocessor and a first memory; a second microprocessor and a second memory;
In an information processing device comprising a built-in memory and an input/output interface for exchanging messages with the device main body, a first storage means for temporarily storing control information to be transferred from the device main body to the interface; a second storage means for temporarily storing control information to be transferred from the interface to the device main body; a third storage means for temporarily storing DMA transfer data between the first and second memories; a first DMA controller that performs DMA transfer between the third storage means and the second memory; and a second DMA controller that performs DMA transfer between the third storage means and the second memory; 2 The above-mentioned first
or transferred via a second storage means, and the data is transferred to the third DMA controller independently from the first and second microprocessors under the control of the first and second DMA controllers.
A message transfer method characterized by transfer via storage means.