JPH0223451A - Dma transfer system - Google Patents

Abstract

PURPOSE:To prevent the effect of CPU runaway on the other part by separating the buses of a main CPU and a sub-CPU, and transferring data with repeating an I/O buffer and without sharing the bus. CONSTITUTION:Presently, when the data are transferred from a memory 4b to a memory 3, a sub CPU 2b writes the command of a transfer start through a bus B2b to an I/O buffer 6b. The command is notified through a bus B1 to a main CPU 1. Further, the CPU 2b instructs address information for a DMA controller 5b, activates the controller 5b, and the controller 5b once writes the data of the memory 4b through the bus B2b to a buffer 7b according to the address information. The controller 5b transfers the data of the buffer 7b through the bus B1 to the memory 3. Thus, by repeating the buffer and without sharing the bus, the effect of the CPU runaway on the other part is prevented.

Description

[Detailed Description of the Invention] (Summary) Regarding a DMA transfer method in which a DMA controller transfers data between memories connected to a main CPU and a sub-CPU with different bus systems, even if one CPU goes out of control, the other In order to avoid affecting the memory of the CPU, the buses of the main CPU and sub CPU are separated, and communication between the two CPUs is carried out via the first I/O frame. Data transfer between the memories is configured to be performed by a tx DMA controller via a second I/O buffer.

[Industrial application field]

The present invention relates to a DMA transfer method, and particularly relates to a DMA (direct memory access) transfer between memories connected to a main CPU and a sub-CPtJ with different bus systems.
% method performed via a controller With the recent demand for faster computer systems, there is a need to reduce the burden on the main CPU by performing processing such as line control on a CPU separate from the main CPU. ing. For this reason, high-speed DMA data transfer using a DMA controller is required between the memories of the main CPU and the sub-CPU.

The roller 5 transfers data from the memory 4 to the memory 3 via both buses B2 and B1 in accordance with the designated address information.

[Conventional technology]

FIG. 3 shows an example of a conventionally used DMA transfer method, in which the memory 3 is connected to the bus B1 of the main CPtJl, and processing such as line control is performed to reduce the burden on the main CPU 1. Sub-CPtJ2 that shares the
The memory 4 is connected to the bus B2 of the computer. and,
These two buses B1 and B2 are connected to each other, and a DM that performs an operation for inter-memory transfer is also connected to the connection line.
A controller 5 is connected.

Now, for example, when data is transferred from memory 4 to memory 3, sub CPtJ2 first transfers data from memory 4 to memory 3.
, the data transfer source address of the memory 4, the transfer destination address of the memory 3, the address size (width), etc. are specified. After this, when the DMA controller 5 is activated, the DMA control (problem to be solved by the invention) is performed. In such a conventional DMA transfer method, both buses B1
and 82 are connected, so both the main CPUI and the sub CPU 2 can access the other party's memory directly without going through the DMA controller 5 in the same way as their own memory.
There is a problem in that when U2 goes out of control and destroys the memory, not only the memory of the runaway CPU but also the memory of the normal CPU is destroyed.

Therefore, an object of the present invention is to prevent, in such a DMA transfer system, even if one CPU goes out of control, the memory of the other CPU is not affected.

(Means for Solving the Problems) In order to achieve the above object, in the DMA transfer method according to the present invention, as shown in principle in FIG.
The buses of the and sub CPU 2 are separated, communication between both CPUs is performed via the first I/O buffer 6, and data transfer between the memories 3 and 4 is performed via the second I/O buffer 7. The configuration is such that the DMA controller 5 performs the following steps.

[Function] In the present invention, as shown in FIG.
- Address information, etc. is exchanged between the sub CPUs 2 using the first I/O buffer 6.

During data transfer, the DMA controller 5 receives the address information from the CPU and transfers the data from one memory to the second memory! The data is temporarily stored in the /O buffer 7 and then transferred to the other memory.

In this way, since data transfer between memories is always performed via the second I/O buffer 7, the DMA controller 5 can be used for transfer between the I/O buffer 7 and the memory, and both There is no need to connect the CPU bus. Therefore, each CPU cannot access the memory of the other CPU.

Therefore, it is possible to transfer data between CPUs without using a common bus, and a system is constructed in which the own memory and the other party's memory are completely separated, and it is not affected by the runaway of the other party's CPU. It turns out.

〔Example〕

FIG. 2 shows an embodiment in which the DMA transfer method of the present invention shown in FIG. In this system, each sub-CPU controls the line and exchanges input/output data with the main CPU, and the main CPU monitors and controls the entire system based on that data. Each sub-CPU has internal buses B2a-B2c. have. The sub CPU 2a is connected to the bus B2a.

Memory 4as first I/O bar, Noah 6a, second I/O
Buffer 7 a-, and DMA controller (DMAC
)5a is connected to the bus B2b, and the sub CPU2b,
Memory 4b, first [/○ buffer 6b, second I/O
Buffer 7b and DMA controller (DMAC) 5
b, bus B2c has sub CPU2e and memory 4C
1 First I/O buffer 6c, second I/O buffer 7
c, and a DMA controller (DMAC) 5c are connected to each other.

Of these, the r/O buffer 6a of the monitoring/control device A, the I/O buffer 7a%, the DMA controller 5a,
I/O buffer 6b, I/O buffer 7b, DMA controller 5b of monitoring/control device B, and I/O buffer 6c of monitoring/control device C, I/O buffer 77C, DM
The A controller 5c is also connected to a bus B1 to which the main CPUI and its memory 3 are connected and separated from the buses B2a, B2b, and B2c.

Next, a case will be described in which inter-memory data transfer in this embodiment is performed from the memory 4b to the memory 3.

■First, sub CPU2b connects I/O via bus B2b.
A command for starting the transfer (for example, the transfer source address and address width of the local memory 2b) is written to the O buffer 6b.

(2) This I/O buffer 6b command is notified to the main CPU via bus B1.

(2) The sub CPU 2b activates the DMA controller 5b by instructing the DMA controller 5b the transfer destination address received in (2) above, as well as the transfer source address of its own memory and its width.

■The DMA controller 5b transfers the designated data in the memory 4b to the bus B according to the address information specified in ■.
2b to the I/O buffer 7b.

(2) The DMA controller 5b transfers the data written to the I/O buffer 7b to the memo+73 via the bus B1, and ends the operation.

In this way, the main CPU and its memory 3 and the sub CPU and its memories 43 to 4c are independent from each other and cannot be accessed in common, so even if one CPU goes out of control, it will not affect the memory of other CPUs. I won't give anything.

(Effects of the Invention) As described above, according to the DMA transfer method of the present invention, the main CP, U and sub CPU buses are separated from each other, and in data transfer between both memories, I/O
Since the configuration is such that the buffers are relayed and the bus is not shared, even if one cPU goes out of control, the memory of the other CPU will not be destroyed.

Furthermore, since DMA can be used, data transfer between CPUs can be performed efficiently at high speed, which in turn contributes to higher speed and higher reliability of the system.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the principle of a DMA transfer method according to the present invention, FIG. 2 is a block diagram showing an embodiment of a DMA transfer method according to the present invention, and FIG. 3 is an example of a conventional DMA transfer method. FIG. In FIG. 1, ■...main CPU. 2...Sub CPU. 3.4... Memory, 5... DMA controller, 6... First I/O buffer, 7... Second I/O buffer. In the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] Main CPU (1) and sub CPU (2) with different bus systems
) is a DMA transfer method in which a DMA controller (5) transfers data between the memories (3) and (4) connected to the main CPU (1) and the sub-CPU (2), respectively. Communication between both CPUs (1) and (2) is performed via the first I/O buffer (6), and the memory (3) (
4) A DMA transfer method characterized in that the data transfer between the two is performed by the DMA controller (5) via a second I/O buffer (7).