JPS6346559A - Dma controller - Google Patents

Abstract

PURPOSE:To perform the DMA transfer between buses with the highest performance and the maximum efficiency of each bus and regardless of the performance of each bus, by dividing the transfer of data between two buses into the bus/data transfer and the data memory/bus transfer respectively. CONSTITUTION:The bus connection control parts 1 and 3 and the driver receivers 4 and 6 are connected to buses A and B respectively. Then a data transfer control part 2 is added together with a data buffer memory 5. Both parts 1 and 3 perform the interface control between both buses A and B and produce various bus control signals for bus arbitration, addresses, etc. Then the transfer of data between both buses is divided into the transfer between the bus A and the memory 5 and transfer between the bus B and the memory 5. Therefore the arbitration jobs are possible independently of each other between buses A and B. In addition, the DMA transfer is attained between both buses with the highest performance and the maximum efficiency of each bus and regardless of the performance of each bus by increasing the data transfer timing speed up to a level at which the speed of the memory 5 can follow the bus of a higher bus.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a DMA controller, and particularly to a multi-C
The present invention relates to a DMA controller when performing DMA between two buses such as a common bus and a local bus in a PU.

[Conventional technology]

DMA controllers are indispensable as peripheral circuits for microprocessors, and many circuits have been published, and many have been implemented as LSIs.

Referring to FIG. 2, an example of the conventional technology connects bus A and bus B using a bus connection control unit 8 that controls each bus through bus arbitration, and a driver and receiver 9 that control data access. After receiving a transfer command from the CPU, etc., the bus connection control unit 8 transmits the DMA transfer command.
1\output data transfer control unit 7.

However, when multiple CPUs use DMA between two buses with different speeds, such as a common bus and a local bus,
When data is to be transferred, access rights to two buses are obtained simultaneously, the timings of both buses are matched, and data is transferred.

To obtain bus access at the same time.

Even if the transfer speeds of two buses are the same, both buses need to be empty, and it takes longer than acquiring access to one bus, and the bus that is acquired first will wait until the next bus is acquired. Waiting time is required. Furthermore, when there is a difference in the transfer speeds of two buses, the bus with the faster transfer speed needs to adjust to the bus with the slower transfer speed, which also requires waiting time.

These reduce bus usage efficiency and response speed, and if bus arbitration is performed frequently as in the case of a common bus for a plurality of CPUs, the performance may drop significantly and become unusable.

[Problem that the invention seeks to solve]

The conventional DMA controller described above acquires access rights to two buses at the same time and synchronizes the timing of the two buses to transfer data, so there is a lot of wasted waiting time to transfer data. It has the disadvantage of reducing usage efficiency. SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a DMA controller that overcomes the above-mentioned drawbacks.

[Means for solving problems]

Since the present invention has two buses, each bus connection control section has a connection control section.
Ruke≠Measurement and Tsukasa Kano you rose to 4r each;℃su←Susumakiki 4
1 has a deaf leprosy← and a driver/receiver, and a data transfer control unit and a data buffer sofa memory are provided in common to these, so that data transfer between the two buses is reduced to two transfers between the bus and the data buffer memory. It is configured to perform the arbitration separately, and as a result, the arbitration of the two buses is
Each bus can perform arbitration operations independently of the other bus, and the data transfer timing can be adjusted to the maximum speed of each bus by increasing the speed of the data buffer memory until it can follow the faster bus. But it is possible.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In FIG. The data transfer control unit 2, which generates bus control signals, receives data from the CPU, etc.
Upon receiving the transfer command, the bus connection control unit 1 divides the data into data transfer sequences for the bus A and the data bus/sofa memory 5 and for the bus B and the data bus/sofa memory 5.
Issue an order to 2. The driver 7 and receivers 4 and 6 connect the bus A or bus B and the data variation memory 5.

Comparing FIG. 1 and FIG. 2 showing the conventional technology, in the case of the present invention shown in FIG. B can be accessed independently. In other words, when viewed from bus A or bus B, the access required for data transfer is minimal. This is a feature of the present invention.

Figures 3 (a> and (b)) show the difference in timing between the two. The sequence in Figure 3 (a) is in accordance with the present invention, and the sequence in Figure 3 (b) is in the conventional technology. In these examples, access to bus B is slower than bus A, and in the sequence shown in FIG. 3(b), bus B arbitration took longer than bus arbitration.See The shaded area with reference numeral 12 is the time after bus A due to the difference in bus arbitration time, and the shaded area with reference numeral 13 is the waiting time of bus A due to the difference in access timing.

These waiting times denoted by reference numerals 12 and 13 inevitably occur unless the two buses perform exactly the same operation, and degrade the transfer efficiency of each bus (bus A in the figure). In the case of the present invention, that is, in the sequence shown in FIG. 3 (a>), this waiting time does not occur.

〔Effect of the invention〕

As explained above, the present invention transfers data between two buses, one between the bus and the data memory, and the other between the data memory and the bus.
By configuring the transfer to be performed in divided steps, the DMA transfer between two buses can be realized with the highest performance and efficiency of each bus, regardless of the performance of each bus.

[Brief explanation of the drawing]

Fig. 1 is a plot diagram showing the configuration of an embodiment of the present invention, Fig. 2 is a plot diagram showing an example of the configuration of a DMA controller according to the conventional technology, and Figs. 3(a) and (b). ) is a chart showing the evening and timing of both. 1... Bus connection control unit A, 2... Data transfer control unit, 3... Bus connection control unit B, 4...
...Data bus driver 7, luciver A, 5...
...Data buffer memory, 6...Data bus driver/receiver B, 7...Data transfer control unit, 8...Bus connection control unit, 9...・・・
Data bus driver/receiver, 12/13...
・Waiting time. $1 picture

Claims (1)

[Claims] In a DMA controller that performs DMA transfer of data between two buses, each bus is equipped with a bus connection control section that controls the bus and a driver/receiver that controls data input/output. A DMA controller comprising a data buffer memory that writes data transferred from a bus and reads the written data and transfers it to another bus.