JPS62184557A - Microprocessor bus interface circuit - Google Patents

Abstract

PURPOSE:To facilitate the reduction of the scale of a hardware, and the modification or addition of functions, by dividing each function part of an interface circuit, and communicating between divided functions with a general control signal in which the difference among the classes of processors are absorbed. CONSTITUTION:A data transfer circuit 201 informs the presence of an output data from a functional block to a bus control signal generation circuit 202 with a general control signal RQO. The circuit 202, in an I/O transfer, requests an interruption to output to a control bus 203. A general purpose microprocessor 204, when receiving the interruption, sends a reading control signal onto the bus 203. A bus control signal conversion circuit 205, after converting the control signal to a general control signal DO within the inside of a functional module corresponding to the classes of the general purpose microprocessors, outputs it to the circuit 201, and the circuit 201 outputs a data according to the signal DO to a data bus 206. The data is received by the processor 204. Adversely, when the processor 204 outputs the data, the circuit 201 receives the data almost in a reverse action.

Description

Detailed Description of the Invention (1) Technical field to which the invention pertains The present invention relates to a microprocessor bus included in one functional block for connecting a functional block and a general-purpose microprocessor bus of household equipment in which the functional block is incorporated. This invention relates to bus interface circuits.

(2) Prior Art Conventionally, such microprocessor bus interface circuits have been designed to limit the type of microprocessor to be connected to the bus interface circuit □. For this reason, a function that performs data transfer and a function that corresponds to control signals of the microprocessor bus may be integrated, or a microprocessor - The bus interface circuit was configured to communicate using internal signals that depended on the bus control signals of the target microprocessor.

Also, regarding the data transfer method, I10
The transfer method or DMA transfer method was set, and the address generation section and bus control signal generation section were designed. For this reason, the function of transferring data and the function of generating bus control signals to be output to the microprocessor bus have been integrated, or a part of one function has been shared.

FIG. 4 is a diagram illustrating an example of I10 transfer according to the conventional technique, in which 100 is a microprocessor interface circuit according to the conventional technique, 101 is a microprocessor in a functional block, 102 is a data bus, 103 is a control bus, 104 is a data transfer circuit, and 105 is a data transfer control circuit.

106 is a general-purpose microprocessor to which functional blocks are connected, 107 is a control bus, and 108 is a data bus.

To explain the operation of this, Microprocessor Nosa 101
puts data to be output from the functional block onto the data bus 102 and writes the data into the data transfer circuit 104 via the control bus 103. Data transfer circuit 104
monitors the control bus 103, and when it detects a write instruction, takes data from the data bus 102.

The data transfer control circuit 105 is a microprocessor 101
The data written from the data transfer circuit 104 is transferred and held within the data transfer circuit 104. If there is data to be output to the general-purpose microprocessor 106 inside the data transfer circuit 104, the data transfer control circuit 105 puts a take-over request signal on the control bus 107 in order to make the general-purpose microprocessor 106 take over the data. General-purpose microprocessor 106 responds to the take-over request and places a data read control signal on control bus 107. The data transfer circuit 104 monitors the control bus 107,
When a read instruction is detected, the data is output to the data bus 108 and the general purpose microprocessor 106 receives the data over the data bus 108 . After detecting that the general-purpose microprocessor 106 has responded to the take-up request, the data transfer control circuit 105 cancels the take-up request.

The data transfer control circuit 105 monitors the control bus 107 and, after the data reading sequence is completed, transfers the next data to be output within the data transfer circuit 104 and outputs a takeover request to the control bus 107. When the general-purpose microprocessor 106 writes data to a functional block, the data is placed on the data bus 108 and a write control signal is placed on the control bus 107. The data transfer circuit 104 is a control bus 107
is monitored and when a reading instruction is detected, the data bus 108
Retrieve data from. The data transfer system m circuit 105 monitors the control bus 107 and
When it detects that data has been written to the microprocessor 101, it transfers and holds the data inside the data transfer circuit 104, and sends a takeover request signal to the control bus 103 in order to make the microprocessor 101 take over the data. In response to the take-back request, the microprocessor 101 puts a data read control signal on the control bus 103 and takes the data from the data transfer circuit 104 via the data bus 102. The data transfer circuit 104 and the data transfer control circuit 105 monitor bus control signals output from the general-purpose microprocessor 106 to the control bus 107 to input/output and transfer data, and also perform data transfer corresponding to the general-purpose microprocessor 106. This functional block, which creates a request signal and outputs it to the control bus 107, is a dedicated circuit for the type of microprocessor targeted.

Because of this configuration, it was impossible to support types of microprocessors that the microprocessor bus interface circuit was not intended for, or it was necessary to add a circuit to convert the bus interface outside of one functional block. and connected to the microprocessor bus. In addition, when modifying the functional block to change the type of microprocessor targeted by the microprocessor bus interface circuit, or when changing the data transfer method such as changing the data transfer method to DMA, a new microprocessor must be installed. Not only some parts depend on the bus control signals, but also the data transfer functions require major modification, and in order to correspond to the bus control signals of multiple microprocessors, In the microprocessor bus interface circuit, it is necessary to prepare a bus control signal support section and a data transfer function section for each type of bus control signal that corresponds to the microprocessor, or to support multiple data transfer methods. Only the type of data transfer required an interface circuit.

(3) Purpose of the Invention The purpose of the present invention is to provide a microprocessor bus interface circuit with a plurality of control signal handling units and data transfer units in order to enable the microprocessor bus interface circuit to handle bus control signals of a plurality of microprocessors. Functional parts etc. may be required.

An object of the present invention is to provide a microprocessor bus interface circuit that solves the problem that major modifications and additions are required when changing or adding bus control signals and data transfer methods supported by the microprocessor bus interface circuit. .

(4) Structure of the invention (4-1) Differences between the characteristics of the invention and the conventional technology The present invention divides each functional section constituting a microprocessor bus interface circuit, and connects the microprocessor bus interface circuit between the functional sections. Unlike the control signals of the microprocessor to which the processor bus interface circuit is intended to correspond, the most important feature is that communication is performed using general-purpose control signals that absorb the differences between the types of processors. What is conventional technology? 1) Functional sections such as individual data transfer within the microprocessor bus interface circuit are separated from other functional sections corresponding to microprocessor control signals.

(2) Each functional unit operates in accordance with a general-purpose control signal that is different from the bus control signal of the microprocessor to which the interface circuit corresponds in the microprocessor bus ink interface circuit, and which absorbs the differences between the types of processors. (3) Of the functional units in the microprocessor bus interface circuit, the functional units that are affected by the type of general-purpose microprocessor that the interface circuit supports are: The configuration is limited to a functional unit that converts the general-purpose control signal used within the bus interface circuit, and (2) a functional unit that generates a bus control signal compatible with the microprocessor from the general-purpose control signal within the bus interface circuit.

etc. are different.

(4-2) Example FIG. 1 is a diagram explaining the first example of the present invention,
200 is a microprocessor interface circuit according to this embodiment, 201 is a data transfer circuit, 202 is a bus control signal generation circuit, 203 is a control bus of a general-purpose microprocessor to which functional blocks are connected, 204 is a general-purpose microprocessor, and 205 is a bus Control signal conversion circuit, 206 is a data bus, 207 is an address bus 9208
209 is an address generation circuit, and 209 is an external address bus 7.
210 is a memory, and 211 is a control register.

(1) In the case of I10 transfer When accessing (I10 transfer) using input/output commands of a general-purpose microprocessor from outside the functional block, there must be data output by the data transfer circuit 2゜1 from the functional block in order to operate this. is notified to the bus control signal generation circuit 202 using the general-purpose control signal RQO. The bus control signal generation circuit 202 that receives the signal RQO sends an output request interrupt to the control bus 203 in the case of I10 transfer.

1. Waits for the input operation of the general-purpose microprocessor 204.

The general-purpose microprocessor 204 receives an output request interrupt from the bus control signal generation circuit 202.

A reading control signal is placed on the control bus 203. Bus control signal change tf 11 times! 205 converts the control signal input from the control bus 203 into a general-purpose control signal DO inside the functional module according to the type of general-purpose microprocessor, and outputs it to the data transfer circuit 201, and the data transfer circuit 201 converts the data according to the general-purpose control signal. bus 2
Data is output to 06. Data output to data bus 206 is received by general-purpose microprocessor 204. Conversely, when the general-purpose microprocessor 204 outputs data, the bus control signal conversion circuit 205 converts the output control signal input from the control bus 203 into a general-purpose control signal DI corresponding to the type of general-purpose microprocessor, and then the data transfer circuit 201 output to the data transfer circuit 20
1 receives data from the data bus 206. After processing the received data, the data transfer circuit 201 notifies the bus control signal generation circuit 202 of the completion of the processing using the general-purpose control signal RQI, and the bus control signal generation circuit 202, which has received the signal RQf, generates a data write ready interrupt for the general purpose. to the microprocessor 204.

(2> In the case of DMA transfer When performing DMA transfer with the functional block acting as a bus mask to the outside of the functional block, the operation of this is explained as follows: The data transfer circuit 201 has data output from the functional block. is notified to the bus control signal generation circuit 202 by the general-purpose control signal RQO, and the bus control signal generation circuit 202 that receives the signal RQO sends a control signal to the control bus 203 for acquiring bus mastership according to the general-purpose microprocessor in the case of DMA transfer. Age, control bus 20
Among them, data bus 206. Bus ownership of address bus 207 is acquired from general-purpose microprocessor 204. The bus control signal generation circuit 202 also requests the address generation circuit 208 to generate a cutting edge address outside the functional block using the general-purpose control signal OA, and the address generation circuit 208 sets the address in the external address buffer 209. After acquiring the bus right, the bus control signal generation circuit 202 outputs a memory write control signal corresponding to the type of general-purpose microprocessor to the control bus 203 in order to output data to the memory 210 using the DMA transfer method, and also transfers data. General-purpose control signals Do and AO are output to the circuit 201 and the external address buffer 209 at timings corresponding to the type of general-purpose microprocessor, and the data bus 20
6 and address bus 207. When inputting from the memory 210 using the DMA transfer method, the bus control signal generation circuit 202 learns from RQI that the input buffer of the data transfer circuit 201 is empty.
In the case of DMA transfer, the control bus 203 sends a control signal for acquiring bus mastership according to the general-purpose microprocessor to the control bus 203. Data bus 206.
Bus ownership of address bus 207 is acquired from general-purpose microprocessor 204. Bus control signal generation circuit 202 also requests address generation circuit 20B to generate an input address to the outside of the functional block using general-purpose control signal IA, and address generation circuit 208 sets the address in external address buffer 209.

After acquiring the bus right, the bus control signal generation circuit 202 outputs a memory read control signal corresponding to the type of general-purpose microprocessor to the control bus 203 in order to input data from the memory 210 using the DMA transfer method. General-purpose control signals DI and AO are output to the transfer circuit 201 and external address buffer 209 at timings corresponding to the type of general-purpose microprocessor, an address is output to the address bus 207, and data is input from the data bus 206.

In addition, when writing control information to the control register 211 so that a functional block is controlled by in-home equipment, when the general-purpose microprocessor 204 outputs the control information to the data bus 206, the bus control signal conversion circuit 205 converts the general-purpose The output control signal of the microprocessor 204 is converted into a general-purpose control signal DI according to the type of general-purpose microprocessor and then output to the control register 211, and the control register 211 receives control information from the data bus 206.

With this configuration, the same data processing function unit can be shared by multiple general-purpose microprocessor types and data transfer methods, and the internal bus interface circuit can also be used for new types of general-purpose microprocessors. , bus control signal conversion circuit 205 and bus control signal generation circuit 20
This can be solved by simply adding or changing 2.

Furthermore, even when setting control information etc. in addition to transferring data from a general-purpose microprocessor, the bus control signal conversion circuit 205 can be shared between the data processing function section and the control register, making it possible to suppress an increase in hardware size. .

FIG. 2 is a diagram illustrating a second embodiment of the present invention,
300 is a microprocessor interface circuit according to this embodiment, 301 is a microprocessor inside a functional block, 302 is a data bus, 303 is a control bus, and 304 is a data transfer circuit.

(1) In the case of I10 transfer When accessing (I10 transfer) using input/output instructions of a general-purpose microprocessor from outside the functional block, the operation is as follows. 302 , a write control signal is placed on the control bus 303 , and the data is written to the data transfer circuit 304 . The data transfer circuit 304 notifies the bus control signal generation circuit 202 by the general-purpose control signal RQO that there is data to be output from the functional block. In the case of I10 transfer, the bus control signal generation circuit 202 that has received the RQO
03 and waits for the input operation of the general-purpose microprocessor 204. General-purpose microprocessor 2
04 receives an output request interrupt from the bus control signal generation circuit 202 and puts a read control signal on the control bus 203. The bus control signal conversion circuit 205 converts the control signal input from the control bus 203 into a general-purpose control signal DO inside the functional module according to the type of general-purpose microprocessor, and then outputs it to the data transfer circuit 304. Data is output to data bus 206 in accordance with the general-purpose control signal. data bus 206
The data output to the general-purpose microprocessor 204
will be taken over. Conversely, when the general-purpose microprocessor 204 outputs data, the bus control signal conversion circuit 205 converts the output control signal input from the control bus 203 into a general-purpose control signal DI corresponding to the type of general-purpose microprocessor.
After converting the data into a data bus 206, the data is output to the data transfer circuit 304, and the data transfer circuit 304 receives the data from the data bus 206. The data transfer circuit 304 notifies the microprocessor 301 via the control bus 303 that there is data fetched from outside the functional block.
2. Receive data through 2. After outputting the received data to the microprocessor 301, the data transfer circuit 304 notifies the bus control signal generation circuit 202 of the completion of processing using the general-purpose control signal RQl, and the bus control signal generation circuit 202 that has received the RQI is ready for data writing. The interrupt is sent to the general-purpose microprocessor 204 via the control bus 203.

+21 In the case of DMA transfer When performing DMA transfer with the functional block acting as a bus mask to the outside of the functional block, the operation will be explained as follows: The microprocessor 301 outputs data to be output to the outside of the functional block to the data bus 302. , a write control signal is placed on the control bus 303 and written to the data transfer circuit 304. The data transfer circuit 304 notifies the bus control signal generation circuit 202 that there is data to be output using the general-purpose control signal RQO. The control bus 20 receives a control signal for acquiring bus mastership according to the processor.
3. Bus rights to the data bus 206° and address bus 207 are acquired from the general-purpose microprocessor 204. The bus control signal generation circuit 202 also requests the address generation circuit 208 to generate a cutting edge address outside the functional block using the general-purpose control signal OA, and the address generation circuit 208 sets the address in the external address buffer 209. After acquiring the bus right, the bus control signal generation circuit 202 outputs a memory write control signal corresponding to the type of general-purpose microprocessor to the control bus 203 in order to output data to the memory 210 using the DMA transfer method, and
General-purpose control signals Do and AO are output to the data transfer circuit 304 and the external address buffer 209 at timings corresponding to the type of general-purpose microprocessor, and the data bus 2
06 and address bus 207. When inputting data from the memory 210 using the DMA transfer method, the bus control signal generation circuit 20 learns from RQI that the input buffer of the data transfer circuit 304 is empty.
2, in the case of DMA transfer, the control bus 203 is controlled (1t-) to acquire bus mastership according to the general-purpose microprocessor, and the bus mastership of the control bus 203, data bus 206, and address bus 207 is acquired from the general-purpose microprocessor 204. Bus control signal generation circuit 2
02 also requests the address generation circuit 208 to generate an input address to the outside of the functional block using the general-purpose control signal IA, and the address generation circuit 208 sets the address in the external address buffer 209. After acquiring the bus right, the bus control signal generation circuit 202 inputs data from the memory 210 using the DMA transfer method.
A memory read control signal corresponding to the type of general-purpose microprocessor is output to 03, and general-purpose control signals AO and DI are output to the data transfer circuit 304 and external address buffer 209 at timings corresponding to the type of general-purpose microprocessor. and outputs the address to the address bus 207, and transfers the address from the data bus 206 to the data transfer circuit 30.
4 to input data.

In addition, when writing control information to the control register 211 so that a functional block is controlled by in-home equipment, when the general-purpose microprocessor 204 outputs the control information to the data bus 206, the bus control signal conversion circuit 205 converts the general-purpose The output control signal of the microprocessor 204 is converted into a general-purpose control signal DI according to the type of general-purpose microprocessor and then output to the control register 211, and the control register 211 receives control information from the data bus 206.

With this configuration, the same data transfer function unit can be shared by multiple general-purpose microprocessor types and data transfer methods, and the internal bus interface circuit can also be used for new types of general-purpose microprocessors. This problem can be solved by simply adding or changing the bus control signal conversion circuit and bus control signal generation circuit.

Furthermore, even when setting control information in addition to data transfer from a general-purpose microprocessor, the bus control signal conversion circuit can be shared between the data transfer function section and the control register, making it possible to suppress an increase in hardware size. .

FIG. 3 is a diagram illustrating a third embodiment of the present invention,
400 is a microprocessor interface circuit according to this embodiment, 401 is a memory in a functional block, 402
is a bus control signal generation circuit.

403 is an address generation circuit, 404 is an internal address buffer, 405 is an address bus inside the functional block, 4
06 is a data transfer circuit.

(1) In the case of I10 transfer When accessing by input/output instructions of the general-purpose microprocessor from outside the functional block (■10 transfer), the operation is explained. To output data from one functional block, the microprocessor 301 must After setting the data to be output to the outside of one functional block in the memory 401, the bus control signal generation circuit 4 passes through the control bus 303.
02 to request data transfer. Upon receiving the data transfer request, the bus control signal generation circuit 402 uses signal A1 to request the address generation circuit 403 to generate an address for transferring data from the memory 401. Set the address to . The bus control signal generation circuit 402 also connects the microprocessor 301 through the control bus 303.
A control signal for acquiring bus mastership is output to data bus 3.
02, control bus 303. After acquiring the bus right of the address bus 405, a control signal for outputting to the memory is output to the control bus 303, and the address of the transfer data is output to the address bus 405 using the signal A3 to control data from the memory 401. bus 30
Output to 3.

The bus control signal generation circuit 402 includes a data transfer circuit 406
It simultaneously controls the data output to the control bus 303 and inputs the data to the data transfer circuit 406. The data transfer circuit 406 notifies the bus control signal generation circuit 402 through RQO that there is data to be output from the functional block. Bus control signal generation circuit 40 that receives and receives RQO
2, in the case of I10 transfer, sends an output request interrupt to the control bus 203, and sends an output request interrupt to the general-purpose microprocessor 204.
Wait for input operation. When the general-purpose microprocessor 204 receives an output request interrupt from the bus control signal generation circuit 402, it puts a read control signal on the control bus 203. The bus control signal conversion circuit 205 converts the control signal input from the control bus 203 into a general-purpose control signal DO inside the functional module in accordance with the type of general-purpose microprocessor, and then outputs it to the data transfer circuit 406.

Data transfer circuit 406 outputs data to data bus 206 in accordance with the general-purpose control signal. Data output to data bus 206 is received by general-purpose microprocessor 204. Conversely, when the general-purpose microprocessor 204 outputs data, the bus control signal conversion circuit 205 converts the output control signal input from the control bus 203 into a general-purpose control signal DI corresponding to the type of general-purpose microprocessor, and then the data transfer circuit 406 The data transfer circuit 406 receives the data from the data bus 206. The data transfer circuit 406 notifies the bus control signal generation circuit 402 with the signal RQ2 that there is data fetched from outside the functional block, and the bus control signal generation circuit 402 sends the memory 40 to the address generation circuit 403 with the signal A2.
Request generation of an address for data transfer to 1,
The address generation circuit 403 is an internal address buffer 40
Set the address to 4. Bus control signal generation circuit 40
2 also outputs a bus mask right acquisition control signal to the microprocessor 301 via the control bus 303, and the data buses 302. Control bus 303. After acquiring the bus right to the address bus 405, it outputs a control signal for inputting to the memory to the control bus 303, and outputs the address of the transfer data to the internal address buffer 404 using the signal A3. The bus control signal generation circuit 402 also controls the data transfer circuit 406 to output data to the data bus 302 and input data to the memory 401 via the data bus 302. After the data transfer circuit 406 outputs the data input from the outside of the two functional blocks to the memory 401, it notifies the bus control signal generation circuit 402 of the completion of processing using the general-purpose control signal RQI, and then outputs the data input from outside the two functional blocks to the memory 401.
The bus control signal generation circuit 402 which received the data write ready interrupt sends a data write ready interrupt to the general-purpose microprocessor 204 via the control bus 203.

(2) In the case of DMA transfer When the functional block acts as a bus master and performs DMA transfer to the outside of the functional block, the operation is explained as follows: The microprocessor 301 sets data to be output to the outside of the functional block in the memory 401. After that, a request is made to the bus control signal generation circuit 402 via the control bus 303 to transfer data. Upon receiving the data transfer request, the bus control signal generation circuit 402 uses the signal AI to request the address generation circuit 403 to generate an address for data transfer from the memory 401.
3 sets an address in internal address buffer 404. The bus control signal generation circuit 402 also outputs a control signal for acquiring bus mastership to the microprocessor 301 via the control bus 303, and the data bus 302.
Control bus 303. After acquiring the bus right of the address bus 405, a control signal for outputting to the memory is output to the control bus 303, and the address of the transfer data is output to the address bus 4'05 by the signal A3, so that the data is transferred from the memory 401. It is output to the control bus 303. The bus control signal generation circuit 402 also controls the data transfer circuit 406 at the same time, and inputs the data output to the data bus 302 to the data transfer circuit 406. The data transfer circuit 406 notifies the bus control signal generation circuit 402 that there is data to be output using the general-purpose control signal RQO, and the bus control signal generation circuit 402 receives the RQO.
In the case of DMA transfer, the control bus 203 sends a control signal for acquiring bus mastership according to the general-purpose microprocessor to the control bus 203. Data bus 206.
Bus ownership of address bus 207 is acquired from general-purpose microprocessor 204. The bus control signal generation circuit 402 also requests the address generation circuit 403 to generate a cutting edge address outside the functional block using the general-purpose control signal OA,
Address creation circuit 403 is external address buffer 209
Set the address to . Bus control signal generation circuit 402
After acquiring bus rights.

In order to output data to the memory 210 using the DMA transfer method, a memory write control signal corresponding to the type of general-purpose microprocessor is output to the control bus 203, and the data transfer circuit 406 and external address buffer 20
General-purpose control signals DO and AO are output to the general-purpose micro 10 setter 9 and 9 at timings corresponding to the type of the general-purpose micro 10 setter, and data and addresses are output to the data bus 206 and the address bus 207. When inputting from the memory 210 using the DMA transfer method, the bus control signal generation circuit 402, which learns from RQI that the input bus of the data transfer circuit 406 is empty, sends an input signal to the control bus 203 according to the general-purpose microprocessor in the case of DMA transfer. The control signal for acquiring bus mastership is raised, and the control bus 203. data bus 2
06. Bus ownership of address bus 207 is acquired from general-purpose microprocessor 204. Bus control signal generation circuit 40
2 also requests the address generation circuit 403 to generate an input address to the outside of the functional block using the general-purpose control signal ■A, and the address generation circuit 403 uses the external address buffer 2
Add the address to 09. Bus control signal generation circuit 4
02 uses the control bus 20 to input data from the memory 210 using the DMA transfer method after acquiring the bus right.
3 outputs a memory read control signal corresponding to the type of general-purpose microprocessor, and outputs general-purpose control signals AO and DI to the data transfer circuit 406 and external address buffer 209 at a timing corresponding to the type of general-purpose microprocessor. The address is output to the address bus 207, and data is input from the data bus 206 to the data transfer circuit 406.

In addition, when writing control information to the control register 211 so that the functional block is controlled by in-house equipment, when the general-purpose microprocessor 204 outputs the control information to the data bus 206, the bus control signal conversion circuit 205 inputs the control information from the control bus 203. The output control signal of the general-purpose microprocessor 204
The signal is converted into a general-purpose control signal DI in accordance with the type of signal and output to the control register 211, and the control register 211 receives the control information from the data bus 206.

With this configuration, the same data transfer function unit can be shared by multiple general-purpose microprocessor types and data transfer methods, and even for new types of general-purpose microprocessors, the bus interface circuit This problem can be solved by simply adding or changing the bus control signal conversion circuit and bus control signal generation circuit.

Furthermore, even when setting control information in addition to data transfer from a general-purpose microprocessor, the bus control signal conversion circuit can be shared between the data transfer function section and the control register, making it possible to suppress an increase in hardware size. .

Furthermore, since the address generator required for DMA transfer can be shared between DMA transfer inside the functional block and DMA transfer outside the functional block, it is possible to suppress the increase in hardware scale related to DMA transfer. It is.

As is clear from these descriptions, compared to the conventional technology, in the present invention, when supporting multiple types of general-purpose microprocessors and multiple data transfer methods, it is possible to Since the microprocessor compatible part is selected and used under tFII control, there is no duplication of one functional block and the hardware scale can be reduced.Also, when supporting a new general-purpose microprocessor type, the data transfer function part remains the same and the microprocessor is used. This problem can be solved by changing only the corresponding part, and there are improvements such as easy additions and changes. By following this configuration in areas other than the data transfer function section, the microprocessor support section and address generation section in the bus interface circuit can be shared, reducing the hardware scale of the nine function blocks, and furthermore, the function of the data transfer function section itself can be reduced. Additions and changes can be made independently of the microprocessor compatible section, making additions and changes easy.

(5) As described in detail, according to the present invention, the configuration of the microprocessor interface circuit can be selected depending on the type of general-purpose microprocessor and the data transfer method.
It is separated and independent into a controlled microprocessor compatible part and a data transfer function part that is independent of the type of general-purpose microphone processor and data transfer method, such as transfer of input/output data within the circuit and generation of output addresses. Because of this configuration, it is possible to reduce the hardware scale of the microprocessor bus interface circuit when supporting multiple general-purpose microprocessors, and when changing or adding functions, it is easy to implement and the hardware There are advantages such as being able to share information and suppressing the increase in hardware scale.

[Brief explanation of drawings]

FIG. 1 is a diagram explaining a first embodiment of the present invention. FIG. 2 is a diagram for explaining a second embodiment of the present invention, FIG. 3 is a diagram for explaining a third embodiment of the present invention, and FIG. 4 is a diagram for explaining an example of I10 transfer according to the conventional technology. shows. In the figure, reference numeral 200 is a microprocessor interface circuit according to this embodiment, 2o1 is a data transfer circuit, and 20
2 is a bus control signal generation circuit; 203 is a control bus of a general-purpose microprocessor to which functional blocks are connected;
204 is a general-purpose microprocessor, and 205 is a bus control signal conversion circuit. 206 is a data bus, 207 is an address bus, 208 is an address generation circuit, 209 is an external address buffer, 2
10 is a memory, 211 is a control register, 300 is a microprocessor interface circuit according to this embodiment, 3
01 is a microprocessor inside the functional block, 302
is a data bus. 303 is a control bus, 304 is a data transfer circuit,
400 is a microprocessor interface circuit according to this embodiment, 401 is a memory in a functional block, 402
403 is a bus control signal generation circuit; 403 is an address generation circuit;
404 is an internal address buffer, 405 is an address bus inside the functional block, and 406 is a data transfer circuit.

Claims (1)

[Scope of Claims] A functional block that is built into a household device to which a general-purpose microprocessor is applied to provide a function is connected to a general-purpose microprocessor bus of the household device; The microprocessor bus within the functional block that transfers data between
In the interface circuit, the timing including the bus timing that depends on the type of general-purpose microprocessor in the home equipment in which the functional block is installed is aligned, and the functional block is directly connected to the general-purpose microprocessor bus of the home equipment. , a general-purpose microprocessor compatible part that converts and creates control signals, and data retention and transfer within the functional block, DMA
Address calculation for transfer, input/output of data to the general-purpose microprocessor bus of the home equipment based on control signals output by the general-purpose microprocessor compatible unit, and data output by the general-purpose microprocessor compatible unit for DMA transfer. A type of general-purpose microprocessor for home equipment in which a functional block is incorporated, which is equipped with a data transfer function unit that performs all or part of the processing including outputting an address to the general-purpose microprocessor bus of the home equipment using control signals. Alternatively, the general-purpose microprocessor compatible section is selected and controlled according to the data transfer method, so that the same data transfer function section can be applied to multiple types of general-purpose microprocessors and multiple data transfer methods. Microprocessor bus interface circuit.