JPH07120329B2 - Bus controller - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an access method for connecting a plurality of masters and a slave (for example, a memory) to be accessed by the bus via a bus, and accessing the slaves by a virtual address from the master. .

2. Description of the Related Art FIG. 3 is a block diagram of a conventional access method of this type, in which 11 is a slave, 12 and 13 are masters, 14 is a data bus, 15 is an address bus, 16 is a bus arbitration circuit and a virtual address. Is a control unit that is combined with a memory management unit (MMU) that has the function of translating from a physical address to a physical address.

In the cycle of accessing the slave 11 from the master 12, the virtual address is sent from the master 12 to the data bus 14, this is converted to a physical address by the control unit 16 and sent to the address bus 15, and the slave 11 and the master 12 Data transfer is performed between them. Until the end of this cycle, each bus is occupied by the master 12, so the other master 13 cannot access the slaves.

Therefore, the timing diagram of the conventional access method is as follows.
As shown in the figure, there is a problem that the conversion time from the virtual address to the physical address leads to an increase in the effective access time.

The present invention has been made in view of the above problems, and an object of the present invention is to provide an access method that can substantially eliminate an increase in access time due to address translation time.

Means for Solving the Problems In order to achieve the above-mentioned object, the present invention provides a plurality of masters, slaves accessed by each master, and data for data transfer between each master and the slave. A bus, a physical address bus for transferring a physical address to the slave, and a virtual address bus for transferring a virtual address from each master,
The master receives a virtual address output from the one master to the virtual address bus, converts the virtual address into a physical address, sends the physical address to the physical address bus, releases the virtual address bus, and the master via the data bus. And while the slave is performing data transfer,
Virtual addresses from other masters are accepted and converted into physical addresses, and immediately after the data transfer between the master and the slave is completed, the converted physical addresses are sent to the physical address bus to transmit the virtual addresses. It is provided with a configuration of arbitration / conversion means for releasing the address bus.

Operation The present invention has the above-described configuration, so that the data transfer during the access cycle of one master and the address translation during the access cycle of another master temporally overlap each other.
As a result of apparently zero conversion time from the virtual address to the physical address, the effective access time by the virtual address can be significantly shortened.

Embodiment FIG. 1 is a block diagram of an access method according to an embodiment of the present invention, in which 1 is a slave (for example, memory), 2 and 3
Is a master, 4 is a data bus, 5 is a physical address bus,
6 is a virtual address bus added according to the present invention, 7 is a bus arbitration circuit and a memory management unit (MM) having a function of converting a virtual address to a physical address.
This is a control unit combined with U). In FIG. 1, all control signals other than the address and data buses are omitted.

Next, the operation when the access cycles of the master (A) 2 and the master (B) 3 are continuously executed will be described.
FIG. 2 is a timing chart in this case.

In the cycle of accessing the slave 1 from the master (A) 2 (“first cycle” in FIG. 2), the virtual address is sent from the master (A) 2 to the virtual address bus 6, and the control unit 7 The conversion from the virtual address to the physical address is executed, and when this conversion is completed, the physical address is sent to the physical address bus 5. After that, data transfer is executed between the slave 1 and the master (A) 2 through the data bus 4, and the access cycle ends.

In the access cycle of the master (A) 2, the conversion from the virtual address to the physical address is completed and the physical address is output to the physical address bus 5, and at the same time, the control unit 7 is occupied by the master (A) 2. The virtual address bus 6 is released.

Therefore, at this point, the master (B) 3 can start an access cycle (“second cycle” in FIG. 2), the virtual address is sent to the virtual address bus 6, and the address translation for the virtual address bus 6 is performed by the control unit. Executed at 7. Then, when the access cycle of the master (A) 2 ends and the data bus 4 and the physical address bus 5 are released, the physical address is sent from the control unit 7 to the physical address bus 5, and the master (B) 3 and the slave Data transfer is executed with the data bus 1 via the data bus 4. Since the control unit 7 releases the virtual address bus 6 at the same time as sending out the physical address, the master (A) 2 can start the next access cycle.

The order of accepting access from each master is determined by the bus arbitration circuit which is closely combined with the MMU in the control unit 7. Therefore, even during the data transfer in the access cycle of a certain master, the control unit 7 can determine from which master the next virtual address should be accepted.

As is clear from the above description and FIG. 2, when accessing from a plurality of masters in order, the data transfer of one master and the address conversion of other masters overlap in time, so that the conversion from the virtual address to the physical address is performed. The time is apparently zero, and the execution access time is significantly shortened.

It is obvious that the present invention can be similarly applied to a system having three or more masters and two or more slaves to shorten the effective access time.

EFFECTS OF THE INVENTION As is apparent from the above description, the present invention provides a plurality of masters, slaves accessed by the masters, and a data bus for data transfer between the masters and the slaves. A physical address bus for transferring a physical address to the slave, a virtual address bus for transferring a virtual address from each master, and a virtual address issued from the one master to the virtual address bus. This is converted to a physical address and sent to the physical address bus, the virtual address bus is released, and while the master and the slave are performing data transfer via the data bus, another master Between the master and the slave, accepting the virtual address of the Immediately after the data transfer is completed, the arbitration / translation means for sending the converted physical address to the physical address bus to release the virtual address bus is used to transfer the data during the access cycle of one master. Since the address translation during the access cycle of other masters overlaps in terms of time, the virtual address to physical address translation time apparently becomes zero, resulting in a significant reduction in the effective access time by the virtual address. Is to have.

[Brief description of drawings]

FIG. 1 is a block diagram of an access system according to an embodiment of the present invention, FIG. 2 is a timing diagram of the same embodiment, FIG. 3 is a block diagram of a conventional access system, and FIG. 4 is a timing diagram of the conventional system. Is. 1 ... Slave, 2,3 ... Master, 4 ... Data bus, 5 ... Physical address bus, 6 ... Virtual address bus, 7 ... Control unit.

Claims (1)

[Claims] 1. A plurality of masters, a slave accessed by each master, a data bus for data transfer between each master and the slave, and a physical bus for transferring a physical address to the slave. An address bus, a virtual address bus for transferring a virtual address from each of the masters, and a physical address bus that receives a virtual address issued from the one master to the virtual address bus and converts it into a physical address To the virtual address bus and release the virtual address bus, and while the master and the slave are performing data transfer via the data bus, accept virtual addresses from other masters and perform conversion to physical addresses. Converted immediately after the data transfer between the master and the slave is completed. Bus control apparatus characterized by having an arbitration-converting means for releasing said virtual address bus by sending an address to the physical address bus.