JPH01166243A - Control system for system bus - Google Patents

Abstract

PURPOSE:To improve the transfer rate of a system bus by transmitting a bus request signal to a device as long as a device of the remote side delivers a ready signal. CONSTITUTION:When a device 4 having the lowest priority degree gives the access requests to other devices 1-3, a bus arbitration control circuit 12 of the device 4 decides whether or not the ready signals are delivered to a signal line 18-1 corresponding to the devices 1-3 from the ready signal generating circuits 13-15 of the devices 1-3 respectively. If so, the request signals are sent to the devices 1-3. Then the circuit 12 decides that no bus request signal is sent to a signal line 19-1, etc., from the devices 1-3 having higher priority degrees together with no transmission of the holding signal to a signal line 20 respectively. Thus an address is delivered to a system bus 17. As a result, a device of a lower priority degree is never kept waiting until a device of a higher priority degree set at the remote side is ready. Then the system bus can be acquired and the transfer rate of the system bus is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a control method for a system bus coexisting with a plurality of devices.

[Conventional technology]

Conventionally, in this type of system bus control method, devices connected to the system bus issue a bus request signal to the system bus in order to transfer data, and when they obtain the right to use the system bus, the data transfer is performed. Even if the other device is not in a ready state and data transfer cannot be performed, the other device becomes ready and monopolizes the right to use the system bus until the data transfer is completed. .

[Problem that the invention seeks to solve]

Conventionally, as mentioned above, when obtaining the right to use the system bus by issuing a bus request signal to the system bus,
Even if the other device for data transfer is not in a ready state and cannot perform data transfer, the device monopolizes the right to use the system bus and waits for the other device to become ready. Since the system bus becomes unusable, there is a problem in that the transfer rate of the system bus deteriorates.

The present invention solves these problems, and its purpose is to improve the transfer rate of the system bus.

[Means for solving problems]

In order to solve the above-mentioned problems, the present invention provides that when a bus request signal is sent to the system bus in order to prevent a device having a lower priority of system bus usage rights from simultaneously acquiring the system bus usage rights than the own device, A plurality of devices acquire the system bus and perform data transfer with other devices via the system bus, with one condition that a bus request signal is not output from a device that has a higher priority of system bus usage rights than the device itself. In a system including a device, each device is provided with a ready signal generation circuit that outputs a ready signal indicating that the device is in a ready state to the system bus, and each device is included in the other device to which data is transferred. The bus request signal is sent out on condition that the ready signal is output from the ready signal generation circuit.

[For production]

When bus usage requests are issued simultaneously to multiple devices with different system bus usage priorities, if a ready signal is output from each data transfer partner device,
A device with a high priority for system bus usage rights sends a bus request signal, and a device with a low priority is forced to wait for acquisition of the system bus. However, if the data transfer partner device of a device with a high priority system bus right to use the system bus does not output a ready signal, the device with a high priority will not send out a bus request signal. Therefore, the device with a low priority will use the system bus. No more waiting for rights to be acquired.

〔Example〕

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, including a system bus 17 and devices Ttl-4 connected to, accessing, or being accessed from the system bus 17. . Each device 1 to 4 connected to the system bus 17 sends a signal to the system bus 17 in synchronization with the bus clock, and each has an internal control memory 5 to 8 and a bus arbitration control circuit 9 to 1.
2, and a ready signal generation circuit 13 to a ready signal generation circuit 13.

The system bus 17 includes an address bus and a data bus.

In addition to the control bus, there are signal lines 18-1 to 18-4 to which ready signals output from ready signal generation circuits 13 to 16 in each device 1 to 4 are added, and signal lines 18-1 to 18-4 to which ready signals are output from bus arbitration control circuits 9 to 11. Signal line 1 to which the bus request signal is added
9-1 to 19-3, and a signal line 20 to which hold signals output from bus arbitration control circuits 9 to 12 are applied. Furthermore, the priority of the right to use the system bus is determined in advance for each device 1 to 4, and in this embodiment, it is assumed that device 1>device a2>device 3>device 4.

When a data transfer request to other devices 2 to 4 occurs, device 1 with the highest priority among devices 1 to 4 determines whether a ready signal is output to the signal line 18-1 corresponding to the other device to which data is to be transferred. When the bus arbitration control circuit 9 determines that the ready signal is being output, the bus arbitration control circuit 9 outputs a bus request signal synchronized with the bus clock 7 to the signal line 19-1. The bus arbitration control circuit 9 determines whether the hold signal (No. 3) is output to the signal line 20. If the bus arbitration control circuit 9 determines that the hold signal is not output to the signal line 20, In the next bus clock cycle after outputting the has request signal, the address is output to the system bus 17 in synchronization with the bus clock, and if it is determined that the hold signal is output, the hold (No. 3 It waits until the hold signal is no longer output, and outputs the address to the system bus 17 in synchronization with the bus clock in the next bus clock cycle after the bus clock cycle in which the hold signal is no longer output.

If the above-mentioned partner device is unable to complete the data transfer of the predetermined number of bytes in l bus clock cycles after device 1 outputs the address and requires N bus clock cycles, device 1 transfers the data to system bus 17. For (N-1) hash clock cycles after the address is output,
A hold signal is output to the signal line 20.

When the hold signal is not output from the partner device, the device 1 transfers 1-byte data in the next bus clock cycle after outputting the address.

Additionally, when a hold signal is output from the partner device, the address is held until the hold signal is no longer output, and the hold signal is no longer output.
Performs data transfer of byte data. Note that when transferring data of multiple bytes, the above-described process is repeated.

Also, the device 2 with the second and third highest priority,
3, when a data transfer request to another device occurs, the bus arbitration control circuit 10.11 determines whether or not a ready signal is output to the signal vA18-i corresponding to the other device to which data is to be transferred; By determining that the signal is being output, a bus request signal synchronized with the bus clock is output from the bus arbitration control circuit 10.11 to the signal lines 19-2 and 19-3, and further to the bus arbitration control circuit 10.11. A determination is made as to whether a bus request signal is being outputted to the signal line 19-j from 'AW, which has a higher priority than the own device 2.3, and a determination is made as to whether a hold signal is being outputted to the signal line 20. and,
If it is determined that a bus request signal is not output from a device with a higher priority than the own device 2.3, and a hold signal is not output to the signal line 20, the next bus clock that outputs the bus request signal The address is output to the system bus 17 in synchronization with the bus clock in each cycle.

In addition, if it is determined that both the bus request signal and the hold signal from the high-priority device are being output, or if it is determined that only the bus request signal from the high-priority device is being output, the following processing is performed.

That is, it is determined whether a hold signal has been output in the second bus clock cycle after the bus request signal from the high priority device is no longer output, and if it is determined that the hold signal has not been output, the high priority device The address is output in the second bus clock cycle after the bus request signal is no longer output, and if it is determined that the hold signal has been output, the bus request signal is sent from the priority visiting device until the hold signal is no longer output. is output. If it is determined that a bus request signal has not been output from a device with a higher priority until the hold signal is no longer output, the address is output in the next hash clock cycle after the bus crofter cycle in which the hold signal is no longer output. If it is determined that a bus request signal has been output from a device with a high priority, it is determined whether a hold signal has been output in the second bus clock cycle after the bus request signal is no longer output, and based on the determination result, the above-mentioned process is performed. Perform the same processing as above.

Furthermore, if it is determined that only the hold signal is being output, the following processing is performed. In other words, it is determined whether or not a bus request signal has been output from a device with a high priority until the hold signal is no longer output, and if it is determined that the bus request signal has not been output, the bus request signal from which the hold signal is no longer output is determined. If the address is output in the next bus cycle after the bus cycle, and it is determined that the address has been output, it is the same as when it is determined that the hold signal and the has request signal from the high-priority device are output. processing is performed.

By outputting the address from g12.3 to the system bus 17, the other device performs the same processing as described above, and devices 2 and 3 perform the same processing as described above depending on whether or not the hold signal is output from the other device. Process.

Furthermore, when a data transfer request to another device occurs, the device 1 to 4 with the lowest priority among the devices 1 to 4 sends a signal corresponding to the other device to the bus arbitration control circuit 12 to transfer data! 18-i determines whether or not a ready signal is being output, and when it is determined that a ready signal is being output, the bus arbitration control circuit 12 causes the signal line 19 to be routed from a device with a higher priority than the self-mounted surface 4. −j
The bus request signal is output to the signal line 20, and the hold signal is output to the signal line 20. Based on the determination result, device 4 performs the same processing as device 2.3 described above, and outputs an address to the system bus.

By outputting the address from Hrr4 to the system bus 17, the other device performs the same process as described above, and the device 2.3 performs the same process as described above depending on whether or not the hold signal is output from the other device. Let's do it.

Now, for example, an access request from the device 1 to the internal control memory I77 of the device 3 and an access request from the device 2 to the internal control memory 8 of the device 4 occur simultaneously at time t1 (see FIG. 2). , it is assumed that a ready signal is output to the signal lines 1B-3 and 18-4 corresponding to device 3.4. However, in this case, it is assumed that each device can transfer 1-byte data in one bus crofter cycle after the address is output, and that no hold signal is output to the signal line 20.

When an access request occurs at time ti, the device 1 sends a signal fi18-3 corresponding to the partner device 3 to which data is to be transferred.
The bus arbitration control circuit 9 determines whether or not a ready signal is output to the device 2, and the device 2 determines whether or not a ready signal is output to the signal line 18-4 corresponding to the partner device 4 to which data is to be transferred. The arbitration control circuit 10 is made to make the determination.

In this case, signal line 18-3.18-4 corresponding to device 3.4
Since the ready signal is output to the bus arbitration system<Tj circuits 9 and 10, the devices 1.2 and 1.2 connect the signal line 19 from the bus arbitration system<Tj circuits 9 and 10 at time t2, respectively, as shown in FIG. 2 (bl, fcl).
-1 and 19-2 to output a bus request signal.

This bus request signal is transmitted to the bus controller 7 shown in ta)
It is synchronized with the

When the system ml outputs a bus request signal to the signal line 19-1 at time t2, it sends addresses A, A, and A to the system bus 17 in the next bus clock cycle (time t3), as shown in FIG. 2 (dl). is output, and in the next bus cycle (time t4), as shown in fe+ in the figure,
The data Dlff is transferred to and from the device 3.

Furthermore, when the device 2 outputs a bus request signal to the signal line 19-2 at time (2), the bus arbitration control circuit 1O receives a bus request signal from the device 1, which has a higher priority than the device 2, to the signal line 19-1. is being outputted and whether a hold signal is being outputted to the signal line 20. In this case, since the bus request signal is being output from the device 1, the device 2 is connected to the device l.
Wait until the bus request signal is no longer output from
As shown in +dl in the figure, at time t4, the address A of the other device is output to the system bus 17, and in the next bus clock cycle (time t5), as shown in tel in the figure, the address A of the other device is output to the system bus 17. The data DI is transferred between the 4 and 4.

In this way, if data transfer requests are generated from multiple devices to other devices at the same time, and if a ready signal is output from each partner device to which data is to be transferred at that time, data transfer is performed in order from the device with the highest priority. .

If multiple devices simultaneously issue data transfer requests to other devices, and at that time, the destination device T1 outputs a ready signal, data transfer will be performed in order from the device with the highest priority, but if the destination device is rare 418 If no code is output, the following processing is performed.

Now, for example, if an access request from the device 1 to the internal control memory 7 of the device 3 and an access request to the internal memory 8 of the device 2 or the device 4 occur simultaneously at time tll (see FIG. 3), then As shown in the figure (dl), it is assumed that the ready signal generation circuit 15 in the device 3 has not outputted the ready signal to the signal line 18-3.However, the ready signal generation circuit 16 in the other device 4 does not output the ready signal to the signal line 18-3. Data transfer of 1 byte data is completed in 1 bus clock cycle after the address is output, and signal line 2
It is assumed that no hold signal is output to 0.

When an access request occurs at time tll, device l
is the signal line 18-3 corresponding to the partner device 3 that performs data transfer.
The bus arbitration control circuit 9 determines whether a ready signal is output to the device 2, and the device 2 performs bus arbitration to determine whether a ready signal is output to the 1ε line 18-4 corresponding to the partner device 4 to which data is to be transferred. Let the control circuit IO make the determination.

In this case, the ready signal is not output to the signal line 18-3 corresponding to device 3, and the ready signal is output to the signal line 18-4 corresponding to device 4.
Waiting for the ready signal to be output at time t12, the device 2 causes the bus arbitration control circuit 10 to output a bus request signal to the signal line 19-2 as shown in FIG. 3 fcl at time t12. This bus request (No. 8) is synchronized with the bus clock shown in ta+ in the figure.

When the device 2 outputs the bus request signal to the signal line 19-2, the device 2 sends the self-installed r! signal to the bus arbitration control circuit 10. 1.2 It is determined whether or not a bus request signal is outputted to the signal line 19-1 from the device l having a higher priority than 1.2, and it is determined whether or not a hold signal is outputted to the signal line 20. In this case, since device 1 is not outputting a bus request signal and no hold signal is being output to signal line 20, device 2 is not outputting a bus request signal at time t13.
As shown in FIG. 1, the address A4 is output to the system bus 17, and in the next bus clock cycle (time t14'I), the data [)za data transfer.

Further, when the ready signal is output from the partner device 3 at time t13, the device 1 transmits the bus request signal to the signal 4119-1 as shown in FIG. 3 (bl) in synchronization with the bus clock shown in FIG. When the device 1 outputs the bus request signal, the device 1 sends the signal vA to the bus arbitration control circuit 9.
20 to determine whether or not a hold signal is output. In this case, the hold signal is not output, so
At time 114, as shown in FIG.
The address A3 is output to the system bus 17, and data Dlff is transferred to and from the device 3 in the next bus clock cycle (time [15), as shown in parentheses in the figure.

In this way, even if an access request occurs to the high priority device 1 and the low priority device 2 at the same time, if the partner device 3 of the high priority device 1 does not output a ready signal, the low priority device RA
2 is given the right to use the system bus, the transfer rate of the system bus can be made high.

The above explanation is for the case where each device can complete the data transfer of 1-byte data in one bus clock cycle after the address is output, and no hold signal is output to the signal line 20. When there is V2'1 in which the transfer cannot be completed within one hash clock cycle after the address is output, and a hold signal is output to the signal line 20, the operation is as follows.

Now, for example, if two bus cycles are required after outputting the address to transfer 1 byte data between device 1 and device 3, the internal control memory of device 1 to device 3 7 and the access request for device 2
Assume that an access request to the internal control memory 8 of the device 4 occurs simultaneously at time t21 (see FIG. 4). However, in this case, it is assumed that ready signals are output to the signal lines 18-3 and 18-4.

When an access request occurs at time t21, device 1
is the signal line 18-3 corresponding to the partner device 3 that performs data transfer.
The bus arbitration control circuit 9 determines whether a ready signal is output to the device 2, and the device 2 determines whether a ready signal is output to the signal line 18-4 corresponding to the partner device 4 to which data is to be transferred. The control circuit 10 is made to make the determination.

In this case, signal line 18-3.18-4 corresponding to device 3.4
Since the ready signal has been output to the bus arbitration control circuits 9 and 10, the devices 1.2 and 1.2 connect the signal lines 19- and 19-2 from the bus arbitration control circuits 9 and 10 at time t22, respectively, as shown in FIG.
1.19-2 outputs a bus request signal. This bus request signal is synchronized with the bus clock shown at ta+ in the figure.

At time t22, the device 1 outputs a bus request signal to the ε branch line 19-■, and in the next hash clock cycle (time L23), it sends the address A to the system bus 17 as shown in +d+ in FIG. , outputs.

As mentioned above, the destination device 3 requires two bus cycles after the address is output for data transfer of one hide data. A hold signal is output on signal line 20 during the cycle. The device engineer outputs the address A until the hold signal is no longer output, and when the hold signal is no longer output, data DI3 is transferred to and from the device 3 as shown in iC1 in the figure. Further, when the device 2 outputs a bus request signal to the signal line 19-2 at time t22, the bus arbitration control circuit 1
0 to determine whether a bus request signal is being output to the signal line 19-1 from the device 1, which has a higher priority than its own device 2, and to determine whether a hold signal is being output to the signal line 20. . In this case, time t22
Since the bus request signal from the device 1 is outputted between t23 and t23, and the hold signal is outputted between the times t24 and t25, the device 2 outputs the bus request signal at time t25 as shown in the figure (dl). The address A4 of the partner device 4 is output, and in the next bus clock cycle (time t26), the data [
In data transfer is performed.

〔Effect of the invention〕

As explained above, the present invention provides a ready signal generation circuit that outputs a ready signal indicating that the own device is in a ready state to each device that accesses the system bus or is accessed from the system bus, and When a request occurs, the bus request signal cannot be output unless the ready signal generation circuit in the other device to which the data is transferred has output the ready signal, and the bus request signal cannot be output at the same time to the device with a high priority and the device with a low priority. When a bus use request occurs, even if the device has a high priority, it cannot output a bus request signal unless the ready signal generation circuit in the other device for data transfer has output a ready signal, and the device with a low priority cannot output a bus request signal. Since devices can preferentially access the system bus, the system bus transfer rate can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIGS. 2 to 4 are explanatory diagrams of the operation of FIG. 1. In the figure, 1-4...device, 5-8...internal control memory, 9-12... lotus arbitration control circuit, 13-16
... Ready signal generation circuit, 17 ... System bus, 1
8-1 to 18-4.19-1 to 19-3.20...Signal line.

Claims (1)

[Scope of Claims] When a bus request signal is sent to the system bus in order to prevent a device having a lower priority of the system bus usage right from acquiring the system bus usage right at the same time, the own device receives the system bus usage right from the own device. In a system including a plurality of devices that acquire the system bus and perform data transfer with other devices via the system bus, each Each device is provided with a ready signal generation circuit that outputs a ready signal indicating that it is in a ready state to the system bus, and each device receives a ready signal from the ready signal generation circuit included in the other device with which data is to be transferred. A system bus control method, characterized in that the bus request signal is sent on condition that the bus request signal is output.