JPH01166242A - Control system for system bus - Google Patents

Abstract

PURPOSE:To improve the transfer rate of a system bus by transmitting a bus request signal as long as no busy signal is received from a data transfer device set at the remote side. CONSTITUTION:A device 1 having the highest priority decides via a bus arbitration control circuit 9 whether or not a busy signal via a signal line corresponding to a device of the remote side which transfers data to other devices 2-4 at generation of a data transfer request. If not, a bus request signal synchronizing with a bus clock is delivered to a signal line 19-1 from the circuit 9. At the same time, the presence or absence is decided by the circuit 9 for the holding signal sent to a signal line 20 and an address is delivered to a system bus 17 in the next bus clock period having no output. The devices 2-4 having lower priority degrees decide via the bus arbitration control circuits 10-12 whether a bus request signal is delivered from the device 1 or not. Then the devices 2-4 deliver the request signals in the same way. Thus the bus 17 is never occupied nor held even in a busy mode. As a result, the transfer rate of the bus 17 is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a control method for a system bus shared by a plurality of vtWl's.

[Conventional technology]

Conventionally, in this type of system bus control method, devices connected to the system bus issue a bus request signal to the system bus in order to transfer data, and when they obtain the right to use the system bus, the data transfer is performed. Even if the other device is in a busy state and data cannot be transferred, the other device becomes ready and monopolizes the right to use the system bus until the data transfer is completed. There is.

[Problem that the invention seeks to solve]

Conventionally, as mentioned above, when obtaining the right to use the system bus by issuing a bus request signal to the system bus,
Even if the other device for data transfer is in a busy state and cannot perform data transfer, it will monopolize the right to use the system bus and wait for the other device to become ready. Since the device is unable to use the system bus, there is a problem in that the transfer rate of the system bus deteriorates.

The present invention solves these problems, and its purpose is to improve the transfer rate of the system bus.

c. Means for Solving Problems] In order to solve the above-mentioned problems, the present invention provides a system for preventing simultaneous acquisition of system bus usage rights for devices having a lower priority for system bus usage rights than the own device. When a bus request signal is sent to the bus, one condition is that the bus request signal is not output from a device with a higher priority of system bus usage rights than the own device, and the system bus is acquired and other devices are sent via the system bus. In a system including a plurality of devices that perform data transfer with a device, each device is provided with a busy signal generation circuit that outputs a busy signal indicating that the device is busy to the system bus, and each device , the bus request signal is sent out on the condition that no busy signal is issued from a busy signal generation circuit included in the partner device to which data is transferred.

[For production]

When bus usage requests occur simultaneously to multiple devices with different priorities for system bus usage rights, if the busy signal is not output from each data transfer partner device, the device with the higher priority for system bus usage rights will send a bus request signal. , and devices with lower priority are forced to wait to acquire the system bus. However, if the data transfer partner device of a device with a high priority system bus usage right is sending out a busy signal, the device with a high priority will not send a bus request signal. Therefore, low-priority devices are not forced to wait for the right to use the system bus.

〔Example〕

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, including a system bus 17 and devices 1-4 connected to, accessing, or accessed from the system bus 17. . System bus 1
Each of the devices 1 to 4 connected to the bus controller 7 sends a signal to the system bus 17 in synchronization with the bus clock, and each has an internal control memory 5 to 8 and a bus arbitration control circuit 9 to 12.
and busy signal generation circuits 13 to 16 that output a busy signal while internal access is being performed.

The system bus 17 includes an address bus and a data bus.

In addition to the control bus, there are signal lines 18-1 to 18-4 to which busy signals output from the busy signal generation circuits 13 to 16 in each device 1 to 4 are added, and signal lines 18-1 to 18-4 to which busy signals output from the bus arbitration control circuits 9 to 11 are applied. Signal line 1 to which the bus request signal is applied
9-1 to 19-3, and a signal i%I20 to which a hold signal output from the bus arbitration control circuits 9 to 12 is added. Furthermore, the priority of the right to use the system bus is determined in advance for each of the devices t to 4, and in this embodiment, it is assumed that the priority is device 1>device 2>device 3>device 4.

! Among It1 to It4, the device Wl with the highest priority requests data transfer to other devices W2 to W4,
The bus arbitration control circuit 9 determines whether a busy signal is output to the signal line 18-i corresponding to the other device to which data is transferred.
When it is determined that the busy signal is not output, the bus arbitration control circuit 9 outputs a bus request signal synchronized with the bus clock to the signal line 19-1, and a hold signal is output to the signal line 20. The bus arbitration control circuit 9 is made to determine whether the If the bus arbitration control circuit 9 determines that the hold signal is not output to the signal line 20, the system bus 17 synchronizes the address with the bus clock cycle in the next bus clock cycle after outputting the bus request signal. If it is determined that Hall No. 113 is being output, wait until the hold signal is no longer output, and then output the address in the next bus clock cycle after the bus clock cycle in which the hold signal is no longer output. System bus 17 in synchronization with the bus clock. Output to.

If the above-mentioned partner device is unable to complete the data transfer of the predetermined number of bytes in one bus clock cycle after device 1 outputs the address and requires N bus clock cycles, device 1 transfers the data to system bus 17. For (N-1) bus clock cycles after the address is output,
A hold signal is output to the signal line 20.

When the hold signal is not output from the partner device, the device 1 transfers 1-byte data in the next bus clock cycle after outputting the address.

Additionally, when a hold signal is output from the partner device, the address is held until the hold signal is no longer output, and the hold signal is no longer output.
When transferring data of byte data, and when transferring data of multiple bytes, the above-described process is repeated.

Also, the device 2 with the second and third highest priority,
3, when a data transfer request to another device occurs, the bus arbitration control circuit 10.11 determines whether a busy signal is output to the signal line 18-1 corresponding to the other device to which the data is transferred, and outputs the busy signal. is not output, the bus request signal synchronized with the bus clock is sent from the bus sub-control circuit 10.11 to the signal line 1.
9-2.19-3, and further bus arbitration control circuit 1
At 0.11, it is determined whether a bus request signal is output to the signal line 19-j from a device with a higher priority than the own device 2.3, and whether a hold signal is output to the signal line 20. Let them do it. If it is determined that a bus request signal is not output from a device with a higher priority than the own device 2.3, and a hold signal is not output to the signal line 20, the next device that outputs the bus request signal The system bus 17 synchronizes the address with the bus crofter during the bus clock cycle.
Output to.

In addition, if it is determined that both the bus request signal and the hold signal from the high-priority device are being output, or if it is determined that only the bus request signal from the high-priority device is being output, the following processing is performed.

That is, it is determined whether a hold signal has been output in the second bus clock cycle after the bus request signal from the high priority device is no longer output, and if it is determined that the hold signal has not been output, the high priority device The address is output in the second bus clock cycle after the bus request signal is no longer output, and if it is determined that the hold signal has been output, the bus request signal is sent from the device with higher priority until the hold signal is no longer output. is output. If it is determined that the bus request signal has not been output from the high-priority VW until the hold signal is no longer output, the address is output in the next bus clock cycle after the bus clock cycle in which the hold signal is no longer output, and the bus request signal is output from the VW with a higher priority. If it is determined that a bus request signal has been output from a device with a high priority, it is determined whether a hold signal has been output in the second bus clock cycle after the bus request signal is no longer output, and based on the determination result, the above-mentioned process is performed. Perform the same processing as above.

Furthermore, if it is determined that only the hold signal is being output, the following process is performed: ml! II. Until the hold signal is no longer output, it is determined whether a bus request signal has been output from a device with a high priority, and if it is determined that the bus request signal has not been output, the hold signal is no longer output. The address is output in the bus block cycle following the bus block cycle, and if it is determined that the address has been output, it is determined that the above-mentioned hold signal and bus request No. 18 from a device with a high priority have been output. The same processing is performed.

By outputting the address from VtW2.3 to the system bus 17, the other device performs the same process as described above, and the device! 2. 3 performs the same processing as described above depending on whether or not a hold signal is output from the partner device.

Also, among devices 1 to 4, the device W with the lowest priority
t4 is another! When a data transfer request for location a occurs, the bus arbitration control circuit 12 determines whether or not a busy signal is being output to the signal line 18-1 corresponding to the destination device to which the data is to be transferred, and determines whether the busy signal is being output. As a result, the bus arbitration control circuit 12
A determination is made as to whether or not a bus request signal is being outputted to the signal *19-j from a device with a higher priority, and a determination is made as to whether or not a hold signal is being outputted to the signal line 20'. Then, based on the determination result, the device W14 performs the same processing as the device 2.3 described above, and outputs an address to the system bus.

Device i! By outputting the address from 4 to the system bus 17, the other device VTFF performs the same process as described above, and the device 2.3 performs the same process as described above depending on whether or not the hold signal is output from the other device. Let's do it.

Now, for example, if an access request from the device 1 to the internal control memory 7 of the device 3 and an access request from the device 2 to the internal control memory 8 of the device Wi 4 occur simultaneously at time t1 (see FIG. 2), then, Assume that no busy signal is output to the signal lines 18-3 and 18-4 compatible with the device FF3.4. However, in this case, it is assumed that each device can transfer 1-byte data in one bus clock cycle after the address is output, and that no hold signal is output to the signal line 20.

When an access request occurs at time t1, device 1 causes bus arbitration control circuit 9 to determine whether a busy signal is output to signal M18-3 corresponding to partner device 3 to which data is to be transferred, and device 2 Partner device 4 for data transfer
The bus arbitration control circuit 10 is caused to determine whether a busy signal is output to the corresponding signal line 18-4.

In the case of Kono, signal vA18-3.18- corresponding to device 3.4
Since no busy signal is output to device 4, device 1.2
As shown in FIG. 2 (bl, (C1) at time t2, the signal line 19
-1 and 19-2 to output a bus request signal.

This bus request signal is synchronized with the bus clock shown in ia+ in the figure.

When the vt device outputs a bus request signal to the signal line 19-1 at time t2, it starts the next bus clock cycle (
At time [3], address A is output to the system bus 17 as shown in Figure 2+dl, and in the next bus clock cycle (time t4), the device 3, and when the device 2 outputs a bus request signal to the signal line 19-2 at time t2, the bus arbitration control circuit 10
Then, a determination is made as to whether a bus request signal is being outputted to the signal line 19-1 from the device 1 having a higher priority than the own device 2, and a determination is made as to whether a hold signal is being outputted to the signal line 20. In this case, since the bus request signal is being output from the device 1, the device 2 waits until the bus request signal is no longer output from the device 1, and as shown in FIG. Address A4 is output to the system bus 17, and in the next bus clock cycle (time t5), as shown in FIG.
As shown in , data D! is exchanged with the partner device 4. 4 data transfer is performed.

In this way, if data transfer requests are issued from multiple devices to other devices at the same time, and if a busy signal is not output from each partner device to which data is to be transferred at that time, data transfer is performed in order from the device with the highest priority. .

plural! If a data transfer request is made to another device at the same time from the J device, and the other device does not output a busy signal at that time, data transfer will be performed from the device with higher priority, but the other device will output a busy signal. If so, the following processing is performed.

Now, for example, from device 1 to r! 13 internal control memo I7
7 and an access request from the device 2 to the internal memory 8 of the device 4 occur simultaneously at time tll (see FIG. 3), and at that time, as shown in FIG. Assume that the busy signal generating circuit 15 of 1 is outputting a busy signal to the signal line 1-3. However, the busy signal generation circuit 13.14.1 of other devices 1 and 2.4
6 does not output a busy signal, the data transfer of 1-byte data ends in an ebus block cycle after the address is output, and no hold signal is output to the signal line 20.

When an access request occurs at time tll, device l
is the signal line 18-3 corresponding to the partner device 3 that performs data transfer.
The bus arbitration control circuit 9 determines whether or not a busy signal is output to the device 2, and the device 2 sends a signal corresponding to the partner device 4 to which data is to be transferred! The bus arbitration control circuit 10 is caused to determine whether a busy signal is output to 1B-4.

In this case, a busy signal is output to the signal line 18-3 corresponding to device 3, and no busy signal is output to the signal line 18-4 corresponding to device 4, so device l
Wait until the busy signal is no longer output to device 2.
At time t12, as shown in FIG. 3+c+, the bus arbitration control circuit 10 outputs a bus request signal to the signal line 19-2. This bus request signal is shown in the same figure (+
It is synchronized with the bus clock shown in 1).

When the device 2 outputs a bus request signal to the signal line 19-2, the bus arbitration control circuit 10 determines whether a bus request signal is being output to the signal line 19-1 from the device 1, which has a higher priority than the device 2. and whether or not a hold signal is being output to the signal line 20. In this case, since the device 1 is not outputting the bus request signal and the hold signal is not being output to the signal line 20, the device 2 is connected to the system bus 17 at time L13 as shown in FIG. Output address A4 to
In the next bus cycle (time t14), data D!
data transfer.

Further, when the busy number 43 is no longer output from the partner device 3 at time t13, the device 1 transmits the bus request signal to the signal 119 as shown in FIG. 3 (bl) in synchronization with the bus clock shown in FIG. 3 (al). Output to -1.

When the bus request signal is output, the device 1 causes the bus arbitration control circuit 9 to determine whether a hold signal is output to the signal line 20 or not. In this case, since the hold signal is not output, the device 1 at time t14 (e
As shown in FIG. 1, address A is output to the system bus 17, and in the next bus clock cycle (time t15), data DI is sent to and from the device 3 as shown in FIG.
3 data transfer is performed.

In this way, even if access requests occur simultaneously in device 1 with a high priority and device 2 with a low priority, the partner device i of the device 1 with a high priority! If device 3 outputs a busy signal, device 2 with lower priority
Since the right to use the system bus is given to the system bus, the transfer rate of the system bus can be made high.

The above explanation is for the case where each 'ATL can complete the data transfer of 1 byte data in 1 bus cycle after the address is output and no hold signal is output to the signal line 20. There is a Vi'lZ in which the data transfer cannot be completed within an I bus clock cycle after the address is output, and when a hold signal is output to the signal line 20, the operation is as follows.

Now, for example, in order to transfer 1 byte data between device 1 and device 3, two bus clockers are required after outputting the address. 7 and the access request for device 2
Assume that requests for access to the internal control memory 8 of the device 4 occur simultaneously at time t21 (see FIG. 4). However, in this case, it is assumed that no busy signal is output to the signal lines 18-1 to 18-4.

When an access request occurs at time t21, device 1
is the signal line 18-3 corresponding to the partner device 3 that performs data transfer.
The bus arbitration control circuit 9 determines whether or not a busy signal is output to the device 2, and the device 2 determines whether or not the busy signal is output to the signal line 18-4 corresponding to the partner device 4 to which data is to be transferred. Let the control circuit IO make the determination.

In this case, signal line 18-3.18-4 corresponding to device 3.4
Since no busy signal is output to , devices 1 and 2 each operate at time t22 as shown in FIG. 4(b).

(As shown in C1, a bus request signal is output from the bus arbitration control circuits 9 and 10 to the signal lines 19-1 and 19-2. This bus request signal is synchronized with the bus clock shown in FIG. 1 (al).

When the device 1 outputs a bus request signal to the signal line 19-1 at time t22, it starts the next bus clock cycle (
At time t23), address A is output to the system bus 17 as shown in fd+ in FIG.

As mentioned above, the destination device 3 requires two bus clock cycles after the address is output to transfer 1-byte data, so as shown in tel in the figure, one bus clock cycle is required from time t24. During this period, a hold signal is output to the signal line 20. The device 1 outputs the address A until the hold signal is no longer output, and when the hold signal is no longer output, the device 1 transfers data [)+i with the device 3 as shown in FIG. Further, the device 2 connects the signal line 19-2 at time t22.
When a bus request signal is output to the bus arbitration control circuit 10, the bus arbitration control circuit 10 determines whether a bus request signal is output from the device 1 having a higher priority than the own device 2 to the signal line 19-1, and outputs a hold signal to the signal line 20. It is determined whether or not is being output. In this case, time 12
Since the bus request signal from device 1 is output from time 2 to t23, and the hold signal is output from time t24 to t25, device 2 outputs the bus request signal from time t25 as shown in fd+ in the figure. The address A4 of the partner device 4 is output, and in the next bus clock cycle (time t26), data D is exchanged with the partner device W4 as shown in ffl in the figure.
za data transfer is performed.

〔Effect of the invention〕

As described above, the present invention provides each device that accesses the system bus or is accessed from the system bus with a busy signal generation circuit that outputs a busy signal to the system bus indicating that the device itself is in a busy state. , when a request to use the bus occurs, a bus request signal is output on the condition that the busy signal generation circuit in the other device to which data is transferred is not outputting a busy signal, and the system bus is not used. Even if system bus usage requests occur simultaneously in a device with a high priority and a device with a low priority, if the busy signal generation circuit of the device with a high priority outputs a busy signal, the device with a high priority will not receive a bus request signal. Since a device that cannot output data and has a low priority can preferentially access the system bus, it has the effect of improving the bus transfer rate.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIGS. 2 to 4 are explanatory diagrams of the operation of FIG. 1. In the figure, 1-4... Device, 5-8... Internal control memory, 9-12... Bus arbitration control circuit, 13-16
... Busy signal generation circuit, 17... System bus,
18-1 to 18-4, 19-1 to 19-
3. 20...A word line. Figure 1 is an explanatory diagram of the operation. Figure 2 is an explanatory diagram of the operation in Figure 1. Figure 3 is an explanatory diagram of the operation.

Claims (1)

[Scope of Claims] When a bus request signal is sent to the system bus in order to prevent a device having a lower priority of the system bus usage right from acquiring the system bus usage right at the same time, the own device receives the system bus usage right from the own device. In a system including a plurality of devices that acquire the system bus and perform data transfer with other devices via the system bus, each Each device is provided with a busy signal generation circuit that outputs a busy signal indicating that it is in a busy state to the system bus, and each device receives the busy signal from the busy signal generation circuit included in the other device to which data is to be transferred. A system bus control method, characterized in that the bus request signal is transmitted on the condition that the bus request signal is not issued.