JPH077954B2 - Control device - Google Patents

Description

The present invention relates to a control device, and more particularly to a control device for controlling a plurality of input / output devices.

(Prior Art) Conventionally, in a control device using a microprocessor, various input / output devices are connected to a central processing unit (hereinafter referred to as CPU), the CPU checks the state of the input / output device, and the CPU turns on. Depending on the state of the output device, the data of the input / output device is read and stored in the main memory device (hereinafter abbreviated as MEM) (this is called input operation), or conversely, the data of the MEM is input / output device. The data is input / output by writing to (this is called an output operation).

In recent years, with the progress of LSI and control technology, interrupt system, direct memory access controller (hereinafter referred to as DAMC), etc. have been generally used, and CPU is involved in controlling input / output devices. The percentage of people doing it has decreased significantly.

FIG. 2 shows a conventional example in which many interrupt devices and a DMAC are used to control many input / output devices.

FIG. 2 shows an example of a conventional control device, and particularly shows a case where the serial input data from the four lines A to D are edited and stored as a telegram on the MEM.

In the figure, 1 is a CPU, 2 is a MEM, 3 is a DMAC, 4 to 7 are serial data, and are converted into parallel data.
A transmitter / receiver (hereinafter referred to as TRC) using an LSI, 12 is an OR gate.

FIG. 3 is a diagram showing an example of a processing program of the CPU of FIG.

Below, the control operation in the case of reception in FIG. 2 will be explained together with FIG.

First, when a reception request is generated, the scheduler of the CPU 1 performs reception start processing.

During the reception start, the CPU1 clears the reception message area of MEM2, and then the reception areas ma to md corresponding to the respective lines A to D.
Is assigned, the start address is instructed to the DMAC3 to enable the operation, and then the TRC4 to 7 are activated. If a received message frame is input from the A line in this state, TR
C4 is a direct memory access request (hereinafter referred to as DAM request) signal line 21 each time it receives 1-byte data.
Request transfer to DMAC3 through. When the DMAC3 recognizes this DMA request, it connects the internal bus 27 and the system bus 20 to form a path between TRC4 and MEM2, and the 1-byte data of the received data read from TRC4 is transferred to the head of the A-line receiving area ma. Transfer to address and increment address in DMAC by +1. In this way, the telegrams are sequentially stored in the reception area ma of MEM2, but the TRC4 judges that the telegram is terminated (reception of the flag F in FIG. 4 (a)) and interrupts that the reception is terminated. When the signal line 22 is turned on, notification is given by an interrupt signal.
In this case, the interrupt signal is sent to the interrupt signal line 23 through the OR gate 12.
To be notified to CPU1. Then, the CPU 1 starts the interrupt processing routine shown in FIG. The CPU 1 knows that the source of the interrupt is TRC4 and that the cause of the interrupt is due to the normal reception end, by accessing the TRCs 4 to 7 via the system bus 20 and the internal bus 27.

After this, the CPU 1 switches the buffer in preparation for the next message reception. Specifically, operation of DMAC3 is prohibited for TRC4, and the reception area ma for A line in MEM2 is changed to new area na.
Then, direct the start address to DAMC3 and set DMAC3 to TRC4.
To be able to operate again. Since TRC4 has not instructed to stop receiving, when the next message comes, it automatically receives regardless of the operation of CPU1 and transfers it to the new area na of MEM2 by the procedure described above.

On the other hand, when the CPU1 completes the buffer switching,
The received message in ma is processed by the low-level protocol that checks the transmission order number and the reception order number, and if there is no problem, the task for performing the high-level protocol processing is generated and the interrupt processing routine is executed. Exit through.
After that, the scheduler of the CPU 1 takes over this task and performs the subsequent processing. Here, the high level protocol processing means higher level processing such as packet order control.

The operation of the line A has been described above, but in reality, the operations of multiple lines are performed in parallel and asynchronously.

(Problems to be Solved by the Invention) However, the processing by the above-described conventional control device has the following problems. This will be described below with reference to FIG.

FIG. 4 is a processing time chart in FIG. In FIG. 4 (a), the synchronization method is the frame synchronization method,
The case where frame 1 and frame 2 sharing the flag “F” are continuously received is shown. The same figure (b) is shown in FIG.
This shows that the DMA request signal on the DMA request line 21 is generated with a delay of 3 bytes as shown in the figure, and the frame reception end interrupt (INT) is the end flag “F” of frame 1.
Is generated after the reception of the message, and the interrupt processing routine of FIG. 3 is started. Also, FIG. 4 (c)-
(E) shows the case where the message reception (continuous frame reception) of the type shown in (a) of the figure occurs only on line A, when three lines A to C occur simultaneously, and when four lines A to D occur simultaneously. Is a time chart of.

The processing program of CPU1 is shown in FIG.
Let T be the time until the buffer switching is completed, and t be the time until the interrupt processing routine is exited after the buffer switching is completed. Then, the time T is a preparation period (hereinafter referred to as a buffer switching time) for normally receiving the next message from the end of reception of the previous message (steps S1 and S2), and this buffer switching process is performed. If the next message is received before the completion, the next message cannot be received normally, so it must be processed promptly. If the buffer switching process is delayed, the previous message and the next message are stored consecutively in the received message area, and the message delimiter is not known. It ends up (wrong message length to be processed).

On the other hand, the time of t is the time when the next message can be received anytime, and it is the time required for the basic part of the protocol (hereinafter,
Basic processing time. ) (Steps S3 to S6).

The buffer switching performed at time T is activated at the normal reception end interrupt of TRC (steps S1 and S2), but the time τ until the transfer request of "A" of the next frame is generated (processing allowance). It is necessary to finish within (time) [Fig. 4 (b)].
This is because, as described above, if the next message is received before the buffer switching process is completed, the next message cannot be received normally. Note that τ becomes shorter in inverse proportion to the reception speed.

Under such a condition, the reception of the message in Fig. 4 (a) becomes TR.
When the error occurs only in the A line at C4, the relationship between the buffer switching time Ta and the basic processing time ta is as shown in FIG. Therefore, the buffer switching time Ta and the basic processing time ta are sufficiently smaller than the processing allowable time τ, and there is no problem.

Next, the reception of the message in FIG.
When the lines are generated simultaneously, the interrupt processing of each line is set to the same level as shown in FIG. 3, so that the priority is first set (the reception of the message is 4 lines of A to D by TRC4 to 7). If they occur at the same time, the priority of the interrupt is line A,
It is assumed that B, C, and D are set in this order in advance. ) High A line processing (buffer switching and basic protocol processing) is continuously performed, and interrupt requests are held for the other B and C lines. At the time when the processing of the A line is completed (at the end of the buffer switching time Ta and the basic processing time ta), the processing of the B line having a higher priority is started. The processing of the C line is performed after the processing of the B line. Therefore, the processing is performed at the timing shown in FIG. In FIG. 5D, Tb and tb are the buffer switching time and the basic processing time for the B line, respectively, and Tc and tc are the buffer switching time and the basic processing time for the C line, respectively. As can be seen from FIG. 6D, the basic processing time tc for the C line is not completed within the allowable time τ (here, 3 bytes), but it is the basic processing time as described above. No problem.

Next, when the TRCs 4 to 7 simultaneously receive the telegram shown in FIG. 7A and the interrupt signals are simultaneously generated from TRCs 4 to 7, when the TRCs 4 to 7 are used, the D lines are connected as shown in FIG. The buffer switching time Td of is not processed within the processing allowable time τ. This indicates that processing can be performed up to 3 lines A, B, and C, but processing cannot be performed in time for 4 lines.

As can be seen from the above, in the conventional interrupt processing that assigns one interrupt level for one interrupt factor of the TRC as an input / output device and sequentially performs asynchronous processing, multiple TRCs are used.
However, when interrupt requests are simultaneously generated, only a few lines (three lines in the above example) can be processed, and the processing capacity is low.

Therefore, an object of the present invention is to provide an excellent control device having high processing capability.

(Means for Solving the Problems) In a control device for executing a plurality of interrupt processes in a processing device by an interrupt signal from a transceiver provided corresponding to a plurality of input / output devices, an interrupt signal from the transceiver Is transmitted as a high level interrupt processing request signal directly to the processing device, and an interrupt signal from the transceiver is stored, and then the low level interrupt processing request signal is processed as the low level interrupt processing request signal. Low-level interrupt processing request signal transmitting means for transmitting to the device, and notifying means for notifying the processing device of the transceiver that has output the interrupt signal,
The plurality of interrupt processes in the processing device include a high level interrupt process routine corresponding to the high level interrupt process request signal and a low level interrupt process routine corresponding to the low level interrupt process request signal. The high-level interrupt processing routine executes the interrupt processing with a high degree of urgency among the plurality of interrupt processing, and the low-level interrupt processing routine executes other interrupt processing of the interrupt processing. To execute the high-level interrupt processing routine as long as there is a request to start the high-level interrupt processing routine, and to start and execute the low-level interrupt processing routine that has been suspended until after the high-level interrupt processing ends. It is provided with a control device characterized by the above.

(Operation) According to the present invention having the above configuration, in response to the same interrupt request of the input / output device, the high level interrupt processing request signal transmitting means outputs the high level interrupt processing request signal, and the low level interrupt processing request signal is output. The interrupt processing request signal transmitting means outputs a low level interrupt processing request signal. The processing device executes high-level interrupt processing and low-level interrupt processing based on these interrupt processing request signals. Then, the processing device preferentially executes the high-level interrupt processing as long as there is a start request to the high-level interrupt processing routine, so that the high-level interrupt processing routine executes the interrupt processing with a high degree of urgency. This enables efficient and high-speed processing.

(Example) Next, this invention is demonstrated with reference to drawings.

FIG. 1 shows an embodiment of a control device according to the present invention, and FIG.
The same reference numerals are used for the same or corresponding parts in the figure. In FIG. 1, the interrupt signals from the TRCs 4 to 7 are input to the OR gate 12 and at the same time supplied to the set input terminals of the flip-flops 8 to 11. The outputs of the flip-flops 8 to 11 are input to the OR gate 13 and also supplied to the read buffer 14.
The output of the OR gate 13 forms a low level interrupt processing request signal (hereinafter also referred to as an interrupt signal) INTL, while the output of the OR gate 12 outputs a high level interrupt processing request signal (hereinafter, interrupt signal). (Also referred to as INTH) and requests interrupt processing to the CPU 1 as the processing device of the present invention via the interrupt signal lines 23 and 24, respectively.

Next, the operation of FIG. 1 will be described below with reference to FIGS. 4 (f) and 5. Note that FIG. 4 (f) is a processing time chart according to the present invention, and FIG. 5 is a diagram showing an example of a processing program of the CPU 1 in FIG.

In the processing program of CPU1 in FIG. 5, compared with FIG. 3, the interrupt processing routine is divided into two, and in high-level interrupt (INTH) processing, only buffer switching is performed after the normal reception of TRC is completed. We are going to create the takeover information (steps S1 to S3), while in the low-level interrupt (INTL) processing,
After performing the low-level protocol processing of the received message based on the takeover information, the task for the high-level protocol processing is generated (steps S1 to S3).

Under the above processing program, if the reception end interrupts are generated at the same time on the four lines A to D in FIG.
Each line is processed as follows.

When the termination flag "F" shown in 41 (a) is detected in the input message of the four lines A to D, TRC4 to TRC7 simultaneously detect the interrupt signal lines.
Turn on 22. As a result, the interrupt signal is input to the OR gate 12, and the output of the OR gate 12 becomes the high-level interrupt processing request signal INTH, which is almost at the same time.
Set ~ 11. The outputs of the flip-flops 8 to 11 are low-level interrupt processing request signals via the OR gate 13.
Notify INTL to CPU1 via interrupt signal line 24.

CPU1 receives the above-mentioned high-level interrupt processing request signal INTH and low-level interrupt processing request signal INTL at approximately the same time, but since the interrupt priority is INTH> INTL, be sure to first
The interrupt processing routine for TH is started. CPU1 is INTH
In the processing routine, first, the CPU 1 accesses the read buffer 14 to know which TRC is, and when the TRC is TRC4, next, TRC4 is accessed and the TRC4 status register (not shown) is accessed. ) To know the cause of the interrupt. Then, after TRC4 determines that the reception is normally completed, the buffer switching processing is performed.

After this, CPU1 stores the line number for which the buffer was switched in MEM2 as takeover information, resets the interrupt factor of TRC4, and exits the high-level interrupt (INTH) processing routine (INTH processing S3 to S5. ).

However, at this point, the other TRC5 to TRC7 are also outputting interrupt processing requests, so the high level interrupt (INTH) processing routine is started again and the low level signals held in the flip-flops 8 to 11 are restarted. The interrupt (INTL) of is left pending.

In this way, the high level interrupt (INTH) of the line B is processed and the buffer is switched.

Similarly, the processing of line C and line D and INTH is completed in sequence. It has been held so far after the processing of INTH on line D is completed.
INTL processing routine is started (Fig. 4 (f), 5th).
Figure INTL processing). The CPU 1 knows from which line the INTL is generated via the read buffer 14, and when the INTLs are generated at the same time, the CPU 1 determines the priority and processes it. When the priority order is line A, B, C, D, and four lines A, B, C, D simultaneously interrupt, low-level protocol processing is performed based on the takeover information of line A. After generating a task for high-level protocol processing, the reset signal line 26 is turned on by an instruction, the flip-flop 8 is reset, and then the INTL processing routine is exited (step S1 of INTL processing
~ S5). At this point, the flip-flops 9 to 11 for the other lines B to D are on (being in the set state), so that the INTL processing routine for the line B is restarted immediately thereafter. INTL for lines C and D are processed in the same manner.

In this manner, the processing of INTH and INTL for all lines is performed, and the processing time is shown in a time chart in FIG. 4 (f). In FIG. 4 (f), when a reception end interrupt occurs simultaneously for four lines A to D, INTH processing Ta, Tb,
This indicates that Tc and Td are sequentially processed, and then INTL processes ta, tb, tc, and td are sequentially processed.

In the prior art example FIG. 4 (e), the buffer switching of the D line was not in time for the processing allowable time, whereas in the present invention, the buffer switching of all lines was performed within the processing allowable time τ as shown in FIG. 4 (f). It shows that you can do it. In short, interrupt processing with a high degree of urgency, especially buffer switching processing for all lines is processed in order from the one with the highest priority so that it does not interfere with reception, and the one with low urgency and does not affect reception Indicates that it is postponed because the allowable processing time τ may be exceeded. As a result, multi-line receiving stations can be processed efficiently and at high speed.

As can be seen from the above description, TRC as an input / output device
The interrupt processing request signals of two different levels are generated at substantially the same time for one of the interrupt factors, and the interrupt processing with the higher level of the interrupt processing has a high degree of urgency. Buffer switching processing, etc., and at lower level interrupt processing, less urgent interrupt processing, such as confirmation of the transmission sequence number and reception sequence number, is performed on the protocol. The TRC processing as an input / output device can be processed efficiently and at high speed. Therefore, it is possible to provide an excellent control device having high processing capability.

The present invention is not limited to the present embodiment, and various applications and modifications are conceivable without departing from the gist of the present invention. For example, in the present embodiment, as the interrupt processing request signal, two different levels of interrupt processing request signal are generated.
The present invention may generate a plurality of different levels of interrupt service request signals. In this case, in a plurality of different levels of interrupt processing, the interrupt processing to be performed may be applied stepwise according to the degree of urgency. The present invention can also be applied to a control device that does not include the direct memory access controller in this embodiment.

Further, the present invention is not limited to this embodiment, and even if the interrupt processing request signals of a plurality of different levels are not generated at substantially the same time, the interrupt processing on the low level side is an interrupt processing with low urgency. The interrupt processing request signal on the low level side may have an appropriate timing that does not interfere with the processing.

(Effects of the Invention) As described above, according to the present invention, a plurality of interrupt processing requests of different levels are generated for the same interrupt factor of the input / output device, and the interrupt processing on the higher level side of the interrupt processing is generated. The interrupt processing is performed with a high degree of urgency, and the low level interrupt processing is performed with a low degree of urgency, so that high-speed I / O devices and multiple I / O devices can be processed efficiently. The effect is great, for example, an excellent control device capable of performing high-speed processing at a high speed and having a high processing capacity can be provided.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a configuration diagram showing an embodiment of a control device according to the present invention, FIG. 2 is a configuration diagram showing an example of a conventional control device, and FIG.
FIG. 4 is a diagram showing an example of the processing program of the CPU of FIG. 2, FIG. 4 is a processing time time chart of the conventional and the present invention, and FIG. 5 is a diagram showing an example of the processing program of the CPU of FIG. 1 ... CPU, 4-7 ... TRC (transceiver), 8-11 ... flip-flops, 12,13 ... OR gate.

Claims (1)

[Claims] 1. A control device for executing a plurality of interrupt processes in a processing device by an interrupt signal from a transceiver provided corresponding to a plurality of input / output devices, wherein the interrupt signal from the transceiver is at a high level. High level interrupt processing request signal transmitting means for directly transmitting to the processing device as an interrupt processing request signal, and storing the interrupt signal from the transceiver and then transmitting to the processing device as a low level interrupt processing request signal. Low level interrupt processing request signal transmitting means and notification means for notifying the device of the transceiver that has output the interrupt signal are provided, and the plurality of interrupt processing in the processing device are the high level interrupt processing. The high-level interrupt processing routine corresponding to the request signal and the low-level interrupt processing routine corresponding to the low-level interrupt processing request signal are separately executed, and the high-level interrupt processing routine is executed. A high-level interrupt process is executed in the low-level interrupt process routine by executing a high-urgency interrupt process among the plurality of interrupt processes, and a high-level interrupt process in the low-level interrupt process routine. A control device, which executes a high-level interrupt process as long as there is a request to start the routine, and starts and executes a low-level interrupt process routine that has been suspended until after the high-level interrupt process is completed.