JPH01114958A - Bus control system - Google Patents

Abstract

PURPOSE:To obtain a method capable of shortening the through-put time of a system by providing an address bus and a data bus with respectively individual arbitration mechanisms and transferring data synchronously with a clock signal. CONSTITUTION:A bus master 6x for requesting data transfer sends an address bus request (ABR) signal by a requester 28 in an address bus arbitration mechanism, inputs its corresponding address bus ground (ABG) signal and then outputs an address/master number (AMNO) signal synchronously with a clock (CLK) signal. A bus slave 7y detecting specification based upon the address sends a data bus request (DBR) signal by a data bus arbitration mechanism synchronously with the clock (CLK) signal, inputs its corresponding data bus ground (DBG) signal and then returns an arrived and latched master number signal. A bus master 6x recognized the establishment of the data bus arbitration by the master number signal and executes data transfer.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an address between a data transfer requesting side (bus master), such as a CPU, and a data sending/receiving side (bus slave), such as a memory. This relates to a bus control method that controls the exchange of data.

[Prior Art] Conventionally, as this type of bus control method in electronic computer systems, so-called multipath, multipath ■, VM
E-bus, etc. are known (e.g. rVMEbus Architecture Manual, published by Japan Motorola Corporation's Semiconductor Division, published by CQ Publishing Co., Ltd., September 1984). Since they are similar, the VME bus will be explained below.

FIG. 2 is a diagram showing the system configuration of the VME bus.

A common bus 1 includes a system controller 2, a plurality of bus masters 31 to 3N, and a plurality of bus slaves 41 to 4M.
is connected. Here, the bus masters 31 to 3N correspond to CPUs and DMA controllers, and the bus slaves 41 to 4M correspond to memories, I10 interfaces, and the like.

FIG. 3 shows when reading data on the VME bus, that is, when reading data on the VME bus,
This indicates the timing of data transfer from any bus slave to any bus master.

Bus master 3i requesting data transfer (i=1 to N
) sends a bus request signal BR (active low) to the bus 1 (FIG. 3(A)). Here, the bus request signal BR is sent out by an open collector driver, and may be sent out simultaneously by a plurality of bus masters.

When the system controller 2 receives the bus request signal BR, it outputs a bus ground signal BG (active low).
is sent to bus 1 (Fig. 3 (8)).

The bus master that receives the pass ground signal BG must not send the bus request signal BR.
If it sends a pass ground signal to the next bus master and itself sends out a bus request signal BR, it takes in this pass ground signal BG and does not send it to the next bus master. In other words, the bus arbitration (bus contention management) configuration is a so-called daisy chain mechanism, in which multiple bus masters receive the bus request signal B.
Even if R is sent, the one that receives the pass ground signal BG first is selected and can use bus 1 exclusively. Note that in the following, it is assumed that the bus master 31 is selected.

In this way, the selected bus master 31 sends out address A (FIG. 3(C)).

Note that the address bus consists of, for example, 31 signal lines, and is normally in a floating state, with bus masters 31 to 31.
It is separated from 3N, and when selected, its master 31
is allowed to transfer address A.

Thereafter, the bus master 31 sends out an address strobe signal AS (active low) (FIG. 3(D)).

The bus slaves 41 to 4M receive the address strobe signal A.
It is known by S that address A has become valid. Therefore, the bus slaves 41 to 4M decode address A and determine whether or not they are selected. The selected bus slave 4j (j=1 to M) starts, for example, memory access.

Next, the bus master 31 sends the data strobe signal DS
((Active Low) (Fig. 3 (E)). The bus slave 4j that has received the data strobe signal DS sends data D to the bus 1 as soon as the operation such as memory access is completed (Fig. 3 (E)). (F)), the data bus consists of, for example, 32 signal lines, and is normally disconnected in a floating state, and is connected to the bus slave 4j at this time.The bus slave 4j then connects the data bus to the data bus. The bus master 31 sends the crudge signal DTACK (active low) to the bus 1 (FIG. 3 (G)).The bus master 31, knowing that the data D has become valid from the data acknowledge signal DTACK, transfers the data. Latch D internally.

Next, the bus master 31 sends the data strobe signal DS
Reset. As a result, the bus slave 4j learns that the bus master 31 has received the data D, resets the data acknowledge signal DTACK, returns the data bus to a floating state, and releases the data bus.
1 resets the address strobe signal AS, returning the address bus to a floating state and releasing it. Here, 1
bus cycle is completed.

In fact, the VME bus has four bus request signals BR.
There are two levels and two types of data strobe signals, but their details are not relevant to the point of this question, so their explanation will be omitted. Furthermore, the data write operation, that is, the data transfer from the bus master to the bus slave, has almost the same timing, so a description thereof will be omitted.

[Problems to be Solved by the Invention] However, in the timing control described above, it takes about 1 [μS] for one bus cycle, that is, from sending the bus request signal BR to returning the address bus to the floating state.
], and other bus masters cannot use the bus during this time, so in systems with multiple processors, the problem is that the overall system throughput time does not improve in proportion to the number of processors. there were.

The present invention has been made in consideration of the above points, and eliminates the problem of one bus master occupying the bus for a long time, thereby reducing throughput time in a system equipped with multiple processors. The aim is to provide a short bus control method with excellent performance.

[Means for solving the problems in between] In order to solve this problem, the present invention provides a bus control method in which a system controller, a plurality of bus masters, and bus slaves are connected to a common bus to control data transfer. was configured as follows.

That is, a unique bus art migration mechanism is provided for the address bus and data bus. Then, the bus master requesting data transfer outputs an address bus request signal in synchronization with the clock signal, takes in the address bus ground signal for this address bus request signal in synchronization with the clock signal, and addresses the bus master in synchronization with the clock signal. and transmits a master number signal. On the other hand, the bus slave specified by the address outputs the data bus request signal in synchronization with the clock signal, captures the data bus ground signal in response to the data bus request signal in synchronization with the clock signal, and captures the data bus ground signal in synchronization with the clock signal. Sends master number signal. After determining that this master number signal matches the number assigned to the bus master, the bus master then
Executes data transfer in synchronization with a clock signal.

[Operation] A bus master requesting data transfer sends out an address bus request signal using the address bus bus arbitration mechanism, takes in the corresponding address bus ground signal, and then sends an address and master number signal in synchronization with a clock signal. Output.

When a bus slave detects that it is specified by this address, it sends out a data bus request signal using the bus arbitration mechanism for the data bus in synchronization with the clock signal, captures the corresponding data bus ground signal, and then Send back the latched master number signal.

The above-mentioned bus master that requested the data transfer recognizes that data bus arbitration has been established by this master number signal in synchronization with the clock signal, and executes the data transfer.

[Example 1] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a timing chart of a data read operation in this embodiment, FIGS. 4 to 6 are block diagrams showing the internal configurations of the system controller 5, bus master 6x, and bus slave 7y in this embodiment, and FIG. 7 is a timing chart of a data write operation in this embodiment, and FIG. 8 is a timing chart showing details of timing control signals in this embodiment.

Although not shown in this embodiment, a common bus 8 is also used.
system controller 5, multiple bus masters 61~
6P and a plurality of bus slaves 71 to 7Q are connected (see FIG. 2).

As shown in FIG. 4, the system controller 5 includes a clock generator 11 that generates and outputs a system clock signal CLK, an address bus enable signal ABEN (active low), and a data bus enable signal DBEN, and an address bus enable signal DBEN. An address bus arbiter 12 receives a request signal ABR (active low) from the bus 8 and outputs an address bus ground signal ABG (active low) to the bus 8, and receives a data bus request signal DBR (active low) from the bus 8 and outputs the address bus ground signal ABG (active low) to the bus 8. The data bus arbiter 13 outputs a bus ground signal DBG (active low) to the bus 8.

Here, the clock generator 11 has a period of 100 [
nsl, system clock signal C with a duty ratio of 50%
LK (FIG. 8(A)), and also generates a data bus enable signal DBEN (data bus enable signal DBEN) which falls at the falling edge of this clock signal CLK and whose falling period is 60% of the period of the clock signal CLK. Figure 8 (B))
It also generates an address bus enable signal ABEN (FIG. 8(C)) which falls at the rising edge of the clock signal CLK and whose falling period is 60% of the period of the clock signal CLK.

As shown in FIG. 5, the bus master 6x (x=1 to P) includes an active element 21 such as a CPU or a DIMA controller. The data input/output terminal of the active element 21 is connected to the data line of the bus 8 via a driver 23 and a receiver 24.

The bus master 6X also includes a transfer control section 25, to which a clock signal CLK and an address bus enable signal ABEN are directly applied from the bus 8, and a data strobe signal DS (active low) is supplied to the transfer control section 25.
and data master number signal DMNO to receiver 2.
6. Further, the transfer control unit 25 is configured to output an address master number signal AMNO, an address strobe signal AS (active low), and a read/write control signal R/W to the bus 8 via the driver 27.

Furthermore, the bus master 6x includes an address bus requester 28. This address bus requester circuit 28 is configured to output an address bus request signal ABR to the bus 8 and to take in an address bus ground signal ABG from the bus 8.

Incidentally, the input/output timing control of the activating element 21 and the address bus requester 28 is performed by the transfer control section 25.

As shown in FIG. 6, the bus slave 7y includes a passive element 51 such as a memory and an I10 interface.

The address input terminal of the passive element 51 is connected to the receiver 52.
It is connected to the address line of bus 8 via. Furthermore, data input/output terminals are connected to the driver 53 and the receiver 5.
4 to the data line of bus 8. The bus slave 7y also includes a transfer control section 55. This transfer control unit 55 receives the upper bit of address A (instructing bus slave) through the receiver 52 and the read/write control signal R/W from the bus 8 through the receiver 56.
It receives an address strobe signal AS and an address master number signal AMNO, and outputs a data strobe signal DS and a data master number signal DMNO to the bus 8 via a driver 57. Further, the transfer control unit 55 controls input/output timing of the passive element 51 and the data bus requester 58. The data bus requester 58 is configured to output a data bus request signal DBR to the bus 8 and receive a data bus ground signal DBG.

Note that the transfer control unit 55 controls the clock signal CLK from the bus 8 and the address bus enable signal ABEN.
, are performed in synchronization with data bus enable signal DBEH.

Next, the data read operation of this embodiment will be explained using FIG. Bus master 6 that needs to read data
x generates an address bus request signal ABR (Fig. 1 (A)) in synchronization with the rise of the clock signal CLK (Fig. 1 (A)).
8)) is sent from the address bus requester 28 to the bus 8. Since the address bus request signal ABR is sent out by an open collector driver, it may be sent out redundantly from a plurality of bus masters.

This address bus request signal ABR is received by the address bus arbiter 12 in the system controller 5, and the system controller 5 sends an address bus ground signal ABG (FIG. 1(C)) from the address bus arbiter 12. do. This signal ABG is a signal generated by a daisy-chain mechanism similar to the VME bus, and is a signal generated by the bus master 6x that sent the address bus request signal ABR.
, and only this bus master 6x can use the address line.

That is, the bus master 6x samples the address bus ground signal ABG at the next rising time t1 of the clock signal CLK, resets the address bus request signal ABR if it is active, and activates the driver 27 in synchronization with the address bus enable signal ABEH. The address master number signal AMNO is sent to the bus 8 via the driver 22, and the address A is sent to the bus 8 via the driver 22 (FIG. 1CD), (E)). The address master number signal AMNO is, for example, a 4-pit signal via 4 signal lines, and is a number unique to each bus master. Consists of bit signals.

Note that the signal lines for the address master number signal AMNO1 and the address A are normally in a floating state and disconnected, and are electrically connected when being sent to the bus 8.

The bus master 6x sends an address strobe signal AS and a read/write control signal R/W (r I J: read) to the bus 8 via the driver 27 at the same time as these signals AMNO and A.

On the other hand, on the bus slave 7y side, when the address strobe signal AS is active, the transfer control unit 55 samples the address A at the falling time t2 of the clock signal CLK, and determines whether the bus slave 7y itself has been selected. do.

If the address master number signal AMNO at this time t2 is selected by the control unit 55,
, address A, and read/write control signal R/W, and perform predetermined operations such as memory access. 1.5 of the clock signal CLK from the point at which such an operation ends.
At the time before the cycle, the bus slave 7y receives the data bus request signal DBR(
1 (tl)) to the bus 8 in synchronization with the rise of the clock signal CLK. Note that since the data bus request signal DBR is sent out by an open collector driver, it may be sent out redundantly from a plurality of bus slaves. In the following, only the case where the signal is sent from the bus slave 7y will be considered.

This data bus request signal DBR is accepted by the data bus arbiter 13 in the system controller 5.
3 to data bus ground signal DBG (Figure 1 CI))
Send out. This data bus ground signal DBG is a signal generated by the same daisy-chain mechanism as the address bus ground signal ABG, and is a signal generated by the data bus request signal D.
Bus slave 7y that sent out BR receives this data bus ground signal DBG.

The bus slave 7y that has sent out the data bus request signal DBR in this way samples the data bus ground signal DBG at the next rising edge time t3 of the clock signal CLK by the control unit 55, and if it is active, the address master number signal AMNO is The value of is sent to the data master number signal DMN via the driver 57.
0 (Fig. 1 (J)). The signal line for the data master number signal DMNO is normally disconnected in a floating state, and when sent to the bus 8, it becomes a transmission state and the address bus enable I signal ABE
This signal DMNO is sent out in synchronization with N. At the same time, the floating state of the data strobe signal line is released and the data strobe signal DS (FIG. 1(L)) is sent to the bus 8.

Thereafter, data D (the first
(in)) is outputted via the driver 53. Data D
is a 32-bit signal formed by, for example, 32 signal lines, and is released from the floating state at the time of transmission and is transmitted in synchronization with the data bus enable signal DBEN.

On the other hand, when the data strobe signal DS is active, the bus master 6x that sent out the address A uses the control unit 25 to sample the data master number signal DMNO at the falling edge of the clock signal CLK, and samples the data master number signal DMNO so that it matches its own master number. Decide whether or not. If they match, the time t5 is delayed by half a period of the clock signal CLK.
In this step, the data D is latched by the active element 21.

Thus, one data read cycle is completed.

Next, the data write operation in the present invention will be explained with reference to FIG. Note that the bus master 6x that needs to write data sends the address bus request signal ABR (seventh
(B)) and sends the address bus ground signal ABG.
(Fig. 7 (C)), address master number signal AMNO (Fig. 7 (D)), address A (Fig. 7 (E)), and address strobe signal As (Fig. 7 (F)).
), and read/write control signal R/W (Figure 7 (G))
The operation up to sending out the read/write control signal R/W
This operation is the same as the data read operation except that it is set to logic "0" indicating a write operation, so its explanation will be omitted.

The bus slave 7y monitors the state of the address strobe signal AS every time the clock signal CLK falls, and if the address strobe signal AS is active, the bus slave 7y samples the upper bit of the address A at that time, and Determine whether you are selected. If oneself is selected, the control unit 55 at time t6
latches the address master number signal AMNO, address A, and read/write control signal R/W.

Further, the bus slave 7y selected at the next rising edge time point t7 of the clock signal CLK is transferred to the data bus requester 5.
8 to data bus request signal DBR (Fig. 7 (■)
) on bus 8.

This request signal DBR is transmitted by the system controller 5
The system controller 5 sends out a data bus ground signal DBG (FIG. 7(I)) from the data bus arbiter 13.

The bus slave 7y that has sent out the data bus request signal DBR samples this ground signal DBG at the next rising time t8 of the clock signal CLK by the control unit 55, and if it is active, resets the data bus request signal DBR and The value of the address master number signal AMNO latched is sent out via the driver 57 as the data master number signal DMNO (FIG. 7(J)). At the same time, a data strobe signal DS (see FIG. 7) is sent to the bus 8.

First, when the data strobe signal DS is active, the bus master 6X that sent out the address A uses the control unit 25 to sample the data master number signal DMNO at the falling edge of the clock signal CLK, and samples the data master number signal DMNO so that it matches its own master number.・Determine whether or not. If they match, data D (Fig. 7 (
)) is sent to the bus 8 via the driver 23.

On the other hand, the selected bus slave 7y writes the data D on the data bus into the passive element 31 at time tlo delayed by a half period of the clock signal CLK from time t9. Thus, one data write cycle is completed.

Therefore, according to the above embodiment, since the address bus and the data bus are treated as independent buses and bus arbitration is performed individually, that is, the arbitration of the address bus and the data bus is pipelined respectively, the arbitration of the address bus and the arbitration of the data bus are performed simultaneously. Arbitration of the data bus can be performed simultaneously, and from this point the throughput time of the entire system can be improved.

Further, according to the embodiment described above, address and data transfer is controlled by a timing control signal (C) from the system controller.
LK, DBEN, ABEN>, a float period is provided during which the address data occupies the bus, and the time is longer than half a cycle of the clock signal and shorter than one cycle, and the change point of the clock signal is determined during that time. Since the address and data can be transferred in less than one clock cycle while the bus is occupied, the previous and subsequent clock cycles can be used to transfer other addresses and data.
From this point of view as well, the throughput time of the entire system can be improved.

That is, a bus control method suitable for a multiprocessor system including a plurality of processors can be realized.

In reality, the bus occupancy time for address and data is
It was about 1/10 of the ME bus.

In the above-mentioned embodiment, the application to an electronic computer system was shown, but the invention can be applied to any system as long as it has a plurality of bus masters.

[Effects of the Invention] As described above, according to the present invention, separate arbitration mechanisms are provided for the address bus and the data bus to perform data transfer in synchronization with a clock signal.
A bus control system that can simultaneously execute address and data transfers using different combinations of bus masters and bus slaves and shorten system throughput time can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a timing chart of each part during a data read operation of an embodiment of the bus control method according to the present invention, FIG. 2 is a block diagram showing a system configuration to which the conventional method is applied, and FIG.
The figure is a timing chart of each part during data read operation in the conventional system, Figure 4 is a block diagram showing the system controller of the above embodiment, Figure 5 is a block diagram showing the bus master of the above embodiment, and Figure 6 is a block diagram showing the above implementation. FIG. 7 is a block diagram showing an example bus slave, FIG. 7 is a timing chart of various parts during data write operation of the above embodiment, and FIG. 8 is a timing chart showing timing control signals of the above embodiment. 5... System controller, 61-6P... Bus master, 71-7Q... Bus slave, 8... Bus, 11... Clock generator, 12... Address bus arbiter, 13...・Data bus arbiter, 21...
- Active element, 25... Transfer control unit, 28...
Address bus requester, 51...passive element, 5
5... Transfer control unit, 58... Data bus requester, CLK... Clock signal, DBEN... Data bus enable signal, ABEN... Address bus enable signal, ABR... Address bus request signal.
ABG: address bus ground signal, A: address, AMNo: address master number signal,
DBR...Data bus request signal, DBG...
Data bus ground signal, D...data, DMNO/
...Data master number signal. Figure 2? Check the timing of each part of the data read operation for 1 country ξ!
- Fig. 3 - Timing chart of data light tuna for one free time - Fig. 7 - Procedural correction (written on my own initiative) July 1988. Director General of the Patent Office on the 18th, Yoshi 1) Moon Takeshi 1, Indication of the case, Patent Application No. 271781 of 1988, 2, Name of the invention, Bus control system 3, Person making the amendment, Relationship with the case, Address of the patent applicant (105 ) 1-7-12 Toranomon, Minato-ku, Tokyo Name (029) Oki Electric Industry Form Company Representative
Nobumitsu Kosugi 4, Agent address (〒108) 4-10-3-5 Shibaura, Minato-ku, Tokyo.
In the "Detailed Description of the Invention" column of the specification to be amended, and "(Active Low)" in "Drawing 6, Contents of Amendment (1) Specification, page 5, line 16", "(Active Low)" (2) In the specification, page 7, line 17, “throughput” should be corrected as “
Correct it to "Access." (3) In the specification, page 8, line 7, "Bus Art Trasion" is corrected to "Bus Arbitration." (4) "Data bus enable" on page 19, line 4 of the specification is corrected to "data bus enable." (5) In the specification, page 22, line 7, "perform memory write, etc." is corrected to "perform memory write, etc." (6) In the specification, page 22, line 11, "that is" is corrected to "further." (7) Delete "address...executable" from lines 13 to 15 on page 22 of the specification. (8) Delete "Time" from page 22, line 16, and page 23, line 8 of the specification. (9) In the specification, page 24, lines 4 and 5, "Throughput time can be shortened" is corrected to "Throughput can be improved." (10) "Passive element" on page 25, line 5 of the specification is corrected to "passive element."that's all

Claims (1)

[Claims] In a bus control method in which a system controller, multiple bus masters, and multiple bus slaves are connected to a common bus to control data transfer, each address bus and data bus has its own bus arbitration mechanism. , one of the bus masters outputs an address bus request signal in synchronization with the clock signal, takes in an address bus ground signal for this address bus request signal in synchronization with the clock signal, and outputs an address in synchronization with the clock signal. and a master number signal, the bus slave specified by the address outputs a data bus request signal in synchronization with the clock signal, and a data bus ground signal in response to the data bus request signal in synchronization with the clock signal. and sends out the master number signal that has been taken in synchronization with the clock signal, and each bus master determines whether its own number matches the master number signal from the bus slave. A bus control method characterized in that data transfer between a bus master and the bus slave is performed in synchronization with the clock signal.