JPH0560625B2 - - Google Patents

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Application Fields Conventional Technology Problems to be Solved by the Invention Means for Solving the Problems (Fig. 1) Working Example (a) One Implementation Explanation of examples (Fig. 2, Fig. 3, Fig. 4,
5, 6) (b) Description of other embodiments Effects of the invention [Summary] When a plurality of masters and a plurality of slaves are connected to a common bus, the master that has acquired the right to occupy the bus transmits a message to the common busy line. In a system in which each master arbitrates for bus ownership when the busy signal is turned off, a busy signal generation circuit is provided in the slave, and during write access, following the master's busy signal,
By having the slave issue a busy signal, write access and bus occupancy arbitration can be performed in parallel.

[Industrial application field]

In the present invention, multiple masters and multiple slaves are connected via a common bus, and the master that has acquired the right to occupy the bus through arbitration accesses the slave via the common bus, and transfers read/write data with the slave. In a master-slave system that performs data transfer, an access control method that transfers data by occupying a common bus according to the response time of each master and slave is particularly important. This invention relates to an access control method that enables efficient bus use.

In master-slave systems in which multiple masters and multiple slaves are connected to a common bus and the master accesses the slaves, in order to enable complex processing, masters with various response speeds,
Slaves are mixed. Therefore, access time varies depending on the combination of master and slave.
Variable access time data transfer technology is used.

In such a system, since there are multiple masters, a cycle is required for contention arbitration (called arbitration) in response to a master's access request (bus occupancy request), and the bus is not used during that time. There is a need for an access control scheme that allows arbitration during the access cycle.

[Conventional technology]

As a master-slave system, for example, three masters 1a, 1b, 1c shown in FIG.
Assume that it is connected to terminals a and 2b. Master 1
a, 1b, 1c are CPU (central processing unit),
A DMAC (direct memory access controller), an I/O controller, etc. are used, and a memory, an I/O controller, etc. are used as the slaves 2a, 2b.

In such a master-slave system, in addition to the common bus C-BUS, a control line is provided for exchanging control signals. *Response line for transmitting ACK to the master side
la, write strobe signal during write access *
A write strobe line lw is provided to transmit WSTRB to the slave, and a start line ls is provided to transmit the start signal *START to the slave.

Further, request lines RQ1 and RQ2 are provided for arbitration between masters 1a, 1b, and 1c, and in this example, master 1a has the highest priority and master 1c has the lowest priority.

In such a master/slave system, as shown in FIG.
Perform read or write access to b, and see access requests on request lines RQ1 and RQ2 while the busy signal *BUSY has fallen to high level.
Arbitration takes place. In this example, if master 1a has issued an access request, even if masters 1b and 1c have access requests, master 1a will issue an access request.
If master a acquires the bus exclusive right and master 1a has not issued an access request but master 1b has issued an access request, master 1b acquires the bus exclusive right even if master 1c has issued an access request. do.

In this case, if the master that has acquired bus occupancy drops the busy signal *BUSY one cycle before the access is completed, as shown in Figure 7B, arbitration can be executed in parallel during the access cycle, resulting in more efficient use of the bus. It becomes possible.

On the other hand, in such a master-slave system, the response time of each master and slave is not necessarily constant, and therefore the access time is not constant.

For example, when performing an ECC check on data,
The master or slave is provided with an ECC creation/check circuit. The required time is determined by the performance of this circuit (that is, the speed of the elements used), which may affect the length of the access time.

Further, the access time differs depending on the type of data holding circuit.

For example, FF, latch, etc. can be accessed in a very short time (several ns to tens of ns). When it comes to memory, there are dozens of static RAMs.
ns, dynamic RAM requires more than 100 ns of time.

In the device, how the data is used or
The type of holding circuit is selected depending on the frequency of use.

For this reason, access time is made variable using a response confirmation method.

For example, assume that master 1a requires 2 clocks to capture read data and 1 clock to output write data, slave 2a requires 1 clock to capture write data, and 1 clock to output read data, and slave 2b requires 1 clock to capture write data. Assuming that it takes 2 clocks to capture and 2 clocks to output read data, the response confirmation sequence is the 8th clock.
It will look like the figure.

When the master 1a performs read access to the slave 2a, as shown in FIG.
is sent to the start line ls, and sent to the common bus C-BUS as an address (including a flag indicating the access mode at the beginning), and slave 2a takes in the address of the common bus C-BUS at the rising edge of the clock shown in the figure, decodes it, and reads it. Access and decode the address.

Since the slave 2a can output read data in one clock, it immediately issues an ACK signal *ACK to the response line la to notify the timing at which the read data becomes valid, notifies the master 1a, and then outputs the read data at the timing of the clock. The common bus C-
Send to BUS.

The master 1a receives the ACK signal *ACK at the rising edge of the clock and takes in read data from the common bus C-BUS in two clocks. At this time, master 1a knows that it takes two clocks, so it turns off (high level) the busy signal *BUSY at the clock one clock after the rising edge of the ACK signal, and the slave 2a turns off (high level) the busy signal *BUSY at the rising edge of the clock. , detects that the busy signal *BUSY is off and stops outputting read data. Therefore, an access time of four clocks is required for the master 1a to read access the slave 2a.

On the other hand, when the master 1a performs write access to the slave 2a, as shown in FIG. 8B, the master 1a
emits a busy signal *BUSY and also a start signal *START, and connects the common bus C-BUS.
send an address to. Along with this, master 1a
Since write data can be output in one clock, the write strobe signal *WSTRB that indicates the valid timing of write data is connected to the write strobe line.
Emit to lw. The slave 2a decodes the address at the rising edge of the clock, learns the write address, and decodes the write address.

Master 1a outputs write data to the common bus C-BUS at the rising edge of the clock, and slave 2
The master 1a issues an ACK signal *ACK indicating completion of taking in the write data, and the master 1a catches the ACK signal *ACK at the rising edge of the clock, thereby dropping the busy signal *BUSY and stopping outputting the write data.

Therefore, it takes two clocks for the master 1a to write access to the slave 2a.

Similarly, in order for the master 1a to read access the slave 2b, as shown in FIG. 8C, the slave 2b requires two clocks to output the read data, as shown in FIG. Clock delay: Read data is also output with a one clock delay, making the access time five clocks.

Also, in order for the master 1a to write access to the slave 2b, as shown in FIG. 8D, compared to FIG. 8B,
Slave 2b captures (writes) write data
Since it takes 2 clocks to complete, the write data is output for 2 clocks, and the ACK signal *ACK is also 1 clock.
It is output with a clock delay, and the access time is three clocks.

If the master requires two clocks to output the write data, the write strobe signals shown in Figure 8 B and D *
WSTRB is delayed by one clock, write data is also outputted with a delay of one clock, and each access time increases by three clocks and four clocks.

In this way, the access time between the master and slave is determined by the data output timing signal, that is, the ACK signal *ACK when reading, the write strobe signal *WSTRB when writing, and the ACK signal *ACK when writing is completed. As shown, it is possible to provide the fastest and most optimal access time depending on the response times of the master and slave.

[Problem that the invention seeks to solve]

In such a conventional access control method, since the master side handles the busy signal *BUSY, it knows its own response time during read access and can obtain a cycle before the access is completed. As shown in A and C, the slave side's ACK signal is sent one cycle before the access is completed*
In response to the ACK, the busy signal *BUSY can be dropped, thus allowing arbitration during the access cycle.

However, during write access, the access is completed by the slave side, so it is not possible to know the cycle before the access is completed. Therefore, the timing to drop the busy signal *BUSY is the slave side's ACK signal (write completion signal) *ACK I had no choice but to generate it by . This also applies to read modified write access, which is handled as a type of write access that performs read and write in series.

Therefore, in write access and read modified write access,
As shown in the figure, the busy signal * until the access is completed.
Since BUSY did not fall, arbitration was performed after the access was completed, and the problem was that arbitration could not be performed during the access cycle and the bus could not be used effectively.

SUMMARY OF THE INVENTION An object of the present invention is to provide an access control method for a master/slave system that can perform arbitration during an access cycle even during write access.

[Means for solving problems]

FIG. 1 is a diagram explaining the principle of the present invention.

In FIG. 1A, the same components as those shown in FIG.
4 is a busy signal generation circuit on the slave side, which is provided in a slave (for example, 2b) which requires two or more clocks to take in write data.

As shown in FIG. 1B, in the case of the master-slave relationship in FIG. 8B, where the slave side takes in write data in one cycle (clock) (for example, slave 2a), before outputting the write data. The master's busy signal *BUSY is dropped.

On the other hand, in cases where it takes two or more cycles (clocks) to capture the write data on the slave side, such as the relationship between master and slave shown in Figure 8D, as shown in Figure 1C, the write data is output (for example, slave 2b). Drop the master's busy signal *BUSY before
Subsequently, the busy signal generating circuit 4 of the slave generates a busy signal *BUSY.

[Effect]

In the present invention, at the time of write access, the master issues the busy signal *BUSY from the start of the access until the write data output, which is its own response time. signal*
Even if BUSY is not issued, the busy signal *BUSY can be dropped one cycle before the access is completed, so
Arbitration is performed first during the access cycle.
It can be executed in parallel as shown in Figure B.

On the other hand, for a slave that requires two or more clocks to take in write data, a busy signal generating circuit 4 is provided to generate a busy signal *BUSY after the master's busy signal *BUSY is turned off.

Since the slave side knows the acquisition time of its own write data, the slave's busy signal *
Since BUSY can be dropped one cycle before the completion of the access cycle as shown in FIG. 1C, arbitration can be executed in parallel during the access cycle.

Moreover, this can be executed without changing the sequence of the other control signals except for the busy signal *BUSY.

In short, the busy signal can be driven even on the data receiving side.

〔Example〕

(a) Description of an Embodiment FIG. 2 is a block diagram of main parts of an embodiment of the present invention, FIG. 2A is a block diagram of the busy signal generation circuit 3 on the master side, and FIG. 2B is a block diagram of the busy signal generation circuit 3 on the slave side. 3 is a configuration diagram of a busy signal generation circuit 4. FIG.

In FIG. 2A, 30 is an AND gate, which is a logic between the busy signal *BUSY on the busy line lb and the access enable signal ACC, which becomes high level (“1”) when access is possible as a result of arbitration. The device that takes the product, 31 is an AND gate that takes the logical product of the read mode signal READ indicating the read access mode and the timing signal RAC that is issued in a cycle before the master completes reading data when reading. ,
32 is an AND gate, which outputs an inverted read mode signal *READ and an inverted write strobe signal.
33 is a NOR gate that performs logical product with WSTRB, and AND gates 31, 3
Those who take 2 Noah (NOT OR), 34 is J
-K flip-flop, and gate 3
The output of 0 is input to the J terminal, the output of the NOR gate 33 is inverted and input to the K terminal, 35 is a tri-state buffer, and the output of the J-K flip-flop 34 connects the busy signal *BUSY to the busy line lb. It is something that emanates.

Therefore, the busy signal generation circuits 3 of the masters 1a to 1c have the following characteristics compared to conventional busy signal generation circuits:
An AND gate 32 and a NOAH gate 33 are added.

To explain the operation of this configuration, the AND gate 30 is opened while the *busy signal BUSY on the busy line lb is at a high level (falling), and if the master acquires the right to occupy the bus by arbitration during that time, the access enable signal ACC This generates an output from the AND gate 30, which inverts the J-K flip-flop 34, thereby turning on the tri-state buffer 35 and transferring the low-level busy signal *BUSY to the busy line lb. Output.

On the other hand, in read access by the master, a read mode signal READ is issued by the master, and the AND gate 31 is opened. The master issues a timing signal RAC in a cycle before completing the acquisition of read data, thereby inverting the JK flip-flop 34 through the AND gate 31 and the NOR gate 33, thereby inverting the tri-state buffer 35. Off, busy signal *
Set BUSY to high level and drop it.

Further, in a master write access (including read modified write access), since the read mode signal READ is low level, the inverted read mode signal *READ becomes high level and opens the AND gate 32. Write strobe signal from the master indicating that write data is valid*
When WSTRB is issued, AND gate 3 is activated by the inverted write strobe signal WSTRB.
2. Inverts the JK flip-flop 34 through the NOR gate 33, thereby turning off the tri-state buffer 35, and outputting the busy signal *
Set BUSY to high level and drop it.

Therefore, in a write access, the master's busy signal *BUSY is at a low level from the start of the write access until before the write data is output.

On the other hand, the slave busy signal generating circuit 4 will be explained with reference to FIG. 2B.

In FIG. 2B, 40 is an ant gate, which receives the master's inverted write strobe signal WSTRB,
41 is a J-K flip-flop which takes an AND with the timing signal WMS when a write access is detected by address decoding of the slave, and the output of the ant gate 40 is input to the J terminal, and the slave write is completed. The timing signal WAC output in the previous cycle is K
What is input to the terminal, 42 is a tri-state buffer, and a J-K flip-flop 41
This output outputs a busy signal *BUSY to the busy line lb.

To explain the operation of this configuration, it does not operate in read access, but operates only in write access. When the slave detects a write access by address decoding, it outputs a timing signal.
Emit WMS and open AND gate 40. When the write strobe signal *WSTRB is issued from the master, the JK flip-flop 4 is activated by the AND gate 40 in response to the inverted signal WSTRB.
1 is inverted, thereby turning on the tri-state buffer 35 and generating a low-level busy signal *
Outputs BUSY to busy line lb.

Next, when the slave issues the timing signal WAC in a cycle before the write is completed, it inverts the JK flip-flop 41, thereby turning off the tri-state buffer 42, and setting the busy signal *BUSY to high level. Drop it.

Therefore, in write access, the slave's busy signal *BUSY is output following the master's busy signal *BUSY off, and is turned off one cycle before the write is completed.

Next, the access operation between the master and slave will be explained.

In FIG. 1A, master 1a as in FIG.
It takes 2 clocks to capture read data and 1 clock to output write data, and slave 2a
It takes 1 clock to capture write data and 1 clock to output read data, and slave 2b
It takes 2 clocks to capture write data and 2 clocks to output read data, and master 1b
(1c) takes 1 clock to capture read data,
The master-slave system shown in FIG. 1A will be explained assuming that it takes one clock to output write data.

In this case, the masters 1a to 1c have the
The busy signal generation circuit 3 of the slave 2b
The busy signal generating circuit 4 of FIG. 2B is provided,
The slave 2a is not provided with the busy signal generating circuit 4.

First, the access operations of the master 1a and slaves 2a and 2b will be explained with reference to FIGS. 3 and 4.

FIG. 3 is an explanatory diagram of access between the master 1a and the slave 2a. FIG. 3A is the read access, FIG. 3B is the write access, and FIG. 3C is the read modified write. The case of access is shown in Figure 4, where master 1
a is an access explanatory diagram of slave 2b;
FIG. 4A shows the case of read access, FIG. 4B shows the case of write access, and FIG. 4C shows the case of read modified write access.

When the master 1a performs read access to the slave 2a, as shown in FIG. 3A,
The operation is the same as that of the conventional example, and arbitration can be performed during the access cycle.

When the master 1a performs write access to the slave 2a, the master 1a outputs the busy signal *BUSY as in the case of FIG. 8D, outputs the address to the common bus C-BUS, and outputs the write strobe signal *WSTRB. Output. Then, write data is output to the common bus C-BUS at the next clock.

The slave 2a takes in the write data and issues an ACK signal *ACK as a completion notification.

As a result, the master 1a stops outputting write data.

At this time, the master 1a completes the access by dropping the busy signal *BUSY using the write strobe signal *WSTRB.
Before the cycle, the busy signal *BUSY falls (becomes high level) and arbitration becomes possible.

Further, when the master 1a performs read-modified-write access to the slave 2a, the master 1a issues a busy signal *BUSY, a start signal *START, and issues an address to the common bus C-BUS. slave 2a
It knows by decoding that it is a read modified access, and since read data can be output in one clock, it outputs an ACK signal *ACK, which makes the read data valid. and,
The slave 2a outputs read data to the common bus C-BUS at the rising edge of the clock.

Since the master 1a can take in read data in two clocks, it outputs the write strobe signal WSTRB at the rising edge of the clock, and the slave 2a stops outputting read data. At the same time, the master 1a drops the busy signal *BUSY and outputs the write data to the common bus C-BUS. This enables arbitration from one cycle before the access is completed.

Next, the case where the master 1a accesses the slave 2b will be explained with reference to FIG.

When the master 1a performs read access to the slave 2b, it is the same as in FIG. 3A, and since the slave 2b requires two clocks to output read data, the ACK signal *ACK and the start of output of read data are delayed by one clock. .

When the master 1a performs write access to the slave 2b, as shown in FIG. 4B, the master 1a outputs a busy signal *BUSY and an address to the common bus C-BUS, as shown in FIG. 4B, and also outputs a write strobe signal * Output WSTRB. Then, at the next clock, the common bus C-
Outputs write data to BUS and drops master 1a's busy signal BUSY. Slave 2b is
It takes in the address, decodes it, and outputs a busy signal BUSY to the busy line lb using the write strobe signal *WSTRB.

Slave 2b uses 2 to capture write data.
Since a clock is required, the ACK signal is output at the clock timing, and the busy signal BUSY is dropped. Also, master 1a
stops outputting write data at the rising edge of the clock due to the ACK signal *ACK.

Therefore, at the start of access, the busy signal *BUSY of the master 1a is driven, and then the busy signal of the master 1a drops by the write strobe signal *WSTRB, and the busy signal *BUSY of the slave 2b is output, indicating that the access is completed. The busy signal falls before one cycle, allowing arbitration during the access cycle.

Furthermore, when the master 1a performs read modified write access to the slave 2b, as shown in FIG. 4C, the process up to the read data output up to the clock is the same as the read access shown in FIG. 4A. Master 1a sends a write strobe signal* in synchronization with the rising edge of the clock.
Output WSTRB. Then, at the rising edge of the clock, write data is output to the common bus C-BUS, and at the same time, the busy signal BUSY is dropped. Slave 2b is a write strobe signal*
WSTRB outputs the busy signal *BUSY, captures the write data, and completes the access.
Drop the busy signal *BUSY before the cycle.

The master 1a detects the fall of the busy signal *BUSY at the rising edge of the clock and stops outputting write data.

In this way, arbitration is possible during the access cycle.

Next, master 1b (or 1c)
The case of accessing a will be explained with reference to FIG.

When master 1b performs read access to slave 2a, as shown in FIG. 5A, the operation is the same as in FIG. One less cycle is required.

Next, when the master 1b performs write access to the slave 2a, as shown in FIG. 5B, the third
The operation is exactly the same as in Figure B.

Furthermore, when the master 1b performs read-modified-write access to the slave 2a, as shown in FIG. 5C, the operation is the same as that in FIG. 3C,
Since the master 1b only needs one clock to take in the read data, the access time can be reduced by one cycle.

Next, the case where the master 1b accesses the slave 2b will be explained with reference to FIG.

When master 1b performs read access to slave 2b, as shown in FIG. 6A, the operation is the same as that in FIG. One less cycle is required.

Further, when the master 1b performs write access to the slave 2b, as shown in FIG. 6B, the operation is the same as that in FIG. 4B.

Furthermore, when master 1b performs read-modified-write access to slave 2b, the sixth
As shown in FIG.
It takes fewer cycles.

(b) Description of Other Embodiments As is clear from the above embodiments, the response times (read data acquisition and write data output times) of a plurality of masters may be the same or different.

On the other hand, the plurality of slaves may have the same or different read data output times, but the present invention is applied to a plurality of slaves that have different write data take-in times.

For example, if the slave 2a requires three cycles (clocks) to take in write data, the slave 2a will also need the busy signal generating circuit 4.

These can be adopted as appropriate depending on the required system configuration.

Furthermore, although each master is given bus occupancy priority in arbitration, it is also possible to perform contention control in which the bus occupancy is given to the one that issued the earliest access request. The number of is also not limited to the example.

Furthermore, although the common bus C-BUS has been described as an access and data multiplexer bus, it may be a separate address bus and data bus, and the control signals may also be in other formats.

Although the present invention has been described above using examples, the present invention can be modified in various ways according to the gist of the present invention, and these are not excluded from the present invention.

〔Effect of the invention〕

As explained above, according to the present invention, even if multiple slaves with different write data acquisition times are connected, arbitration can be executed during write access, and the bus can be used effectively. This is effective, and in particular, the bus of a complex system in which various slaves are connected can be used effectively, and the overall processing efficiency can be improved.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram of the principle of the present invention, Fig. 2 is a configuration diagram of essential parts of an embodiment of the invention, Figs. 3 to 6 are illustrations of access to an embodiment of the invention, and Figs. The figure is an explanatory diagram of the prior art. In the figure, 1a, 1b, 1c...master, 2a, 2
b...Slave, 3, 4...Busy signal generation circuit, C-BUS...Common bus, lb...Busy line.

Claims (1)

[Claims] 1. A plurality of masters 1a, 1b, 1c and a plurality of slaves 2a, 2b are connected to a common bus C-BUS, and the plurality of masters 1a, 1b, 1c are connected to a busy bus on a common busy line lb. Each master 1 when the signal is not valid
In a master-slave system, in which the master that has acquired the bus occupancy right after arbitration of bus occupancy rights of a, 1b, and 1c enables the busy signal on the common busy line lb and accesses the desired slave, the busy signal is sent to the slave. A generation circuit 4 is provided, and at the time of write access, the master that has acquired the right to occupy the bus enables the write strobe, then disables the write strobe, disables the busy signal, and transfers the write data to the common bus. In the slave, the busy signal generating circuit 4
A busy signal is generated and enabled on the common bus in response to the write strobe, and the busy signal is disabled one cycle before the completion of the capture of the write data, thereby making it possible to arbitrate bus occupation rights between the masters. An access control method characterized by: