JPS62175850A - Channel device - Google Patents

Abstract

PURPOSE:To decrease the starting frequency of the channel control firmware in order to reduce its load and at the same time to shorten the access time, by setting only the address that lost its continuity to an address register via the firmware. CONSTITUTION:The channel adaptor part 20 of a channel device 1 receives the transaction request of the address/command sent from a peripheral device 4 and fetches the address and the command set on a direct channel interface 5 to an address/command store register 21. An address discordance detecting circuit 24 compares the address fetched by the register 21 with an address stored in an address register. When no coincidence is obtained between both addresses, an interruption flip-flop is set to produce an interruption signal. Thus the channel control firmware of a channel control part 10 is started.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a channel device installed between a main storage device and a peripheral device in an electronic computer system.

2. Description of the Related Art In general, in computer systems, a channel device is installed between peripheral devices such as input/output devices and the main storage device, and after the central processing unit issues an input/output command to the channel device, Peripheral devices can access the main memory through this channel device without any intervention from the central processing unit.

In a channel device that receives an access address of a main memory device from a peripheral device via a direct channel interface, each time an access address is received from the peripheral device, it is set in an address register under firmware control.

Problems to be Solved by the Invention Among the conventional channel devices mentioned above, those that access the main memory and transfer data to and from the peripheral device in units of one word have a channel control firmware that accesses the main memory and transfers data to and from the peripheral device on a word-by-word basis. must be started and set in the address register. Therefore, there are problems in that memory access takes time and the load on the channel control firmware increases.

Means for Solving the Problems The channel device of the present invention which solves the problems of the prior art described above increments the access address each time it is supplied to the main memory, and also increments the access address received from the peripheral device. The continuity of main memory access addresses is monitored, and if this continuity is maintained, the incremented access address is supplied as is to the main memory for access, and if this continuity is lost, It is configured to supply an access address received from a peripheral device to the main storage device under firmware control for access.

In other words, the channel device of the present invention focuses on the continuity of access addresses, which means that accesses to the main memory are often made on consecutive addresses in a relatively large unit. By setting the address in the address register via firmware only when address continuity is lost, instead of setting all of the addresses in the address register by firmware, channel 1fdl? This reduces the number of times the wholesale firmware starts up, reducing the load and reducing memory access time.

FIG. 1 is a block diagram showing the configuration of an electronic computer system including a channel device according to an embodiment of the present invention. A direct channel interface 5 is provided to connect the device 1 and the peripheral device 4.

The channel device 1 includes a channel control section 10, a channel adapter section 20, and a data transfer control section 30. The channel adapter section 20 includes an address/command storage register 21 that stores main memory addresses and read/write commands transferred from the peripheral device 4 via the direct channel interface 5, and an address/command storage register 21 that stores received data from the peripheral device 4. In addition to a reception data storage register 22 for storing data to be sent to the peripheral device 4 and a transmission data storage register 23 for storing data to be sent to the peripheral device 4, an address mismatch detection circuit 24 is provided. The data transfer control unit 3o includes an address sending circuit 31 that sends read/write access addresses to the main storage device 3, and temporarily holds data written to the main storage device 3 and data read from the main storage device 3. The data buffer 32 is provided with a data buffer 32.

Address mismatch detection circuit 2 in channel adapter section 2o
4, as illustrated in the block diagram of FIG. 2, an address increment circuit 41 increments the previous main memory address stored in the address/command storage register 21, and stores this incremented main memory address. address register 42,
An address comparison circuit 43 that compares the current main memory address stored in the address/command storage register 21 and the main memory address stored in the address register 42, and when the result of this address comparison does not match, the channel; An interrupt flip that generates an interrupt in part 10
A flop (F/F) circuit 44 is provided.

A transfer cycle on the direct channel interface 5 consists of an address/command cycle and a data cycle, as shown in the time chart of FIG. The address/command cycle is started when the peripheral device 4 issues an address/command takeover request to the channel device 1, and when the channel device 1 sends an address/command takeover completion notification to the peripheral device 4. finish. A data cycle is started by a request for data acquisition processing from the peripheral device 4, and when the channel device 1 completes the acquisition of data from the peripheral device 4 (in the case of a write command), or when the channel device 1 completes the acquisition of data from the peripheral device 4. Each process ends when the peripheral device 4 completes taking over (in the case of a lead cloak).

Upon receiving an input/output request from the central processing unit 2, the channel control unit 10 in the channel device 1 controls the channel adapter unit 2.
The peripheral device 4 is activated via 0.

The activated peripheral device 4 sends a read/write command for the address of the main memory device 3 and a request for taking over the address on the direct channel interface 5 in order to transfer data between the main memory device 3 and the main memory device 3. do. When the channel adapter unit 20 of the channel device 1 receives this address/command takeover request, it takes in the address and command on the direct channel interface 5 into the address/command storage register 21 (time A in FIG. 3). .

Address comparison circuit 43 in address mismatch detection circuit 24
compares the address taken into the address/command storage register 21 with the address in the address register 42. The address comparison circuit 43 activates the channel control firmware of the channel control unit 10 by setting an interrupt flip-flop (F/F) 44 and generating an interrupt signal on the signal line 45 when the comparison result does not match. do.

When the firmware of the channel control unit 10 receives the above-mentioned interrupt, the firmware of the channel control unit 10 connects the signal line 4 in the address mismatch detection circuit 24.
6, transfers the read address to the address output path 31 in the data transfer control unit 30, and notifies the channel adapter unit 20 of the end of the transfer of this address. . The address sending circuit 31 sets the address received from the channel control unit 10 in the address counter 31a. On the other hand, the channel adapter section 20, which has received the notification of completion of address transfer from the channel control section 10, transfers the address in the address/command storage register 21 to the address mismatch detection circuit 24.
The incremented address is incremented by the address increment circuit 41 in the address register 42 (at time B in FIG. 3).
), notifies the peripheral device 4 of completion of address/command takeover.

Peripheral device 4, which has received this notification of data collection completion, sends a data collection processing request to channel device 1.

When the read/write command in the address/command storage register 21 is write, the channel adapter section 20 of the channel device W1 takes in the write data transferred from the peripheral device 4 into the received data storage register 22, and stores the data. A request is made to the transfer control unit 30 to write the received data. The data transfer control unit 30 is connected to the channel adapter unit 20
The data buffer 32 receives the write data stored in the received data storage register 22 in the address sending circuit 31, and writes it to the address in the main memory 3 specified by the address counter 31a in the address sending circuit 31.

When the writing of one word of data is completed, the data transfer control section 30 increments the address counter 31a in the address sending circuit 31 (time point CZ in FIG. 3).

On the other hand, if the read/write command stored in the address/command storage register 21 in the channel adapter section 20 is a read, the channel adapter section 20 controls data transfer to read data from the main memory device 3. Department 30.

Upon receiving this read request, the data transfer control unit 30 reads one word of data from the address of the main storage device 3 specified by the address counter 31a in the address sending circuit 31, and increments the address counter 31a (third Time point C+ in the figure). The data successively output from the main memory device 3 is transferred to the transmission data storage register 23 in the channel adapter section 20 via the data buffer 32, and then received by the peripheral device 4 via the direct channel interface 5.

If the address comparison result performed by the address mismatch detection circuit 24 of the channel adapter section 20 matches,
The address comparison circuit 43 is an interrupt flip-flop 44
is not set, and therefore no interrupt to the channel control firmware described in 10 occurs. In this case, the channel adapter unit 2° immediately notifies the peripheral device 4 of the completion of address/command takeover. The address in the address/command storage register 21 is the address in the address mismatch detection storage 2.
After being incremented by an address increment circuit 41 in 4, it is held in an address register 42 and prepared for comparison with the next main memory access address.

The operations of the peripheral device 4 and the channel device 1 after the peripheral device 4 receives the notification from the channel device 1 that the address/command reception is completed are the same as in the case where the address comparison results do not match.

Data transfer between the peripheral device 4 and the main storage device 3 via the channel device 1 is performed as described above, so as long as the transfer addresses on the main storage device 3 are continuous, no intervention by the channel control firmware is performed. , the data transfer control unit 30 as the main storage address necessary for memory access.
The contents of the address counter 31a in the address sending circuit 31 are supplied to the main storage device 3 as they are.

Above, we have exemplified a configuration in which the main memory address received from the peripheral device is compared with the main memory address received immediately before, which is incremented. Alternatively, the main memory address received from the main memory device may be subtracted from the main memory address received immediately before, and whether or not the difference is in a predetermined step unit is determined. It may be configured to make a determination. In short, any suitable method can be used as long as the continuity of main memory addresses can be monitored.

Effects of the Invention As explained in detail above, the channel device of the present invention has the following effects:
Focusing on the fact that memory accesses from peripheral devices are often performed on consecutive addresses in a certain amount of units, we supply the address to the address sending circuit under firmware control only when the continuity of access addresses is lost. This configuration reduces the chance of channel control firmware intervention, reducing the load on channel control firmware and reducing address/command takeover time (address/command cycle time).
This has the effect of shortening the time and speeding up data transfer.

[Brief explanation of drawings]

FIG. 1 is a block diagram illustrating the configuration of an electronic computer system including a channel device according to an embodiment of the present invention, and FIG. 2 is a block diagram illustrating the configuration of an address mismatch detection circuit 24 in the channel device 1 of FIG. 1. , FIG. 3 is a timing chart illustrating a procedure for transmitting signals on the direct channel interface 5 of FIG. ■...Channel device, 3...Main storage device, 4...Peripheral device, 5...Direct channel interface, 10
...Channel control section, 20...Channel adapter section, 2
1. Address/command storage register, 22. Reception data storage register, 23. Transmission data storage register, 24. Address mismatch detection circuit, 30. Data transfer control unit, 31. Address sending circuit, 31a.・Address counter, 41...Address increment circuit, 42...Address register that holds the incremented address, 43...
Address comparison circuit, 44... interrupt flip-flop.

Claims (1)

[Claims] It is installed between the main memory device and peripheral devices in a computer system, and accesses the main memory device according to the main memory access address and access type received from the peripheral device, and sends and receives access data to and from the peripheral device. A channel device that increments the access address each time it supplies an access address to the main memory, monitors the continuity of the main memory access addresses received from peripheral devices, and maintains this continuity. If the continuity is lost, the incremented access address is supplied to the main memory for access, and if this continuity is lost, the access address received from the peripheral device is transferred to the main memory under firmware control. A channel device characterized in that it supplies and accesses.