JP2724797B2 - Direct memory access system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a FIFO (First InFirst) for sequentially storing data.
The present invention relates to a direct memory access (DMA) system that transfers data between an out memory and a normal memory such as a main memory without using a CPU.

[0002]

2. Description of the Related Art One of the DMA transfer systems is a dual address mode. This is because the address of the transfer source device is output in the first bus cycle, and a dedicated register (hereinafter referred to as a temporary register) for holding DMA transfer data provided in the DMA controller from the transfer source device is provided.
, The address of the transfer destination device is output in the next bus cycle, and the data is transferred from the temporary register to the transfer destination device.

FIG. 11 is a block diagram of a conventional DMA system using such a DMA transfer system and having a processing bit width of 8 bits, where 1 is a DMA transfer control unit, 1-1 is a control unit, 1-2 is an 8-bit temporary register, 1-3 is a bus interface section, 1-4 is an 8-bit data bus, 1-5 is a write signal of the temporary register 1-2, and 1-6 is a write signal of the bus interface section 1-3. Control signal 2, 4-byte FIFO memory, 2-1 to 2
-4 is four 8-bit data storage areas in the FIFO memory 2, 3 is a peripheral device, 4 is a memory, 4-1 to 4-4 are four continuous 8-bit data storage areas in the memory 4, 5
Is an 8-bit data bus, 6 is a DMA request signal, 7 is DM
A permission signal 8 is a serial or parallel data line.

Here, an example will be described in which the DMA request generation condition of the FIFO memory is a 4-byte data full reception from a peripheral device and a transmission data empty to the peripheral device. FIG. 12 is a state transition diagram showing the outline of the operation of the control unit 1-1.
r indicates a read state, and Sw indicates a write state. FIG. 13 is a timing chart of the DMA transfer from the FIFO memory 2 to the memory 4, and FIG.
5 is a timing chart of DMA transfer to the FO memory 2.

Next, referring to FIG. 11 to FIG.
The DMA transfer operation from the memory 2 to the memory 4 will be described. First, the control unit 1-1 of the DMA transfer control unit 1
Since there is no MA request (DMAREQ), it is in an idle state (Si in FIG. 12). Next, the FIFO memory 2 receives data from the peripheral device 3 through the data line 8 and stores the data in the storage area 2.
-1, 2-2,... Are sequentially stored. When four bytes of data are received, a DMA request signal 6 (DMAREQ) is asserted to the DMA transfer control unit 1. When the DMA request signal 6 is asserted, the DMA transfer control unit 1 acquires a bus right from a bus master such as a CPU, and then asserts a DMA permission signal 7 (DMAACK) to the FIFO memory 2 (DMA permission signal 7). Asserts the FIFO memory 2 confirms the acceptance of the DMA request) and starts the DMA transfer operation.
Reads 8-bit data from the FO memory 2 (FIG. 12)
Sr).

At this time, the FIFO memory 2 sets the read address to the address of the storage area 2-1 by itself. The data input to the DMA transfer control unit 1 through the bus 5 passes through the bus interface unit 1-3 and the bus 1-4, and is input to the temporary register 1-2 by the write signal 1-5 from the control unit 1-1. Is stored. DMA
Subsequently, the transfer control unit 1 accesses the memory 4 and transfers the 8-bit data of the temporary register 1-2 to the bus 1-.
4, writing to a predetermined storage area (4-1) of the memory 4 through the bus interface section 1-3 and the bus 5 (FIG. 1)
2 Sw).

The FIFO memory 2 keeps asserting the DMA request signal 6 until all four bytes of data are read, and negates the DMA request signal 6 when the DMA permission signal 7 for the last data is asserted. When the DMA request signal 6 is negated, the DMA transfer control unit 1 completes the corresponding transfer, enters an idle state, and releases the bus right to a bus master such as a CPU. Hereinafter, the same operation as described above is repeated for data reception of the FIFO memory 2 from the peripheral device 3. FIG. 13 shows that the DMA method
The storage areas 2-1 and 2- of the FIFO memory 2 according to the request
2 shows a case where data of 2, 2-3 and 2-4 are sequentially transferred to four storage areas 4-1 4-2, 4-3 and 4-4 in the memory 4, respectively.

Next, a DMA transfer operation from the memory 4 to the FIFO memory 2 will be described with reference to FIGS. 11, 12 and 14. First, the control unit 1-1 of the DMA transfer control unit 1 is in an idle state (Si in FIG. 14) because there is no DMA request (DMAREQ) at first. Since there is no data to be transferred to the peripheral device 3 (data empty), the FIFO memory 2 asserts the DMA request signal 6 to the DMA transfer control unit 1. The DMA transfer control unit 1 starts a DMA transfer operation after acquiring a bus right from a bus master such as a CPU, and reads 8-bit data in a predetermined storage area (4-1) of the memory 4. (Sr in FIG. 12).

At this time, the data input through the bus 5 passes through the bus interface section 1-3 and the bus 1-4, and is input to the temporary register 1-2 by the write signal 1-5 from the control section 1-1 and stored. Is done. Then DMA
The transfer control unit 1 accesses the FIFO memory 2 and
The DMA enable signal 7 is asserted, and the 8-bit data of the temporary register 1-2 is written to the FIFO memory 2 through the bus 1-4, the bus interface unit 1-3, and the bus 5 (Sw in FIG. 12).

At this time, the FIFO memory 2 sets its own write address to the address of the storage area 2-4. FIF
The O memory 2 keeps asserting the DMA request signal 6 until all 4 bytes of data have been written, the data is written in the order of the storage units 2-4, 2-3, 2-2, 2-1 and the last data When the DMA permission signal 7 is asserted, the DMA request signal 6 is negated. When the DMA request signal 6 is negated, the DMA transfer control unit 1 completes the corresponding transfer, enters an idle state, and releases the bus right to a bus master such as a CPU. FIG. 14 shows four storage areas 4- in the memory 4 in response to a DMA request by the above-mentioned DMA method.
The figure shows a case where data of 1, 4-2, 4-3, and 4-4 are sequentially transferred to storage areas 2-4, 2-3, 2-2, and 2-1 of the FIFO memory 2, respectively.

[0011]

In the conventional DMA system configured as described above, as can be seen from FIGS. 13 and 14, each cycle of the DMA transfer has an FIF.
There is a problem that the bus operation for reading or writing to the O memory 2 is always performed, and the bus use efficiency is low.

The present invention has been made to solve such a problem, and a FIFO is used in accordance with the contents of transfer data.
It is an object of the present invention to provide a DMA system that improves bus use efficiency by omitting a bus access to a memory.

[0013]

A DMA according to the first invention
The system includes a buffer for storing the same data as the data to be transferred to the memory, and a comparator provided with a comparator for comparing the data to be transferred to the next memory with the data in the buffer.
An O memory and a control unit that, when the comparison result of the comparator of the FIFO memory matches, eliminates the bus operation for reading data from the FIFO memory and transfers the previous transfer data to the memory as the current transfer data. It is characterized by the following.

According to a second aspect of the present invention, there is provided a DMA system including a buffer in which data can be set in advance, and a comparator provided with a comparator for comparing data to be transferred to the next memory with setting data in the buffer; A buffer in which the same data as the setting data of the buffer is set in advance is provided. If the comparison result by the comparator of the FIFO memory matches, the bus operation for reading data from the FIFO memory is omitted and the setting data of the own buffer is omitted. And a control unit for transferring the data to the memory as the current transfer data.

[0015] A DMA system according to a third aspect of the present invention provides a buffer for storing the same data as transfer data from a memory;
And a comparator for comparing the data to be transferred next with the data stored in the buffer, and a control unit for omitting a bus operation for writing data to the FIFO memory when the comparison result by the comparator matches, A FIFO memory for storing the same data as the transfer data of the controller, and storing the previous transfer data stored in its own buffer as the current transfer data when the comparison result by the comparator of the control unit matches. It is characterized by having.

A DMA system according to a fourth aspect of the present invention is provided with a buffer in which data can be set in advance, and a comparator for comparing data to be transferred next from the memory with data set in the buffer. If a match is found, a control unit that eliminates the bus operation for writing data to the FIFO memory and a buffer in which the same data as the setting data of the buffer of the control unit are set in advance are provided. When they match, a FIFO memory for storing the setting data of the own buffer as the current transfer data is provided.

[0017]

The DMA system according to the first invention has a FIFO
Each time data is transferred from memory to memory, the same data as the transfer data is stored in the FIFO memory buffer, and the next transfer data is compared with the previous transfer data by the FIFO memory comparator. If the transfer data is the same as the previous transfer data, the control unit
By omitting the bus operation for reading data from the FO memory,
The previous transfer data in the control unit is transferred to the memory as the current transfer data, and the bus access to the FIFO memory when the same data is continuously transferred is omitted.

[0018] The DMA system according to the second invention has a FI
The same data that is expected to have a high transfer frequency is set in the buffer of the FO memory and the buffer of the control unit, and the next transfer data is compared with the set data of the buffer by the comparator of the FIFO memory. If the current transfer data is the same as the setting data of the buffer of the FIFO memory, that is, the setting data of the buffer of the control unit, the control unit
The bus operation for reading data from the O memory is omitted, the setting data in the buffer of the control unit is transferred to the memory as the current transfer data, and the same data as the previously set data is transferred to the FIFO memory. Omit bus access.

In the DMA system according to the third aspect of the invention, every time data is transferred from the memory to the FIFO memory, the same data as the transfer data is stored in the buffer of the control unit.
The same data is stored in a buffer of the FIFO memory, and as a result of comparing the next transfer data with the previous transfer data by the comparator of the control unit, if the current transfer data is the same as the previous transfer data, the control unit Eliminates the bus operation for writing data to the FIFO memory, and the FIFO memory stores the previous transfer data in its own buffer as the current transfer data.
The bus access to the IFO memory is omitted.

In the DMA system according to the fourth aspect of the present invention, the same data that is expected to have a high transfer frequency is set in the buffer of the control unit and the buffer of the FIFO memory, and the next data is set by the comparator of the control unit. When the current transfer data is the same as the control unit setting data, that is, the setting data of the FIFO memory buffer, as a result of comparing the transfer data of Is omitted, the FIFO memory stores the setting data in its own buffer as the current transfer data, and omits a bus access to the FIFO memory when the same data as the preset data is transferred.

[0021]

【Example】

Embodiment 1 FIG. FIG. 1 is a block diagram of a first embodiment of the DMA system according to the present invention. In the figure, the same parts as those of the conventional example shown in FIG. In the figure, 9 is a DMA transfer control unit, 9-1 is a control unit, 10 is a 4-byte FIFO memory, 10-1 is an 8-bit data storage unit, 10-2 is an 8-bit data comparator, 1
0-3 and 10-4 are 8-bit data buses, and 11 is an output signal of the comparator 10-2. FIG. 2 shows the control unit 9-
FIG. 4 is a state transition diagram schematically showing the operation of No. 1, where Sra indicates a read state (pseudo read state) without a bus operation.
Further, FIG. 3 shows that the D
It is a timing chart of MA transfer.

Next, the operation will be described. First, the control unit 9-1 of the DMA transfer control unit 9 first issues a DMA request (DMAR
Since there is no EQ), it is in an idle state (Si in FIG. 2).
Next, the FIFO memory 10 receives data from the peripheral device 3 through the data line 8, and stores the data in the storage areas 2-1, 2-2,... When receiving the data of 4 bytes, it asserts the DMA request signal 6 to the DMA transfer control unit 9. After acquiring the bus right from the bus master such as the CPU, the DMA transfer control unit 9 asserts the DMA permission signal 7 (DMAACK) to the FIFO memory 10 and starts the DMA transfer operation, and the storage area of the FIFO memory 10 2-1 to 8-bit data is read (FIG. 2
Sr).

At this time, the FIFO memory 10
The data read by the A transfer control unit 9 is also stored in the storage unit 10-1 via the bus 10-3. D through bus 5
The data read by the MA transfer control unit 9 passes through the bus interface unit 1-3 and the bus 1-4, and is written by the write signal 1-5 from the control unit 9-1.
2 and stored. The DMA transfer control unit 9 subsequently accesses the memory 4 and sets the temporary register 1
The -2 8-bit data is written to a predetermined storage area (4-1) of the memory 4 through the bus 1-4, the bus interface 1-3, and the bus 5 (Sw in FIG. 2).

The FIFO memory 10 keeps asserting the DMA request, and compares the data of the storage area 2-2 to be transferred next with the immediately preceding transfer data stored in the storage unit 10-1 by the comparator 10-2. Then, if the result of the comparison is the same, the output signal 11 is asserted together with the DMA request signal 6. The DMA transfer control unit 9 includes a FIFO memory 10
Therefore, if the output signal 11 is asserted, only the DMA permission signal 7 (DMAACK) is asserted to the FIFO memory 10 and the read bus operation is not performed (Sra in FIG. 2). Then, the DMA transfer control unit 9 accesses the memory 4 and transfers the transfer data immediately before being written to the temporary register 1-2 to a predetermined portion of the memory 4 through the bus 1-4, the bus interface unit 1-3, and the bus 5. Write to the storage area (4-2) (Sw in FIG. 2).

FIG. 3 shows that the data in the storage areas 2-1, 2-2, 2-3 and 2-4 of the FIFO memory 10 are stored in the four storage areas 4-1 and 4-
When the data is sequentially transferred to 2, 4-3 and 4-4, the first 3
This shows a case where the two data are the same. As is clear from the figure, the bus operation to the FIFO memory 10 does not occur in the second and third transfers of the same data continuously, so that the bus use efficiency is higher than in the conventional example.

Embodiment 2 FIG. FIG. 4 is a state transition diagram of the control unit 9-1 showing the second embodiment of the DMA system according to the present invention having the configuration shown in FIG. In the first embodiment, the FIFO
When the output signal 11 is asserted by the memory 10, the transfer is performed in the pseudo read state (no bus operation) and the normal write state, whereas in the present embodiment, a dedicated write state different from the normal write state Transfer is performed by Swa. Swa indicates a state in which the write operation to the memory 4 is performed simultaneously with the assertion of the DMA permission signal 7 to the FIFO memory 10. FIG.
The storage areas 2-1 and 2 of the FIFO memory 10 according to the request
When the data of -2, 2-3, and 2-4 are sequentially transferred to the four storage areas 4-1, 4-2, 4-3, and 4-4 in the memory 4, the first three data are The situation when they are the same is shown. As is clear from the figure, the responsiveness of the transfer to the DMA request is improved as compared with the first embodiment.

Embodiment 3 FIG. FIG. 6 is a block diagram of a third embodiment of the DMA system according to the present invention. In the figure,
11 and FIG. 1 are denoted by the same reference numerals, and description thereof is omitted. In the figure, reference numeral 12 denotes a DMA transfer control unit;
-1 is a control unit, 12-2 is an 8-bit data storage unit, 12
-3 is a selector, 12-4 and 12-5 are 8-bit data buses, 12-6 is a select signal, and 13 is a 4-byte FIF
O memory 13-1 is an 8-bit data storage unit.

Next, the operation will be described. First, the storage unit 12-2 of the DMA transfer control unit 12 and the FIFO memory 13
The same data that is expected to have a high transfer frequency is set in advance in the storage unit 13-1. The control unit 12-1 of the DMA transfer control unit 12 first issues a DMA request (DMARE).
Since there is no Q), it is in an idle state (Si in FIG. 2). Next, the FIFO memory 13 is connected to the peripheral device 3 through the data line 8.
, And stores the data in the order of the storage areas 2-1, 2-2,.... When receiving 4 bytes of data, D
The DMA request signal 6 is asserted to the MA transfer control unit 12. After acquiring the bus right from the bus master such as the CPU, the DMA transfer control unit 12 asserts the DMA permission signal 7 (DMAACK) to the FIFO memory 13, but the FIFO memory 13 is stored in the storage unit 13-1. The comparator 10-3 compares the set data with the data to be transferred next stored in the storage area 2-1. If the comparison result is the same, the output signal 1 is output together with the DMA request signal 6.
Assert 1.

If the output signal 11 from the FIFO memory 13 is asserted, the DMA transfer control unit 12
O memory 13 with DMA permission signal 7 (DMAAC
K) is only asserted and the read bus operation is not performed (Sra in FIG. 2). The DMA transfer control unit 12 subsequently accesses the memory 4, but at this time, the FIFO memory 1
If the output signal 11 from 3 is asserted, the storage unit 1
2-2 data, and FI if not asserted
By performing a read bus operation on the FO memory 13, the data stored in the temporary register 1-2 is selected by the selector 12-3 and the select signal 12-6, and the bus 12-5 and the bus interface section 1-3 are selected. Then, the data is written to a predetermined storage area (4-1) of the memory 4 through the bus 5 (Sw in FIG. 2).

Embodiment 4 FIG. In the present embodiment, the control unit 12-1 of the DMA system having the configuration of the third embodiment performs transfer in a pseudo read state (no bus operation) and a normal write state when the output signal 11 is asserted. Unlike the third embodiment, a dedicated write state Sw similar to the second embodiment is used.
The transfer is performed by a. That is, the FIFO 13
When the output signal 11 is asserted, a write operation to the memory 4 is performed simultaneously with the assertion of the DMA permission signal 7 to the FIFO memory 13.

Embodiment 5 FIG. FIG. 7 is a block diagram of a fifth embodiment of the DMA system according to the present invention. In FIG. 1, FIG.
1 and the same parts as those in FIG. In the figure, reference numeral 14 denotes a DMA transfer control unit;
1 is a control unit, 14-2 is an 8-bit data comparator, 14-
3 is an 8-bit data storage unit, 14-4 and 14-5 are 8-bit data buses, 14-6 is a write signal, 14-7 is an output signal of the comparator 14-2, 15 is a 4-byte FIFO memory, and 15- 1 is an 8-bit data storage unit, 15-2 is a selector, 15-3 and 15-4 are 8-bit data buses, 16
Is an output signal from the control unit 14-1. FIG. 8 is a state transition diagram showing an outline of the operation of the control unit 14-1, and Swb shows a write state (pseudo write state) without a bus operation. Furthermore, FIG.
5 is a timing chart of a DMA transfer to the memory 15;

Next, the operation will be described. The control unit 14-1 of the DMA transfer control unit 14 first issues a DMA request (DMAR
Since there is no EQ), it is in an idle state (Si in FIG. 8).
The FIFO memory 15 asserts the DMA request signal 6 to the DMA transfer control unit 14 because there is no data to be transmitted to the peripheral device 3 via the data line 8 (transmission data empty). When the DMA request signal 6 is asserted, the DMA transfer control unit 14 acquires a bus right from a bus master such as a CPU and then starts a DMA transfer operation.
The 8-bit data in the predetermined storage area (4-1) is read (Sr in FIG. 8). At this time, the data read through the bus 5 is transmitted to the bus interface section 1-3 and the bus 1-
4 and is input to and stored in a temporary register 1-2 by a write signal 1-5.

The DMA transfer control unit 14 stores the FIFO memory 1
5, the DMA enable signal 7 is asserted, and the 8-bit data of the temporary register 1-2 is transmitted through the bus 1-4, the bus interface unit 1-3, the bus 5, the selector 15-2, and the bus 15-4. FIFO
Writing to the storage area 2-4 of the memory 15 (S in FIG. 8)
w). At this time, the FIFO memory 15 stores the same data as the write data in the storage unit 15-1, and the DMA transfer control unit 14 transmits the 8-bit data of the temporary register 1-2 through the bus 14-4 and outputs the write signal 14 -6 to the storage unit 14-3 for storage. FIFO memory 1
5 keeps asserting the DMA request signal 6 until the remaining 3 bytes of data are written.

Next, the DMA transfer control unit 14 reads the second 8-bit data from the storage area 4-2 of the memory 4 to the temporary register 1 # 2 similarly to the first data. The comparison with the immediately preceding transfer data stored in the unit 14-3 is performed by the comparator 14-2.
If the result of the comparison is the same, the output signal 14-7 to the control unit 14-1 is asserted. The DMA transfer control unit 14 continues to perform a write operation to the FIFO memory 15, but if the above comparison results are the same, the DMA transfer control unit 14 only asserts the output signal 16 together with the DMA enable signal 7 to the FIFO memory 15 and stops the bus operation. Not performed (Swb in FIG. 8). F
When the output signal 16 from the DMA transfer control unit 14 is asserted together with the DMA permission signal 7, the IFO memory 15
The immediately preceding transfer data stored in the storage unit 15-1 is selected by the selector 15-2 through the bus 15-3, and is stored in its own storage area 2-3 through the bus 15-4.

FIG. 9 shows four storage areas 4-1 and 4-2 in the memory 4 in response to a DMA request by the above-mentioned DMA method.
When the data from 4-3 and 4-4 are sequentially transferred to the storage areas 2-4, 2-3, 2-2 and 2-1 of the FIFO memory 15, the first three data are the same. The state of the case is shown. As is clear from the figure, when the same data continues, the bus operation to the FIFO memory 15 does not occur, and the bus use efficiency is higher than in the conventional example.

Embodiment 6 FIG. FIG. 10 is a block diagram of a sixth embodiment of the DMA system according to the present invention. FIG.
1 and FIG. 7 are denoted by the same reference numerals, and description thereof is omitted. In the figure, reference numeral 17 denotes a DMA transfer control unit, 17-1.
Is a control unit, 17-2 is an 8-bit data storage unit, 18 is 4
The byte FIFO memory 18-1 is an 8-bit data storage unit.

Next, the operation will be described. First, the storage unit 17-2 of the DMA transfer control unit 17 and the FIFO memory 18
The same data is stored in advance in the storage unit 18-1. The control unit 17-1 of the DMA transfer control unit 17 is in an idle state (Si in FIG. 8) because there is no DMA request (DMAREQ) at first. The FIFO memory 18 asserts the DMA request signal 6 to the DMA transfer control unit 17 because there is no data to be transmitted to the peripheral device 3 via the data line 8 (transmission data empty). When the DMA request signal 6 is asserted, the DMA transfer control unit 17
After acquiring the bus right from the bus master or the like, the DMA transfer operation is started, and the 8-bit data in the predetermined storage area (4-1) of the memory 4 is read (Sr in FIG. 8). At this time, the comparator 14-5 compares the read data with the setting data of the storage unit 17-2 at the same time, and asserts the output signal 14-7 to the control unit 17-1 if the comparison result shows the same.

Next, the DMA transfer control unit 17 performs a write operation to the FIFO memory 18. When the comparison results are the same, the DMA transfer control unit 17 asserts the output signal 16 to the FIFO memory 18 together with the DMA permission signal 7. Only the bus operation is not performed (Swb in FIG. 8). FIFO memory 18
When the output signal 16 is asserted together with the DMA permission signal 7, the selector 15-2 selects the setting data stored in the storage unit 18-1 through the bus 15-3 by the selector 15-2,
The data is stored in its own storage area 2-4 through the bus 15-4. Therefore, when the same data continues, a bus operation to the FIFO memory 18 does not occur, and the bus use efficiency is higher than in the conventional example.

In the above embodiment, a DMA system having a processing bit width of 8 bits has been described as an example, but the processing bit width is not limited to 8 bits. The DMA system of the present invention can be similarly applied to a system in which the DMA transfer control unit performs data assembly using 32 bits or the like.

Further, the number of buffers provided in the DMA transfer control unit and the FIFO memory for setting values in advance is not limited to one.

Further, the DMA system may be built in the chip or external.

[0042]

As described above, the DMA system of the present invention improves the DMA transfer efficiency when the transfer data is continuously the same or when the transfer data includes a large amount of the same data. It has an excellent effect of increasing the processing capacity.

[Brief description of the drawings]

FIG. 1 is a block diagram of Embodiments 1 and 2 of a DMA system according to the present invention.

FIG. 2 is a state transition diagram of a control unit in the first and third embodiments of the DMA system of the present invention.

FIG. 3 is a timing chart of DMA transfer in the first and third embodiments of the DMA system of the present invention.

FIG. 4 is a state transition diagram of a control unit in Embodiments 2 and 4 of the DMA system according to the present invention.

FIG. 5 is a diagram showing D in Embodiment 2 of the DMA system of the present invention;
It is a timing chart of MA transfer.

FIG. 6 is a block diagram of Embodiments 3 and 4 of a DMA system according to the present invention.

FIG. 7 is a block diagram of Embodiment 5 of the DMA system of the present invention.

FIG. 8 is a state transition diagram of a control unit in the fifth and sixth embodiments of the DMA system of the present invention.

FIG. 9 is a timing chart of the DMA transfer in the fifth and sixth embodiments of the DMA system of the present invention.

FIG. 10 is a block diagram of a sixth embodiment of the present invention.

FIG. 11 is a block diagram of a conventional DMA system.

FIG. 12 is a state transition diagram of a control unit in a conventional DMA system.

FIG. 13 is a timing chart of a DMA transfer from a FIFO memory to a memory in a conventional DMA system.

FIG. 14 is a diagram showing a configuration of a conventional DMA system from memory to F;
4 is a timing chart of a DMA transfer to an IFO memory.

[Explanation of symbols]

 1-2 8-bit temporary register 1-3 Bus interface section 1-4 8-bit data bus 1-5 Write signal 1-6 Bus interface section control signal 2-1 to 2-4 8-bit data storage area 3 Peripheral device 4 8 Bit data width memory 4-1 to 4-4 8-bit storage area 5 8-bit data bus 6 DMA request signal 7 DMA enable signal 8 Data line 9 DMA transfer control section 9-1 Control section 10 4-byte FIFO memory 10-1 8 Bit data storage unit 10-2 8-bit data comparator 10-3, 4-bit data bus 11 Output signal 12 DMA transfer control unit 12-1 Control unit 12-2 8-bit data storage unit 12-3 Selector 12-4, 5 8-bit data bus 12-6 select signal 13 4-byte FIFO memory 13-1 8-bit data storage Storage unit 14 DMA transfer control unit 14-1 Control unit 14-2 8-bit data comparator 14-3 8-bit data storage unit 14-4, 58-bit data bus 14-6 Write signal 14-7 Output signal 15 4 bytes FIFO memory 15-1 8-bit data storage unit 15-2 Selector 15-3, 4-bit data bus 16 Output signal 17 DMA transfer control unit 17-1 Control unit 17-2 8-bit data storage unit 18 4-byte FIFO memory 18 -1 8-bit data storage unit

Claims (4)

(57) [Claims] In a direct memory access system for transferring data to a memory without the intervention of a CPU, each time data is transferred to a memory, a buffer for temporarily storing the same data as the transferred data, and A FIFO memory provided with a comparator for comparing data to be transferred to the memory with data stored in the buffer;
A control unit for omitting a bus operation for reading data from the FIFO memory and transferring the previous transfer data to the memory as the current transfer data to the memory when the comparison result by the comparator of the memory matches; A direct memory access system, characterized in that: 2. In a direct memory access system for transferring data to a memory without the intervention of a CPU, a buffer in which data can be set in advance and data to be subsequently transferred to the memory are compared with data set in the buffer. A FIFO memory provided with a comparator and a buffer in which the same data as the setting data of the buffer of the FIFO memory are set in advance are provided. If the comparison result by the comparator of the FIFO memory matches, the FIFO memory is used.
A direct memory access system, comprising: a control unit that transfers setting data of its own buffer to the memory as current transfer data by omitting a bus operation for reading data from the memory. 3. A direct memory access system in which data is transferred from a memory without the intervention of a CPU, each time data is transferred from a memory, a buffer for temporarily storing the same data as the transfer data, and A comparator for comparing data to be transferred from the memory with data stored in the buffer; a control unit for omitting a bus operation for writing data to the FIFO memory when the comparison result by the comparator matches; Each time the data transfer is performed, a buffer for temporarily storing the same data as the transfer data is provided. If the comparison result by the comparator of the control unit matches, the transfer from the previous memory stored in its own buffer is performed. A FIFO memory for storing data as current transfer data. Access system. 4. In a direct memory access system for transferring data from a memory without using a CPU, a buffer in which data can be set in advance and data to be transferred from the next memory are compared with data set in the buffer. A comparator is provided, and when the comparison result by the comparator matches, a control unit for omitting a bus operation for writing data to the FIFO memory, and the same data as the setting data of the buffer of the control unit are preset. A buffer provided with a FIFO memory for storing the setting data of its own buffer as the current transfer data when the comparison result by the comparator of the control unit matches; system.