JPH10116245A - DMA controller - Google Patents

Abstract

(57) [PROBLEMS] To provide a DMA control device for controlling data transfer from a transfer source to a transfer destination based on DMA information, capable of acquiring DMA information without lowering the data transfer speed,
Further, by providing a means for performing the DMA transfer twice by activating the DMA once, the processing time of the entire DMA transfer can be reduced. By using a dedicated bus for DMA information acquisition or by acquiring a bus for data transfer utilizing interruption of data transfer, data transfer by one DMA information is performed by DMA information acquisition means (1). The next DMA information is acquired on the way. The notification means 6 monitors the preparation / non-preparation of data in the local buffer 5, and
Two DMAs, a DMA from the transfer source to the local buffer 5 and a DMA from the local buffer 5 to the transfer destination, are controlled by a single DMA activation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DMA control device for transferring data without using a CPU in a computer system or the like.

2. Description of the Related Art DMA (Direct Memory Access) is data transfer performed between a main memory and an input / output adapter without using a CPU. According to the DMA, data transfer can be performed efficiently.
It is intended to shorten the overall transfer processing time including the A information.

[0003]

2. Description of the Related Art In order to perform DMA, DMA information such as a transfer source address, a transfer destination address, and a transfer amount is required, and a DMA controller performs data transfer based on the information. This DMA information is stored in a register or stored in a memory. However, when a plurality of pieces of DMA information are acquired and DMA transfer is performed a plurality of times by one DMA activation, that is, when the DMA transfer is linked in a chain. In such a case, since the data amount of the DMA information changes depending on the number of times of the DMA transfer, it is generally placed on a memory.

[0004] DMA transfer is performed in the following procedure. Acquire DMA information. Acquire transfer data from transfer source address. Normally, the transfer source address is incremented with the transfer of data, but the transfer source may be a fixed address such as a FIFO.

The transfer data is output to a transfer destination address. Normally, the transfer destination address is incremented with the transfer of data, but the transfer destination may be a fixed address such as a FIFO.

[0006] When the DMA transfer is linked by a chain, the procedure is repeated again after the above procedure.

[0007]

Conventionally, when DMA transfers are linked by a chain, after the data transfer using one piece of DMA information is performed, the next DMA information is obtained, and the transfer process is repeated in the same manner. Was. Since the acquisition of DMA information and the actual data transfer are alternately repeated, the DMA
When information is acquired, data cannot be transferred, and if it takes time to acquire DMA information, there is a problem that the overall data transfer speed is reduced.

In a network adapter or the like for connecting a public line or the like, the communication speed on the line side is considerably lower than the speed of an IO bus (input / output bus).
Since the efficiency of the IO bus side deteriorates due to reasons such as transfer in units of bytes, the transfer data is temporarily stored in a local buffer, then transferred to the IO bus at a time (at the time of reception), or transferred from the IO bus. In many cases, the data accumulated in the local buffer is transferred little by little to the line side (at the time of transmission).

In this case, two transfers, data transfer to the local buffer and data transfer from the local buffer, occur. However, after the transfer from the transfer source to the local buffer is completed, the transfer from the local buffer to the transfer destination is performed. Therefore, it is necessary to restart the DMA from the local buffer to the transfer destination after the CPU or the like confirms the end of the transfer to the local buffer by using an interrupt or the like, which takes a long processing time. Was.

The present invention has been made to solve the above problems, and firstly, to provide a means for acquiring DMA information which does not lower the data transfer rate. Secondly, once the DMA is started even when a local buffer is used. Therefore, it is an object of the present invention to provide a means for performing the DMA transfer twice so that the processing time of the entire DMA transfer can be reduced.

[0011]

FIG. 1 is a block diagram showing the principle of the present invention. FIG. 1A shows an example of a configuration for acquiring DMA information without reducing data transfer, and FIG. This shows an example of a configuration in which transfer can be performed by starting DMA once even when a local buffer is used.

DMA information acquisition means 1 shown in FIG.
Is the next DM during data transfer by one DMA information.
A means for acquiring A information. DMA information holding means 2
Is storage means capable of holding a plurality of pieces of DMA information. The transfer control means 3 controls the data transfer from the transfer source to the transfer destination based on the DMA information held in the DMA information holding means 2. 1 controls to continue the data transfer according to the next DMA information acquired in advance.

As a method for realizing the DMA information acquisition means 1,
For example, there are the following two methods. One is to provide a dedicated bus for acquiring DMA information separately from a bus for transferring data by DMA, and to use the dedicated bus so that the next DMA information can be acquired during data transfer by DMA. It is. In this way, as shown in FIG. 1 (A1), the second DMA information is acquired during the data transfer by the first DMA information, and immediately after the first data transfer is completed, the second DMA information is obtained. Can start data transfer.

Another method is as shown in FIG. 1 (A2). For example, in data transfer to a network adapter or the like, the communication speed on the line side is slower than the communication speed of the IO bus, so that there is a gap between data transfer and data transfer. That is, in the data transfer based on the first DMA information, as shown in FIG. 1 (A2), the data transfer bus is used by utilizing the idle time generated between the actual data transfer and the data transfer. By the next DM
Acquire A information.

The transfer control means 4 shown in FIG.
A storage unit (not shown) for holding the A information, a local buffer 5 for DMA data transfer, a notifying unit 6 for notifying whether data of a DMA transfer source is ready on the local buffer 5, When the notifying unit 6 notifies that the data is not ready, the stopping unit 7 for stopping the DMA transfer from the local buffer 5 to the transfer destination and the notifying unit 6 are notified that the data is ready. Then, D from the local buffer 5 to the transfer destination
Resuming means 8 for resuming MA transfer.

The transfer control means 4 directly recognizes the end of the data transfer from the DMA transfer source to the local buffer 5, and
The DMA from the local buffer 5 to the transfer destination is stopped by the stop means 7 until the data transfer is completed and the transfer source data is ready. When the data is ready on the local buffer 5, the DMA to the transfer destination is prepared. Is restarted by the restart means 8. By performing such control, two DMA transfers can be controlled by one DMA activation.

The notifying means 6 is, for example, a predetermined control information holding means (not shown) indicating that the transfer source data has been prepared.
Alternatively, by checking the control bit provided in the DMA information by polling, it is checked whether or not the transfer source data has been prepared in the local buffer 5 or not. The notification to the means 8 is performed.

[0018]

FIG. 2 shows an example of an application system of the present invention. The present invention is of course, but not limited to, applied to a computer system such as that shown in FIG.

The central processing unit (CPU) 100
A device that fetches and executes instructions. The main memory 101 is a storage device that stores programs and data. The bus bridge 102 includes a CPU bus and an IO bus 10.
3 is an interface device for connecting the C.I. IO bus 1
03 is a bus for transferring input / output data.

The network adapter 104 is connected to the CPU 1
This is an adapter for connecting a computer such as 00 to a network, and performs line control for data transmission / reception to / from the IO bus control unit 105, the local memory 107, and the communication line 110 for transmitting / receiving data to / from the IO bus 103. A network control unit 109 has an internal bus 108 for connecting these.

According to the present invention, the D
The main memory 101 and the local memory 107 in the network adapter 104 are related to the MA control circuit 106 and the like.
DMA control in data transfer from the local memory 107 to the main memory 101,
Alternatively, the main memory 101 and the network control unit 109
DMA of data transfer via local memory 107 between
The control is performed efficiently.

[First Embodiment of DMA Control Circuit] FIG. 3 is a block diagram showing the configuration of the DMA control circuit.
The DMA information holding unit 11 stores a transfer source address, a transfer destination address, a transfer amount (the size of data to be transferred),
When there is information, DMA information including a DMA information address for chaining the DMA information is held. The DMA information holding unit 11 is provided in, for example, the main memory 101 shown in FIG.

The next DMA information acquisition control circuit 10
This is a control circuit for sending an address and a read control signal to the information holding unit 11 to acquire chained DMA information in advance. The read DMA information is transferred via the dedicated bus 23 to the next transfer source address register 12 (transfer source address), the next transfer counter 13 (transfer amount), the next transfer destination address register 14 (transfer destination address), and the next DMA. It is set in the information address register 15 (chain information).

The transfer source address in the next transfer source address register 12, the transfer amount in the next transfer counter 13, the transfer destination address in the next transfer destination address register 14, and the chain information in the next DMA information address register 15 are as follows. DMA
At the start of data transfer, the transfer source address register 16, the transfer counter 17, and the transfer destination address register 1
8. The data is sent to the DMA information address register 19, and data transfer based on one piece of DMA information is started.

The contents of the DMA information address register 19 are sent to the next DMA information acquisition
If the A information exists, it is used to obtain it. The transfer source control circuit 20 reads the transfer source address from the transfer source address register 16 and the transfer amount from the transfer counter 17, and sends the transfer source address and a control signal for requesting data transfer to the transfer source. The transfer source data transmitted above is written into the internal buffer 22 by write control. When the writing is completed, the transfer control circuit 21 is notified of the completion of the data capture.

The transfer destination control circuit 21 is a transfer source control circuit 2
The transfer destination address read from the transfer destination address register 18 and a control signal for data transfer are sent to the transfer destination in response to the notification of the completion of the capture from 0, and the data read from the buffer 22 is sent to the transfer destination by the read control. The transfer completion is notified to the transfer source control circuit 20 and the next DMA information acquisition control circuit 10.

The transfer counter 17 is determined by one piece of DMA information.
Is completed, the next DMA information acquisition control circuit 10 has already transferred the next DMA information to the next transfer source address register 12 and the next transfer counter 1.
3. Since the next transfer destination address register 14 and the next DMA information address register 15 are set, they are transferred to the transfer source address register 16, the transfer counter 17, the transfer destination address register 18, the DMA information address register 19
The transfer source control circuit 20 immediately starts the data transfer based on the next DMA information. Hereinafter, similarly, the DMA data transfer is continued.

FIG. 4 is a block diagram of the transfer source control circuit shown in FIG. In FIG. 4, the transfer address counter 3
0 is a counter to which an address value from the transfer source address register 16 shown in FIG. 3 is set. The address value held by the transfer address counter 30 is incremented by the data fetch unit every time data is fetched from the transfer source.

The transfer counter 31 is a counter for setting the transfer amount from the transfer counter 17 shown in FIG. 3. When data is taken in from the transfer source, the data is decremented by the unit of the data take-in.

The transfer amount determination circuit 32 is a circuit for determining the amount of data to be transferred in one burst transfer. The transfer amount is determined based on the temporary buffer amount, the remaining transfer amount indicated by the transfer counter 31, and the transfer source burst length. The amount is determined, the increment amount of the transfer address counter 30 and the decrement amount of the transfer counter 31 are controlled, and the transfer amount is notified to the transfer source bus control circuit 34 and the transfer destination control circuit 21 shown in FIG.

The transfer source bus acquisition circuit 33 outputs a counter load timing signal to the transfer address counter 30 and the transfer counter 31 in response to a start signal according to a DMA activation instruction from the CPU or the like, and acquires a bus for taking in data. Is output. When a bus grant signal indicating permission for use of the bus arrives in response to the bus request signal, the bus request signal is notified to the transfer source bus control circuit 34.

The transfer source bus control circuit 34 sends the transfer source address, the data size, and the strobe signal from the transfer address counter 30 to the transfer source, and increments the transfer address counter 30 and the transfer counter 31. Outputs a decrement timing signal. When an acknowledgment signal indicating that data has been sent arrives on the bus, the buffer control circuit 35 is notified.

The buffer control circuit 35 outputs a write timing signal and a write address to the buffer 22 shown in FIG. 3, and controls writing of data on the bus to the buffer 22. The buffer control circuit 35 outputs a start signal to the transfer destination control circuit 21 shown in FIG.

FIG. 5 is a block diagram of the transfer destination control circuit shown in FIG. In FIG. 5, the transfer address counter 4
0 is a counter to which an address value from the transfer destination address register 14 shown in FIG. 3 is set. The address value held by the transfer address counter 40 is incremented by the data transfer amount every time data is transferred to the transfer destination.

The transfer counter 41 is a counter for setting the transfer amount of the transfer destination data sent from the transfer amount determination circuit 32 of the transfer source control circuit shown in FIG. 4, and when the transfer of data to the transfer destination is performed. , Is decremented by the data transfer amount.

The transfer amount determination circuit 42 is a circuit that determines the amount of data to be transferred in one burst transfer, and determines the transfer amount based on the transfer amount from the transfer source control circuit 20 and the transfer destination burst length. It controls the increment amount of the transfer address counter 40 and the decrement amount of the transfer counter 41 and notifies the transfer destination bus control circuit 44 of the transfer amount.

The transfer destination bus acquisition circuit 43 receives the start signal from the buffer control circuit 35 of the transfer source control circuit shown in FIG.
1 to output a counter load timing signal.
It outputs a bus request signal for requesting a bus to transfer data. When a bus grant signal indicating permission to use the bus arrives with respect to the bus request signal, the bus grant signal is notified to the transfer destination bus control circuit 44.

The transfer destination bus control circuit 44 outputs the transfer destination address from the transfer address counter 40, the data size, and the strobe signal to the bus, and accordingly, the buffer control circuit 45 changes to the state shown in FIG. By outputting a read timing signal and a read address to the buffer 22, data is read from the buffer 22 and data transfer to the transfer destination is controlled. Buffer control circuit 45
When data transfer from the buffer 22 is completed,
Is output to the transfer source control circuit 20 shown in FIG.

The transfer destination bus control circuit 44 outputs an increment timing signal of the transfer address counter 40 and a decrement timing signal of the transfer counter 41.

FIG. 6 is a block diagram of the next DMA information acquisition control circuit shown in FIG. In FIG. 5, a DMA information start address register 46 is a register in which a start address of the DMA information (an address of the DMA information holding unit 11 shown in FIG. 3) is set before the start of the DMA.
It is used to acquire DMA information used for the first DMA transfer. As shown in FIG.
Are used to acquire chained DMA information other than the first DMA information.

The DMA information holding unit control circuit 47 is a circuit for controlling the reading of DMA information from the DMA information holding unit 11 shown in FIG. From the next time on, reading of the DMA information is controlled by loading the address from the DMA information address register 19 and outputting the address, the strobe signal and the read enable signal.

The address register control circuit 48 includes the next transfer source address register 12 and the next transfer counter 1 shown in FIG.
3. Transfer the contents of the next transfer destination address register 14 and the next DMA information address register 15 to the transfer source address register 1
6, transfer counter 17, transfer destination address register 18,
An address register set timing signal to be transferred to the DMA information address register 19 is output, and the DMA information read from the DMA information holding unit 11 is transferred to the next transfer source address register 12, the next transfer counter 13, the next transfer destination address register 14, the next DMA. Information address register 1
Next, the next address register set timing signal to be set to 5 is output. Thereafter, a start signal is output to the transfer source control circuit 20 shown in FIG.

FIG. 7 is a timing chart showing the operation of each circuit described above. FIG. 7A shows clock edges of a clock signal for controlling the operation timing of each circuit. (B) to (v) are the following signals in the above description, respectively.

(B): DMA start signal (c): DMA information strobe signal (d): next address register set timing signal (e): address register set timing signal (f): transfer source control circuit start signal ( g): transfer source counter load timing signal (h): transfer source bus request signal (i): transfer source bus grant signal (j): signal of transfer source bus strobe, etc. (k): transfer source bus acknowledge signal (l) : Buffer write signal, etc. (m): Transfer source counter decrement / increment timing signal (n): Transfer destination control circuit start signal (o): Transfer destination counter load timing signal (p): Transfer destination bus request signal (q): Transfer destination bus grant signal (r): Signal of transfer destination bus strobe, etc. (s): Transfer destination bus grant signal Acknowledge signal (t): buffer read signal etc. (u): transfer destination counter decrement / increment timing signal (v): transfer source control circuit start signal As shown in the timing chart of FIG. 7, transfer destination counter load of (o) FIG. 3 shows the timing signal output.
Since the transfer source address register 16 to the DMA information address register 19 shown in (1) become empty, the values of the next transfer source address register 12 to the next DMA information address register 15 can be transferred. Therefore, the address register set timing signal in (e) and the signal such as the DMA information strobe in (c) are turned on, and then the next address register set timing signal in (d) is turned on. As a result, the data transfer by the DMA and the reading of the next DMA information are executed in parallel in time.

[Second Embodiment of DMA Control Circuit] FIG. 8 is a block diagram showing another configuration of the DMA control circuit. By the next DMA information acquisition control circuit 50, one D
The point that the next DMA information is acquired during the data transfer based on the MA information is the same as the DMA control circuit shown in FIG.

However, in the DMA control circuit shown in FIG.
While the dedicated bus 23 is used to acquire the DMA information, the DMA control circuit shown in FIG. 8 uses a data transfer bus to acquire the DMA information and shares the bus between the acquisition of the DMA information and the data transfer. Is different. However, before the data transfer by one DMA information is completed, the next DM
In order to obtain the A information, as shown in FIG. 1 (A2), the next DMA information is obtained by utilizing the idle time of the bus due to the actual interruption of data transfer.

This is because, in the system as shown in FIG.
Paying attention to the fact that the communication speed of the IO bus 103 on the 100 side is lower than the communication speed of the IO bus 103, an interval between data transfer using the IO bus 103 is increased, and the idle time is used for acquiring the next DMA information. It is like that.

For this reason, the completion of the data fetch and the completion of the transfer are notified between the transfer source control circuit 59 and the transfer destination control circuit 60, and when a vacancy occurs in the bus due to the completion of the fetch, the next DMA information acquisition control circuit is provided. 50, the next DM
Notifies that acquisition of A information is possible. As a result, the next DMA information acquisition control circuit 50 outputs a bus request signal and, after obtaining a bus use permission (bus grant), reads the next DMA information. The read DMA information is stored in the next transfer source address register 51 and the next transfer counter 5.
2. The next transfer destination address register 53 and the next DMA information address register 54 are set.

The other components are the same as those of the DMA control circuit shown in FIG. 3, and the description thereof will not be repeated. [Third Embodiment of DMA Control Circuit] FIG.
FIG. 9 is a block diagram illustrating another configuration of the control circuit.

In FIG. 9, the local buffer 76
For example, it corresponds to the local memory 107 in the network adapter 104 shown in FIG. 2, and when transmitting data to the communication line 110, the transfer source DMA control unit 70 transfers the data from the main memory 101 to the local memory 107 (local buffer 76) in FIG. The transfer destination DMA control unit 80 controls the data transfer from the local memory 107 to the internal buffer of the network control unit 109. The data transfer is performed by the network control unit 109 from the CP.
The same applies to the reverse operation performed on the U100 side, such as the basic operation described below.

In the DMA control circuit shown in FIG. 9, two DMAs, DMA data transfer from the main memory 101 to the local buffer 76 and DMA data transfer from the local buffer 76 to the network control unit 109, etc.
It can be performed by one DMA start from U100.

For this reason, the transfer source DMA control unit 70 includes a transfer source local buffer address register 71 for holding the address of the local buffer 76 for writing the transfer source data, and an address of the transfer source main memory 101 (FIG. 2). Source address register 72 for holding the transfer, transfer source transfer counter 73 for counting the transfer amount, and transfer source control circuit 7 for controlling the fetching of data from the transfer source.
With 4.

On the other hand, the transfer destination DMA control section 80 has a transfer destination local buffer address register 81 for holding an address for reading data from the local buffer 76.
And a transfer destination address register 8 for holding the address of a buffer of the transfer destination, for example, of the network control unit 109.
2, a transfer destination transfer counter 83 for counting the transfer amount, and a transfer destination control circuit 84 for controlling the transfer of data to the transfer destination.

In addition, the transfer destination control circuit 84 controls the stop control circuit 85 for controlling the stop of the DMA transfer from the local buffer 76 to the transfer destination, and controls the restart of the DMA transfer from the local buffer 76 to the transfer destination. Restart control circuit 86
With

The present invention is particularly different from the prior art in that the transfer destination control circuit 84 has a stop control circuit 85 and a restart control circuit 86 and a notifying means 75 for operating them.

The transfer source control circuit 74 outputs a transfer source address and a control signal for taking in data based on the values of the transfer source local buffer address register 71, the transfer source address register 72, and the transfer source transfer counter 73. The data is sent to the transfer source, and the data sent from the transfer source is written in the local buffer 76.

The notifying means 75 monitors whether or not the data of the DMA transfer source is ready on the local buffer 76 by, for example, polling a specific control bit, and monitors the information by the stop control circuit 85 and the restart control. The circuit 86 is notified. As a result, the stop control circuit 85 and the restart control circuit 86 instruct the transfer destination control circuit 84 to stop / restart the DMA transfer.

The transfer destination control circuit 84 generates a transfer destination address and a control signal for data transfer based on the values of the transfer destination local buffer address register 81, the transfer destination address register 82, and the transfer destination transfer counter 83. The data is sent to the transfer destination, the transfer destination data is read from the local buffer 76, and sent to the transfer destination.

FIG. 10 shows an example of the data structure of the DMA information used in the present embodiment. DMA used for DMA transfer
The information includes, for example, a transfer source address, a transfer destination address, a transfer amount, and various control information as shown in FIG. The control information includes the presence / absence of a chain of the next DMA information, address information for the chain, and information on whether or not to notify the end of the transfer to the DMA transfer request source by interruption.
In addition, in the present embodiment, the prepared / unprepared control bit 8 in the control information is used as a work control bit for DMA transfer.
8 are provided. The preparation / unprepared control bit 88 has an initial value of “0”, indicating that data is not prepared in the local buffer 76. When the transfer source control circuit 74 writes data in the local buffer 76, it becomes "1", indicating that the data is ready.

In this example, at the time of DMA transfer, DMA information is prepared in the local buffer 76 in advance, and the transfer source DMA control unit 70 holds the start address of the DMA information. Transfer source control circuit 74
Sets the ready / unprepared control bit 88 to “1” with the data being taken into the local buffer 76,
Thus, the notifying means 75 knows that the data has been prepared on the local buffer 76. Instead of using the control bit in the DMA information as the work flag, a bit of a predetermined specific address in the local buffer 76 may be used.

As described above, the notification means 75 intervenes to take over the DMA transfer from the transfer source to the transfer destination.
It is possible to control two DMA transfers by starting the DMA from the CPU 100 once.

[Fourth Embodiment of DMA Control Circuit] FIG. 11 is a block diagram showing still another configuration of the DMA control circuit. The basic operation of each part of the DMA control circuit shown in FIG. 11 is almost the same as that of the DMA control circuit shown in FIG.

The major difference between the DMA control circuit shown in FIG. 11 and the circuit shown in FIG. 9 is the notification means 90, whereas the notification means 75 in FIG. 9 monitors the control bits of the DMA information by polling. The notifying means 90 according to the present embodiment receives the notification of the transfer completion from the transfer source control circuit 74, and sends it to the transfer destination DMA control unit 8 by an interrupt signal.
The difference is that the stop control circuit 85 and the restart control circuit 86 of 0 are notified.

According to the present embodiment, two DMA transfers can be controlled by a single DMA activation from the CPU 100.

[0065]

As described above, according to the present invention,
It is possible to acquire chained DMA information without reducing the data transfer speed, and to shorten the processing time of the entire DMA transfer. Further, since two DMA transfers can be controlled by one DMA activation, efficient communication is possible.

[Brief description of the drawings]

FIG. 1 is a principle block diagram of the present invention.

FIG. 2 is a diagram illustrating an example of an application system of the present invention.

FIG. 3 is a block diagram illustrating a configuration of a DMA control circuit.

FIG. 4 is a block diagram of a transfer source control circuit shown in FIG. 3;

FIG. 5 is a block diagram of a transfer destination control circuit shown in FIG. 3;

FIG. 6 is a block diagram of a next DMA information acquisition control circuit shown in FIG. 3;

FIG. 7 is a timing chart showing the operation of the circuit.

FIG. 8 is a block diagram showing another configuration of the DMA control circuit.

FIG. 9 is a block diagram showing another configuration of the DMA control circuit.

FIG. 10 is a diagram illustrating an example of a data structure of DMA information.

FIG. 11 is a block diagram showing still another configuration of the DMA control circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 DMA information acquisition means 2 DMA information holding means 3 Transfer control means 4 Transfer control means 5 Local buffer 6 Notification means 7 Stop means 8 Restart means

Claims (6)

[Claims] 1. A DMA controller having storage means for holding a plurality of pieces of DMA information and controlling data transfer from a transfer source to a transfer destination based on the held DMA information. DMA control, comprising: DMA information acquiring means for acquiring the next DMA information during data transfer; and control means for continuing data transfer with the previously acquired next DMA information after the transfer by one DMA information is completed. apparatus. 2. The DMA controller according to claim 1, wherein said DMA information acquisition means has a dedicated bus for acquiring DMA information, separately from a bus for transferring data by DMA. . 3. The DMA controller according to claim 1, wherein said DMA information obtaining means uses a bus for data transfer by DMA for obtaining DMA information, and includes a bus for data transfer by one DMA information. A DMA controller for acquiring the next DMA information by using a data transfer bus during a vacant time between a temporary transfer and a partial transfer. 4. A storage means for holding DMA information and a DMA
A DMA controller which has a local buffer for data transfer and controls data transfer from a transfer source to a transfer destination based on held DMA information, wherein data of the DMA transfer source is stored in the local buffer. Notifying means for notifying whether or not the data is ready; stopping means for stopping DMA transfer from the local buffer to the transfer destination when notified that the data is not ready; A DMA control device, comprising: a resuming means for resuming DMA transfer from the local buffer to a transfer destination when notified that data is ready by the means. 5. The DMA control device according to claim 4, wherein said notifying means polls control information provided in said predetermined control information holding means or DMA information indicating that transfer source data is ready. A DMA controller for confirming whether or not transfer source data is prepared in the local buffer by checking the data. 6. The DMA control device according to claim 4, wherein said notifying means is means for notifying that transfer source data is ready by an interrupt signal.