JPS5854430A - Data transfer system between memories - Google Patents

Abstract

PURPOSE:To resolve an inevitable defect of software processing requiring a long time for data transmission/reception by executing data transmission/reception between a memory in a central processing unit and a memory in a local processing unit through hardware processing. CONSTITUTION:An output of a command register 1 is transferred to a control circuit 6 and both the units 1, 6 constitute a continuous access control circuit. An address line 7 from a central processing unit (CPU) is also connected to the control circuit 6. A signal line 8 is connected from the circuit 6 to a counter 3 and set-up timing signals 14, 15, 16 from respective registers are transferred from the circuit 6 to a start address register 1, a counter 2 and the couter 3 respectively. A line 10 is connected from the circuit 6 to an address switching gate circuit 9 and a line 12 is connected from the circuit 6 to a memory of a processing unit, e.g. a read-out/write indication terminal (R/W) of a picture memory 11 in a display device.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an inter-memory data transfer method that allows continuous data transfer between the memory of a Tispray MS and the memory of a central processing unit using hardware processing.

In an information processing system in which a display device is connected to the microcomputer, data is continuously sent and received between the main memory of the microcomputer and the screen memory of the display device, and data is stored at consecutive addresses in the memory. Or, when reading data, each time one data is sent, the index register must be incremented or decremented using several instructions, and the number of data transferred must also be counted1. The fact that multiple instructions tw must be used for each data means that the number of data that must be continuously transferred is large, and the total time taken for such processing becomes long, and the data This would make it impossible to meet the demand for continuous transfer management.

The present invention was devised to solve the drawbacks of the conventional techniques as described above, and its purpose is to perform data transmission and reception between the memory of a central processing unit and the memory of a processing unit using hardware-like processing. The object of the present invention is to provide a data transfer method between memories that solves the long time required for data transmission and reception, which is unavoidable in conventional software processing.

Hereinafter, a dormitory embodiment of the present invention will be described with reference to the accompanying drawings.

In the accompanying drawings, 1 is a command register, 2 is an end address register, and 3 is a start address register/counter. lti data bus 4KIi & 2.
3 is connected to the address bus 5. These paths extend to a central processing unit (not shown) and are connected to the necessary parts of its internal memory supply.

The output of command register 1 is connected to control circuit 6. The command register 1 and control circuit 6 function as a continuous access control circuit. In the sash circuit 6, there is also
An address signal line 7 from the central processing &- (upper address * such that the memory range and command register 1 is decoded) is connected. 111iI8 from control ah path 6 to start address register/counter 3 and set-up timing signals 14, 15, 16 of each register.
There are 118. This line 8 is a string supplying a count amplifier signal or countdown signal tube. Mayu, from control circuit 6 to address switching circuit 9 1ii105E
The memory 12 of the processing device is connected from the circuit to the read/ill input instruction terminal (R/W) of the mth memory 11 of the display device. The line lO switches between the output address bus 5 of the start address register/counter 3 and the address input of the memory 11 (Muro n
) is used to control the connection to the 7 dressing section of the memory 11, and all 2 is a read function or write function tube for the 7 dressing section of the memory 11, and switches whether to operate with this function or to perform normal memory R/W & operation. supply the signal.

The output of the start address register/counter 3 and the output of the end address register 2 are connected to the comparison [11613, and the match output of the l[@ path is connected to the control i path 6. -Ikl of comparison circuit 13! Control circuit 6 is configured to generate an interrupt signal on line 17 in response to signal i.

Next, the operation of the circuit shown in the accompanying drawings will be explained.

Processing from the central processing unit! ! Specify data and count up or down on the data bus 4 from the central processing unit 1 at the start of access (read or write) to the memory of the i-device, for example the screen memory 11 of the display device. At the same time as the data is sent out, the address specified by the command register 1181 is sent out on the address bus 5. Each data on the data bus 4 is placed in the command register 1 specified by this address.

After that, when the start address is sent onto the address bus 5, the fill-in data on the start address is sent onto the data bus 4 at the time of filJ. At this point, the operation of the memory is normal, and at the same time, fIi on the address bus is set in the start end address register, and then the end address is similarly sent and set in the end address register 2. Subsequent accesses to the memory attotos range (R@ad, Wy mouth) either change the contents of command register 6 by 1 (interruption instruction) or change the contents of start address register/counter 3 and end address register 2. It will remain under the control of this function until it matches.

The control circuit 6, which receives the address of the central processing unit FIII from the number 7 (to know the range of memory addresses, the upper few are sufficient) and the command register 1, switches the address via the line 10. A switching gate signal tube is supplied to the gate circuit 9 so that the address of the start address register/counter 3 is supplied to the address input (mu DD) of the memory 11, and after the fi12 meeting, the entry number and number of the pilgrimage are written. An instruction signal 14# is supplied to set the memory 11 to read mode or write mode. Also, a count up or count down signal is supplied to the start address register/counter 3 to cause it to count up or count down.

In this way, the address of counter 3 is changed every 1-byte read/write operation, and the address is changed to memory 11.
The memory 11 is accessed one after another in one of the modes which is input to the address input (ADD) of the address input (ADD) and is fixed by the signal on l1112. If the access mode is in the start mode, the data read from successive addresses is sent to the memory of the central processing unit via the data bus 4Yr, and if the access mode is in the write mode, the data is sent from the memory of the central processing unit to the data bus 41M. The incoming data is written to successive addresses in the memory 11.

The address of the write counter 3 is generated continuously until the match signal which reaches the end address of the end address register 2 is output from the comparison path 13. <. When a match signal is generated from the comparison circuit 13, it is sent to the central processing unit via the interrupt signal 1 line 171 of the control circuit 6 that responds to this signal, and is then sent to the central processing unit for the next processing V.
Enter C.

As mentioned above, continuous reading from or successive glances at the screen 11 by the book FIIK is performed as before.
Since it is not necessary to process a series of data using HA instructions for data processing, the time required for a series of data processing can be significantly reduced. Therefore, the reduced time is used for more detailed processing, so that the processing density can be increased. Additionally, the program capacity is reduced.

Note that the present invention can be practiced regardless of whether or not the above-mentioned data transfer is performed while occupying the data bus.

In summary, according to the present invention, the following effects can be obtained.

■ Processing time can be significantly reduced.

■ Can be used to improve processing density.

■ 7° Roku > 4W amount is likely to decrease.

[Brief explanation of the drawing]

The choreography drawing is a circuit diagram of an embodiment of the present invention. In the figure, 1 is a command register, 2 is an end address register, 3 is an expanded start address register/counter, and 4 is a command register.
is a data bus, 5#i address I<s, 6 is a control circuit,
13 is a comparison circuit and ll&i memory. Il! jp person Fujitsu Limited

Claims (1)

[Claims] In an inter-memory data transfer method in which data is continuously transferred between a memory of a central processing unit and a memory of a processing unit via a data bus, the processing unit includes a start address register/counter, an end address register,
A continuous access control circuit and a comparison circuit are provided, and the continuous access control circuit is set to a continuous access mode under the control of the central processing & wrinkles, and the start address is set to 1 in the start address register/counter, and the start address is set to 1 in the start address register/counter. Set all the end addresses in the end address register and cause the count value of the start address register/counter to change, and then set the start address register/counter.
Until equality between the count of the counter and the address value of the end address register is detected by the comparator circuit, no access is made to the memory of the processing unit and the memory of the central processing unit i. The data is transferred continuously via the data bus between t%
A data transfer method between memory.