JPS607529A - Buffer memory device - Google Patents

Abstract

PURPOSE:To shorten a data reading time by switching the mode between the data input and the data output of each memory circuit when the reading is through with all addresses written into one of two memory circuits. CONSTITUTION:When the reading is through with all addresses written previously into one of the 1st and 2nd memory circuits, the mode is switched between the data input and the data output of each memory circuit before the writing is through for the other memory circuit. For instance, the reading is through for the data written into a memory circuit 2 and the new data is written into a memory circuit 1. Under such conditions, a flag 13 is inverted and reset by a control circuit 31 and then the circuits 1 and 2 are set in data output and data input modes respectively. Then the data of the register 5 is stored in a register 32 in said mode switching state. Then counters 7 and 8 are reset and ''0'' is stored to registers 5, 6 and 33 respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a buffer memory device that connects, for example, data processing devices operating at different speeds, and particularly to a device that increases data read speed.

Conventionally, there has been a device of this type as shown in FIG.

In the figure, (1) and (2) are memory circuits, (3) is a register that stores data to be written to either memory circuit (1) or (2), and (4) is a memory circuit (1) or (2).
); (5) a register for storing data read from one of the registers;

(6) is a register that stores data for specifying addresses of memory circuits (1) and (2); (7) and (8) are reset functions and carry signals CI.

A counter having a function of outputting C2, (9) a selection circuit, and (10) the memory circuit (1).

(2), a control circuit that controls counters (7), (8), etc., and (11), data is written to all addresses of either memory circuit (1) or (2), and memory circuit (1) ,
A flag that is set when data output is possible from either (2), (12) is the memory circuit (1), (2)
There is room to write data to one of the addresses,
A flag (13) is set when data input is possible to either memory circuit (1) or (2).
) is set to data output mode,
Conversely, the memory circuit (1) is set to data output mode,
A flag that is reset when the memory circuit (2) is set to data input mode, (14) is a data bus that inputs input data to the register (3), (15) to (18)
) is a data bus, (19) is an output bus for outputting output data to an external device, and (20) and (21) are registers (5) for the outputs of counters (7) and (8), respectively.

Buses (22) and (23) input to (6) are carry signals CI from counters (7) and (8), respectively.

A signal line that inputs C2 to the control circuit (10), (24) a signal line that inputs a data output request signal from an external device, and (25) a signal line that inputs a data input request signal W from an external device. , (26).

(27) is a signal line that inputs the contents of flags (11) and (12) to the control circuit (10) and external device, and (28)
) is a signal line for inputting the contents of the flag (13) to the control circuit (10). The memory circuits (1) and (2) are alternately switched to a data output mode and a data input mode by a control circuit (10), and are not set to the same mode twice. Further, the counter (7), bus (20), register (5), counter (8), bus (21), and register (6) are each connected to an address designation signal generation circuit (29),
(30), and now the memory circuit, circuits (1), (2)
For example, the addresses from address O to the final address are specified. Note that after specifying from address 0 to the final address, it may be specified conversely from address N to address O.

Next, the operation of the conventional buffer memory device having the above configuration will be explained. As an initial setting, the memory circuit (1)
, (2) are stored with 0 in registers (5) and (6), flag (11) is reset, and flags (12) and (13) are set. Since the flag (12) is set, the memory circuit (1).

In (2), only data input is possible, and the flag (
13) is sent, the memory circuit (1) is set to data input mode, and when the input request signal W is input from the signal line (25), the input data is stored in the register (3) and the memory circuit ( 1) is written to address O. In parallel with this operation, the counter (7) counts
After writing to the above address is completed, the output of the counter (7) is stored in the register (5) and the next address is designated. This operation is sequentially repeated each time the input request signal W is input. Memory circuit (1
) is written to the last address of the counter (
7) is counted and amplified, a carry signal C1 is output from the counter (7), and this signal C1 is applied to the signal line (2).
2) to the control circuit (10). When this signal C1 is input, a flag (1
1) is set, and the flag (13) is also set. When the flag (13) is reset, the memory circuit (2
) is set to the data input mode, and therefore input data is sequentially written to each address of the memory circuit (2) by inputting the input request signal W through the same operation as described above. Next, when an output request signal is input from the signal line (24), the data at the predetermined address specified by the output of the register (5) of the memory circuit (1) is transferred to the selection circuit (9).
), stored in register (4), and output. At this time, the counter (7) is counted up, this data is stored in the register (5), and the next address is specified. This operation is repeated every time an output request signal is input. When the carry signal C1 is output from the counter (7) after reading data from all addresses of the memory circuit (1), the data is written to all addresses of the memory circuit (2) and is also read from the counter (8). A flag (13) is set when the carry signal C2 is output.

As a result, the memory circuit (1) is set to the data input mode and the memory circuit (2) is switched to the data output mode. That is, the switching between the data output mode and the data input mode is performed after all addresses in one memory circuit have been read and all addresses in the other memory circuit have been written. In this way, input data can be written to one memory circuit and pre-written data can be output from the other memory circuit in parallel, making it possible to use a data buffer memory device to connect devices with different operating speeds. Can be configured.

However, in conventional buffer memory devices, each memory circuit (1), (2) is set to read mode only after data has been written to all addresses. The drawback is that data cannot be read out until after it has been written to an address, and as the capacity of the memory circuit increases, the time from when data is written until when it is read becomes longer.

The present invention has been made to eliminate the above-mentioned drawbacks.
1st. When reading of all addresses written in advance in one of the second memory circuits is completed, the data input and data output modes of each memory circuit are switched without waiting for the writing of the other memory circuit to be completed. This shortens the data read time. That is, when input request signal W is input, input data is written to either the first or second memory circuit, and when output request signal W is input, data that has not yet been read to the other memory circuit is written. If there is, it will be read and output, but the first condition is as follows:
Preferably, when the first condition and the second condition are met, a memory circuit set in data output mode is switched to data input mode, and a memory circuit set in data input mode is switched to data output mode. be.

The first condition among the above conditions is that reading of all data previously written in one memory circuit set to data output mode has been completed, and the second condition is that one memory circuit is set to data input mode. The presence of one or more newly written data in the other memory circuit. Therefore, the memory circuit set to the data input mode is set to the data output mode during data writing, so that the data reading time can be shortened. The present invention will be described in detail below using Examples.

FIG. 2 is a block diagram showing an embodiment of the buffer memory device according to the present invention, and in the same figure, (1) to (9)
, (11) to (30) are the same as the conventional device explained in FIG.

(31) is a control circuit, (32) and (33) are resettable registers, and (34) and (35) are each register (5
) and register (32), register (6) and register (3
3) Comparison circuit that compares the data, (36), (37)
are signal lines (38) to (41) that input coincidence signals Ml and M2, which are output when the two data input to the comparison circuits (34) and (35) are equal, to the control device (31), respectively;
) is the data hash.

The operation of the buffer memory device having such a configuration will be described below.

The initial setting and the operation when the data input/output mode of the memory circuits (1) and (2) are switched will be explained.

Now, after the flag (13) is sent, the memory circuit (
1) is set to data input mode, and the memory circuit (2)
is set to the data output mode, and the first condition is that reading of all data written in the memory circuit (2) set to the data output mode is completed, and the memory set to the data input mode. Assume that the second condition that one or more newly written data exists in circuit (1) is satisfied. At this time, the control circuit (31) is activated, the flag (13) is inverted and reset, the memory circuit (1) is set to data output mode, and the memory circuit (2) is set to data output mode.
) is set to data entry mode. When this mode is switched, the register (32) is set to register (5).
The address designation data of the memory circuit (1) specified at the time of the above mode switching is stored, then the counters (7) and (8) are reset, and the register (
5), (6) and register (33) are stored with 0.

The default setting is register.

O is also stored in (30). Next flag (11) (1
2) is sent, data can be input/output from an external device, and data input/output is executed in accordance with input/output signals W and L as described above. Register (6), (33)
Since both data are 0 at first, the comparison circuit (35)
A match signal M2 is output from the register (2), but when data is written to address 0 in the memory circuit (2), the register (
Since the data in 6) is counted up, the match signal M
2 will no longer be output. This can also be interpreted as a mismatch signal being output. This means that the second condition above is satisfied. Furthermore, each time data is output from the memory circuit (1), the data stored in the register (5) is counted and amplified, addresses are sequentially specified, and the data is written. 32) become equal, a match signal M1 is output from the comparator circuit (32). That is, from the memory circuit (1) to the register (32)
When the data at the specified address stored in the memory circuit (1) is read out, this means that all the data written in the memory circuit (1) in the previous data input mode has been read out. This means that the condition is satisfied. Since the second condition has already been met, the modes of the memory circuits (1) and (2) are switched again.

Therefore, when all previously written data is read from one memory circuit, if even a small amount of data has been written to the other memory circuit, the mode is switched, so that reading can be speeded up. Note that the reason why the second condition is added in addition to the first condition is to avoid wasteful reading operations performed even though no writing has been performed.

Note that when data is written to all addresses of a memory circuit set to data input mode, the counter (7) (G) corresponding to this memory circuit becomes the counter (8).
Carry signals CI, , C2 are output from the control circuit (
31), the flag (12) is reset, and data input from an external device is disabled. Further, if only the first condition is satisfied, it means that all input data has been output, so the flag (11) is reset and data cannot be output to an external device. Flags (11) and (12) are set when the above two conditions are met.

Note that in the above embodiment, each memory circuit (1).

(2) was explained assuming that the first written data is read first regarding data input, but register (3)
2), (33) always put an O on the counter (7)
, (8) is provided with a count-a-knob and current-down mechanism, and when writing data, it counts up and specifies the address in the direction of the final address, and when reading, it counts down and specifies the address. By specifying the data in the address direction of address 0, the data written last can be read out first, producing the same effect as in the above embodiment.

As described above, according to the present invention, the first. In a buffer memory device having a control device that alternately switches a second memory circuit between a data input mode and a data output mode, all data written in the data input mode of the memory circuit set to the data output mode is read out. Since the data input/output mode of the two memory circuits is exchanged when the data input/output mode of the two memory circuits is changed, it is possible to quickly retrieve the written data.

[Brief explanation of drawings]

Figure 1 is a block diagram of a conventional buffer memory device, Figure 2 is a block diagram of a conventional buffer memory device.
FIG. 1 is a block diagram of a buffer memory device according to an embodiment of the present invention. (1), (2)...Memory circuit, (5). (6), (32), (33) ... register, (7)
, (8) ... counter, (10). (31)...control circuit, (11), (12). (13)...Flag, <34), (35)...Comparison circuit. In addition, in the figures, the same reference numerals indicate the same or corresponding parts. Agent Masuo Oiwa (and 2 others)

Claims (1)

[Scope of Claims] (11. Addressing means for specifying addresses of first and second memory circuits in a predetermined order; In the first memory device, the number of data written in the first and second memory circuits is stored in the first and second data output modes at the time of switching between the data input and output modes. comprising a second storage means, and first and second determination means for detecting that the number of data read from the memory circuit matches the number of data stored in advance in the storage means and outputting a coincidence signal; The control means controls the first and second determination means based on the coincidence signal output from either the first or second determination means.
A buffer memory device characterized in that the data input/output mode of the second memory circuit is switched. (2) The address specifying means specifies the order of addresses when writing data and the order of specifying addresses when reading data, and the first. (7-four memory device) (recited in claim 1), characterized in that data written earlier in the second memory circuit is read out faster than data written later. (3) The addressing means reverses the order of specifying addresses when writing data and the order of specifying addresses when reading data, so that the data written first and the second memory circuit is the data written later. The memory device according to claim 1, characterized in that data is read out more slowly. (4) Immediately after the control means changes the data input/output mode of the storage means storing the number of written data. reset to
1st. One of the second determining means compares the number of data in the reset storage means and the number of data written in the memory circuit, and outputs a mismatch signal when the two data do not match, and the control means is controlled from this determining means. a mismatch signal, and
The data input/output mode of the first and second memory circuits is switched based on a coincidence signal from the other determining means that detects coincidence between the number of data stored in advance and the number of read data. The buffer memory device according to scope 1.