JP2723843B2 - Dual port memory control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dual-port memory control circuit, and more particularly to a control circuit for preventing various failures when a write address and a read address match when a dual-port memory is used as a first-in first-out memory. About.

[0002]

2. Description of the Related Art In a dual port memory for obtaining read data from a specified read address while writing the specified write data to a specified write address, generally, when the write address and the read address match, the write data is used. Since the read data is destroyed or the read time is extremely slow, it is prohibited that the write address matches the read address.

For this reason, conventionally, when a dual-port memory is used as a first-in first-out memory, a control circuit for avoiding a coincidence between a write address and a read address has been provided. As shown in FIG. 2, the conventional dual-port memory control circuit includes a dual-port memory 10, a comparison circuit 90 that compares a write address with a read address, and an address change control circuit 80 that changes a read address. ing. In the operation of this conventional example, the write address and the read address input by the comparison circuit 90 are compared, and when the address difference falls within a certain value, the read address is compared with the write address by the address control circuit 80. The address is changed so as to be equal to or larger than a certain address difference and supplied to the dual port memory 10 to avoid writing and reading to the same address.

[0004]

In the conventional dual port memory control circuit described above, when the write address and the read address approach each other, the read address is changed to avoid the coincidence between the write address and the read address. As a result, the data written to the address to be changed cannot be used, and must be rewritten again, and the processing speed and the processing speed of a data processing system and device using this dual port memory control circuit However, there is a problem that characteristics are deteriorated.

[0005]

A dual-port memory control circuit according to the present invention has a first dual-port memory control circuit which has the same function and configuration and inputs a designated write address and designated write data at the same timing. A port memory, a second dual port memory, and an address delay circuit for delaying an input timing of a designated read address to the first dual port memory by a predetermined delay timing with respect to an input timing to the second dual port memory. A data delay circuit for delaying an output timing of data read from the second dual-port memory based on the designated read address by a predetermined delay timing equivalent to the address delay circuit; The designation specified in the port memory A comparison circuit for comparing whether the read write address matches the delayed read address, and selecting data read from the first dual-port memory when a comparison result indicating an address match is not output from the comparison circuit. A selection circuit for selecting data read from the second dual-port memory delayed through the data delay circuit when a comparison result indicating an address match is output from the comparison circuit.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention. In FIG. 1, the dual port memory control circuits have the same function and configuration as each other, and write (input).
A first dual-port memory for inputting data, a write address, and a read address and outputting read (output) data;
An address delay circuit 30 comprising a shift register and delaying a read address to the first dual-port memory 10 by a predetermined cycle; a comparing circuit 50 for comparing a write address and a read address of the first dual-port memory 10; A data delay circuit 60 comprising a shift register and delaying output data of the second dual-port memory 20 by the same predetermined cycle as that of the address delay circuit 30; Output data or data delay circuit 6
0, a selection circuit 70 for selecting any of the output data of the second dual port memory 20 and input terminals 101 to 1 for inputting and outputting various data and information to and from the outside.
03 and an output terminal 111. An input terminal 101 for inputting write data and an input terminal 102 for inputting a write address are directly connected to the first and second dual-port memories 10 and 20, respectively. An input terminal 103 for inputting a read address is directly connected to the second dual-port memory 20, but is connected to the first dual-port memory 10 through the address delay circuit 30. The output of the selection circuit 70 is connected to the output terminal 111. The write address and the read address supplied to the present circuit are repeated while continuously changing at a constant cycle number, and the delay cycle values of the address delay circuit 30 and the data delay circuit 60 are arbitrary smaller than these cycle numbers. Value.

Next, the operation will be described. The same data is written to the same address of the first dual port memory 10 and the second dual port memory 20. The read address for the first dual port memory 10 is delayed by a predetermined cycle, but while the delayed read address does not match the write address, the comparing circuit 50 outputs a comparison result indicating a match. Instead, the selection circuit 70 outputs the output data of the first dual port memory 10 to the output terminal 111. When the delayed read address in the first dual-port memory 10 matches the write address, the comparison circuit 50 outputs a comparison result indicating the match, and the selection circuit 70 outputs the data delay circuit 6
The output data of the second dual port memory 20 delayed by 0 is output to the output terminal 111. That is, the data to be read at the delayed read address on the first dual-port memory 10 which is the main memory is
The data has already been read at the corresponding read address without delay on the side of the second dual-port memory 20 which is the auxiliary memory, and the data delay circuit 60 has
And the same delay is given, and the timing is replaced.

Table 1 shows a timing chart for explaining the operation when the write and read operations are delayed by three cycles in the address delay circuit 30 and the data delay circuit 60, respectively.

[0009]

[Table 1]

In Table 1, a to z are addresses, D
(A) to D (z) indicate the data of the address shown in parentheses. The read address a of the input terminal 103 in the first cycle is delayed by three cycles in the address delay circuit 30 and is input to the first dual port memory 10 in the fourth cycle. Matches. In this case, in the second dual-port memory 20, the data D (a) has already been read by the read address a in the first cycle,
The data D (a) is delayed by three cycles in the data delay circuit 60 and is input to the selection circuit 70 and selected in the fourth cycle.

[0011]

As described above, according to the present invention, two dual port memories, a first dual port memory serving as a main memory and a second dual port memory serving as an auxiliary memory, are provided and designated. Writing of the specified write data to the address is performed at the same timing, and the first dual-port memory outputs the read data with the specified read address delayed by a predetermined delay timing, and outputs the read data to the second dual-port memory. Outputs the data read at the specified read address with a delay of a predetermined delay timing, and normally selects the data on the first dual port memory side as output data. When the read address matches the write address of the memory, the write address When the read addresses do not match, the data of the second dual-port memory that has been read earlier is selected as output data, so that the specified write address for the dual-port memory and the delayed specified Even if the read address matches, normal data can be written to the dual-port memory and normal data can be read from the dual-port memory. This eliminates the need to perform a write operation again as an apparatus to which the present invention is applied, and Speed and characteristic deterioration can be prevented.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing a conventional dual port memory control circuit.

[Description of Signs] 10, 20 First and second dual-port memories 30 Address delay circuit 40 Read operation control circuit 50 Comparison circuit 60 Data delay circuit 70 Selection circuit 101 Input terminal for write data 102 Input terminal for write address 103 Read Address input terminal 111 Read data output terminal

Claims (1)

(57) [Claims] 1. A first dual-port memory and a second dual-port memory having the same function and configuration and inputting a designated write address and designated write data at the same timing. An address delay circuit for delaying the input timing of the read address to the first dual-port memory by a predetermined delay timing from the input timing to the second dual-port memory; and the second delay circuit based on the specified read address. A data delay circuit for delaying the output timing of the data read from the dual port memory by a predetermined delay timing equivalent to the address delay circuit, the specified write address input to the first dual port memory, and Delayed read address and A comparison circuit for comparing whether or not
When the comparison result indicating the address match is not output from the comparison circuit, the data read from the first dual-port memory is selected, and when the comparison result indicating the address match is output from the comparison circuit, the data delay circuit is selected. A selection circuit for selecting data read from the second dual-port memory delayed through the second dual-port memory.