JPH04321993A - Storage control device - Google Patents

Abstract

PURPOSE:To write individual data in the address of a second storage circuit by successively storing in a first storage circuit the write address and the write data of the second circuit and then reading them out of the first circuit. CONSTITUTION:When a write request signal 113 to the second storage circuit 102 is inputted in a input control circuit 114, the write address 103 of the circuit 102 is selected by a selector 106, a write signal 119 is generated by a write circuit 118, and the address 103 is written in the O-order of the first storage circuit 101. Then, the write data 105 is selected by the selector 106, and the data 105 is written in the 1st word of the circuit 101. Then, by a control signal 122 from an output control circuit 121, the write address 108a is read from the O-order word of the circuit 101 and written in the address register 109 of the circuit 102. Successively, the write data 108b is read from the 1st word and written in the data register 111 of the circuit 102.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage control device that uses a memory to implement a FIFO circuit used in an input buffer section of a data processing device.

0002

2. Description of the Related Art Conventionally, FIFO circuits have been implemented using two methods: a method using a shift register and a method using a memory. In the method using a shift register, data is physically moved from an input end to an output end using a shift clock. However, with this method, data must necessarily propagate from the input end to the output end, so a long F
There was a problem in that it was not suitable for realizing an IFO circuit.

On the other hand, in the method using memory, instead of moving data, a pointer is used to manage the address to which data should be written next, and a pointer is used to manage the address to which data should be read next. FI by providing
The FO circuit was realized logically.

Since the storage control device of the present invention is a type of FIFO circuit using the latter type of memory, a conventional example of a method using the memory will be explained. As a conventional example, “FIFO
``Circuit'' (Japanese Unexamined Patent Publication No. 60-262242).

FIG. 4 shows a block diagram of a conventional FIFO circuit. In FIG. 4, 201 is a memory circuit consisting of n words;
02 is a write request signal, 203 is a write request signal 2
02, the first counter increases by 1 modulo n, 204 is the value output from the first counter 203, 20
5 is a write circuit for the memory circuit 201; 206 is a write signal output from the write circuit 205; 207 is a read request signal; 208 is a second counter that increases by 1 in the n-method according to the read request signal 207; 209;
is the value output from the second counter, 210 is the memory circuit 20
1 is a readout circuit, 211 is a readout circuit 210
212 is a coincidence detection circuit that compares the value 204 output from the first counter 203 and the value 209 output from the second counter 208 to detect whether they match. 213 and 214 are coincidence circuits. 212 is a status signal output, 215 is write data, and 216 is read data. Conventional FIFO configured as above
Explain the operation of the circuit.

In FIG. 4, each part is assumed to be in its initial state. Write request signal 202 from data processing device 1 (not shown)
occurs, the value 20 output by the first counter 203
The write circuit 205 generates a write signal 206 for the memory circuit 201 in response to the 0th signal of the memory circuit 201.
Write data 215 is written to the word. After the writing of the memory circuit 201 is completed, the value 204 output from the first counter 203 increases from 0 to 1. Next, when a read request signal 207 is generated from the data processing device 2 (not shown), the read circuit 210 generates a read signal 211 for the storage circuit 201 according to the value 209 output from the second counter 208, and Read data 215 is read from the 0th word of circuit 201. Memory circuit 201
After reading is completed, the value 209 output from the second counter 208 increases from 0 to 1.

[0007]

However, in the FIFO circuit described above, the FIFO address for generating a write request signal in the FIFO circuit is fixed to one address. In order to distinguish write data B corresponding to read request signal B from data A and write data B corresponding to read request signal B, there is a problem in that two sets of FIFO circuits must be prepared and separate FIFO addresses must be assigned to each set.

SUMMARY OF THE INVENTION In view of the above, an object of the present invention is to provide a storage control device that functions as a single FIFO circuit even when writing individual data to a plurality of addresses. ■
Another object of the present invention is to provide a storage control device that can prohibit reading from a first storage circuit when the second storage circuit is in a busy state by providing a read prohibition signal.

[0009]Furthermore, it is an object of the present invention to provide a storage control device that stores data size information at the same time as the write address of a second storage circuit, thereby forming a variable data length FIFO circuit.

0010

[Means for Solving the Problems] In order to solve the above-mentioned problems, the present invention provides (1) a first memory circuit, a second memory circuit, and a first memory circuit that controls the write address of the first memory circuit.
a write circuit that generates a write address for the first storage circuit according to the value of the first address counter; a second address counter that controls a read address of the first storage circuit; Second
a read circuit for generating a read address for the first memory circuit according to the value of an address counter of the second memory circuit; and a read circuit for sequentially and alternately storing the write address and write data of the second memory circuit in the first memory circuit. a selector, an input control circuit that controls the selector, the first address counter, and the write circuit, an address register of a second storage circuit, and a data register of the second storage circuit;
an output control circuit for sequentially and alternately storing write addresses and write data of a second memory circuit read out from the first memory circuit in order and alternately into an address register and a data register of the second memory circuit; This is a storage control device characterized by comprising:

[0011] ■ The write address and the write data of the second memory circuit read out alternately from the first memory circuit of the storage control device described in (■) above are transferred to the address register of the second memory circuit and the data. This storage control device is characterized in that an output control circuit for sequentially and alternately storing data in a data register is provided with a read prohibition circuit.

■ The selector for sequentially and alternately storing the write address and write data of the second memory circuit of the storage control device in the above (■) in the first memory circuit.
This storage control device is characterized in that data size information of write data is stored in a first storage circuit together with a write address of the storage circuit.

[0013]

[Operation] With the above-described structure, the present invention stores the write address of the second memory circuit and the write data of the second memory circuit in order and alternately in the first memory circuit; By sequentially and alternately reading the write address of the memory circuit and the write data of the second memory circuit from the first memory circuit and storing them in the address register and data register of the second memory circuit, Individual data can be written to any address in the memory circuit.

■ The write address of the second memory circuit and the write data of the second memory circuit are sequentially and alternately stored in the first memory circuit, and then, when the read inhibit signal is not output, the write address of the second memory circuit is stored alternately in the first memory circuit. The write address of the memory circuit and the write data of the second memory circuit are sequentially and alternately read from the first memory circuit and stored in the address register and data register of the second memory circuit. When the second storage circuit is not busy, individual data can be written to any address in the second storage circuit.

■ The write address and write data size information of the second memory circuit and the write data of the second memory circuit are sequentially and alternately stored in the first memory circuit, and then the second memory circuit By alternately reading out the write address and write data size information of and the write data of the second memory circuit from the first memory circuit and storing them in the address register and data register of the second memory circuit. , any of the second storage circuits

Individual data of any data length can be written to the address.

[Embodiment] FIGS. 1 to 3 are block diagrams showing an embodiment of the storage control device of the present invention, and FIG.
FIG. 2 shows an embodiment of the storage control device according to claim 1, and FIG. 3 shows an embodiment of the storage control device according to claim 2, and FIG. 3 shows an embodiment of the storage control device according to claim 3. An example of a storage control device is shown. In FIGS. 1 to 3, 10
1 is a first memory circuit, 102 is a second memory circuit, 103
105 is the write address of the second memory circuit, 106 is the write address 103 and write data 105 of the second memory circuit, and 106 is the write address 103 and write data 105 of the second memory circuit.
107 is the value output from the selector 106, and 108 is the first value.
109 is the address register of the second storage circuit, and 110 is the address register 10.
9 is the output value, 111 is the data register of the second storage circuit, 112 is the value output from the data register 111, 1
13 is a write request signal to the second memory circuit, and 114 is a write request signal to the first memory circuit 101 in response to the write request signal 113.
115 is a control signal output from the input control circuit 114, 116 is a control signal 11
117 is a write address value outputted from the first address counter 116 to the first memory circuit 101, and 118 is a first address counter. A write circuit generates a write address for the first memory circuit 101 according to the value of 116, 119 is a write signal outputted from the write circuit 118 to the first memory circuit 101, and 121 is a write circuit that generates a write address for the first memory circuit 101 in accordance with the value of 122 is an output control circuit for alternately storing the read write address of the second memory circuit and the write data in the address register and the data register of the second memory circuit; control signal to output,
123 is a second address counter that controls the read address of the first storage circuit according to the control signal 122;
4 is a read address value for the second memory circuit 101 output by the second address counter 123; 125 is a read circuit that generates a read address for the first memory circuit 101 according to the value of the second address counter 124; 126 is a control signal output from the readout circuit 125 for the first storage circuit 101, 127 is a control circuit for the second storage circuit, and 128 is a control signal output from the control circuit 127. 101 is 201 in FIG. 2, 107 is 215, 108 is 216, 115 is 202, 11
6 to 203, 117 to 204, 118 to 205,
119 goes to 206, 122 goes to 207, 123 goes to 208
, 124 goes to 209, 125 goes to 210, 126 goes to 2
Corresponds to 11.

In FIG. 1, assuming that each part is in its initial state,
When writing data from the data processing device to the second storage circuit, when the write request signal 113 to the second storage circuit is generated, the control signal 11 output from the input control circuit 114 is
5 is turned on, the selector 106 selects the write address 103 of the second memory circuit, and the selector output value 10
7 and the first address counter 116.
The write circuit 118 outputs the write signal 11 according to the write address value 117 for the first storage circuit outputted by
9 and stores the second word in the 0th word of the first memory circuit 101.
The write address 103 of the memory circuit is written. After the first write to the first memory circuit 101 is completed, the control signal 115 output from the input control circuit 114 is turned off, the selector 106 selects the write data 105 of the second memory circuit, and the selector outputs At the same time, the first address counter 116 outputs the first value 107.
The write address value 117 for the memory circuit increases from 0 to 1, and the write circuit 118 generates a write signal 119 according to the write address value 117, and writes the second word to the first word of the first memory circuit 101. The write data 105 of the memory circuit is written. After the second write to the first memory circuit 101 is completed, the write address value 117 for the first memory circuit output from the first address counter 116 increases from 1 to 2. Next, the control signal 122 output from the output control circuit 121 causes the read circuit 125 to respond to the read address value 124 for the first storage circuit output from the second address counter 123.
generates the read signal 126 and the first storage circuit 101
The write address 108a of the second memory circuit read from the 0th word is written into the address register 109 of the second memory circuit. First memory circuit 101 for the first time
After completion of reading, the second address counter 123 outputs the read address value 12 for the first storage circuit.
4 increases from 0 to 1, and the readout circuit 125 generates a readout signal 126 according to the readout address value 124, and the second memory circuit reads out the first word of the first memory circuit 101. The write data 108b is written to the data register 111 of the second storage circuit. After the second reading of the first memory circuit 101 is completed, the read address value 124 for the first memory circuit output from the second address counter 123 increases from 1 to 2. After the writing to the address register 109 of the second storage circuit and the data register 111 of the second storage circuit is completed, the writing of the second storage circuit is performed by the control signal 128 output from the control circuit 127 of the second storage circuit. Write data 105 of the second memory circuit can be written to address 103.

In FIG. 2, 120 is the output control circuit 12.
This is a read prohibition signal that prohibits the operation of 1. Assuming that each part is in the initial state, when writing data from the data processing device to the second storage circuit, when the write request signal 113 to the second storage circuit is generated, the control signal output from the input control circuit 114 is 115 is turned on, the selector 106 selects the write address 103 of the second memory circuit, and outputs it to the output value 107 of the selector, as well as the write address value 117 for the first memory circuit output by the first address counter 116. In response to this, the write circuit 118 generates a write signal 119 and sets the write address 103 of the second memory circuit to the 0th word of the first memory circuit 101.
is written. After the first write to the first memory circuit 101 is completed, the control signal 115 output from the input control circuit 114 is turned off, the selector 106 selects the write data 105 of the second memory circuit, and the selector outputs value 1
07 and the first address counter 11.
The write address value 117 outputted by No. 6 increases from 0 to 1, and the write address value 117 outputs from
17, the write circuit 118 outputs the write signal 119.
The write data 105 of the second memory circuit is written into the first word of the first memory circuit 101. After the second write to the first memory circuit 101 is completed, the write address value 117 for the first memory circuit output from the first address counter 116 increases from 1 to 2. Here, while the read inhibit signal 120 that inhibits the operation of the output control circuit 121 is on, it is in a wait state. When the read inhibit signal 120 is turned off, the output control circuit 12
1, the readout circuit 125 generates a readout signal 126 in accordance with the readout address value 124 for the first storage circuit outputted from the second address counter 123, and The write address 108a of the second memory circuit read from the 0 word is stored in the address register 1 of the second memory circuit.
Write to 09. After the first reading of the first memory circuit 101 is completed, the read address value 124 for the first memory circuit output from the second address counter 123 increases from 0 to 1, and according to the read address value 124 Readout circuit 125 generates readout signal 126;
The second word read from the first word of the first memory circuit 101
The write data 108b of the second memory circuit is written to the data register 111 of the second memory circuit. 1st of the 2nd time
After the reading of the memory circuit 101 is completed, the read address value 124 for the first memory circuit output from the second address counter 123 increases from 1 to 2. Address register 109 of the second memory circuit and data of the second memory circuit
After the writing to the data register 111 is completed, the control signal 128 output from the control circuit 127 of the second storage circuit causes
The write data 105 of the second memory circuit can be written to the write address 103 of the second memory circuit.

In FIG. 3, 104 is the write data size of the second memory circuit. Assuming that each part is in the initial state, when writing data from the data processing device to the second storage circuit, when the write request signal 113 to the second storage circuit is generated, the control signal output from the input control circuit 114 is 1
15 is turned on, the selector 106 selects the write address 103 of the second memory circuit and the write data size 104 of the second memory circuit, and selects the output value 107 of the selector.
At the same time, the write address value 1 for the first storage circuit outputted by the first address counter 116 is
17, the write circuit 118 outputs the write signal 119.
The write address 103 of the second memory circuit and the write data size 104 of the second memory circuit are written to the 0th word of the first memory circuit 101. After the first write to the first memory circuit 101 is completed, the control signal 115 output from the input control circuit 114 is turned off, and the selector 106 selects the write data 105 from the second memory circuit.
b is selected and output to the output value 107 of the selector, and the write address value 117 for the first storage circuit outputted by the first address counter 116 increases from 0 to 1, and according to the write address value 117. The write circuit 118 generates a write signal 119, and the write data 105b of the second memory circuit is written into the first word of the first memory circuit 101. At this time, if the write data size 104 of the second memory circuit is longer than the word length of the first memory circuit, for example, the word length of the first memory circuit is
When the word length of the second memory circuit is 4 bytes and the word length of the second memory circuit is 16 bytes, the 16 bytes of write data in the second memory circuit are written in the first to fourth words of the first memory circuit. The input control circuit 114 operates to store the data in a word. Therefore, after the second write to the first memory circuit 101 is completed, the write address value 117 for the first memory circuit output from the first address counter 116 increases from 1 to 2, and according to the write address value 117 The write circuit 118 generates a write signal 119 and writes the write data 105c of the second memory circuit into the second word of the first memory circuit 101.
is written. After the third write to the first memory circuit 101 is completed, the write address value 117 for the first memory circuit output from the first address counter 116 increases from 2 to 3, and according to the write address value 117. The write circuit 118 generates a write signal 119;
The write data 105d of the second memory circuit is written into the third word of the first memory circuit 101. After the fourth write to the first memory circuit 101 is completed, the write address value 117 for the first memory circuit output from the first address counter 116 increases from 3 to 4, and according to the write address value 117 The write circuit 118 generates a write signal 119, and the write data 105e of the second memory circuit is written into the fourth word of the first memory circuit 101. After the fifth write to the first memory circuit 101 is completed, the first address counter 116 outputs the first
The write address value 117 for the storage circuit increases from 4 to 5.

Next, according to the control signal 122 output from the output control circuit 121, the read address value 12 for the first storage circuit output from the second address counter 123 is changed.
4, the readout circuit 125 generates a readout signal 126, and outputs the write address of the second memory circuit read from the 0th word of the first memory circuit 101 and the write data size 108a of the second memory circuit. is written to the address register 109 of the second storage circuit and simultaneously output to the output control circuit 121. After the first reading of the first memory circuit 101 is completed, the read address value 124 for the first memory circuit output from the second address counter 123 increases from 0 to 1, and according to the read address value 124 The readout circuit 125 generates a readout signal 126 and writes the write data 108b of the second storage circuit read from the first word of the first storage circuit 101.
is written into the data register 111b of the second storage circuit. Here, it is assumed that the data register 111 of the second memory circuit has 16 bytes, and there are 111b to 111e divided into 4 bytes each, similar to the second memory circuit. After the second reading of the first memory circuit 101 is completed, the read address value 124 for the first memory circuit output from the second address counter 123 increases from 1 to 2, and according to the read address value 124. The read circuit 125 generates a read signal 126 and writes data 108c of the second memory circuit read from the first word of the first memory circuit 101.
is written into the data register 111c of the second storage circuit. After the third reading of the first memory circuit 101 is completed, the read address value 124 for the first memory circuit output from the second address counter 123 increases from 2 to 3, and according to the read address value 124. The read circuit 125 generates a read signal 126, and writes the write data 108d of the second memory circuit read from the first word of the first memory circuit 101 to the data register 111d of the second memory circuit. Write. After the fourth reading of the first memory circuit 101 is completed, the second address counter 12
The read address value 124 for the first storage circuit outputted by No. 3 increases from 3 to 4, and the read address value 124 outputs from No. 3 increases from 3 to 4.
24, the readout circuit 125 outputs the readout signal 126.
The write data 108e of the second memory circuit read from the first word of the first memory circuit 101 is written into the data register 111e of the second memory circuit. After the fifth reading of the first memory circuit 101 is completed, the read address value 124 for the first memory circuit output from the second address counter 123 increases from 4 to 5. After writing to the address register 109 of the second memory circuit and the data register 111 of the second memory circuit is completed,
Control signal 1 output from the control circuit 127 of the second storage circuit
28, the write address 10 of the second storage circuit is
The write data 105b to 105e of the second memory circuit can be written to the second memory circuit.

[0021]

Effects of the Invention As described above, according to the present invention:
It is possible to write data to the IFO circuit, ■ It is also possible to control reading of the FIFO circuit depending on the operating state of the second memory circuit, and ■ Furthermore, it is possible to write any data to any address in the second memory circuit. Since long individual data can be written to the FIFO circuit, it is very effective when a FIFO circuit is provided between the data processing device and the storage circuit. The present invention is extremely effective in practice in any data processing apparatus that performs data transfer.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a storage control device according to claim 1;

FIG. 2 is a block diagram showing an embodiment of the storage control device according to claim 2 of the present invention;

FIG. 3 is a block diagram showing an embodiment of a storage control device according to claim 3 of the present invention;

[Figure 4] Block diagram showing an example of a conventional FIFO circuit

[Explanation of symbols]

101...First memory circuit, 102...Second memory circuit, 103...Write address (of the second memory circuit),
104...Write data size (of the second memory circuit), 105...Write data (of the second memory circuit), 1
06...Selector, 109...Address register, 11
1...Data register, 113...Write request signal (to the second storage circuit), 114...Input control circuit, 11
6... (first) address counter, 118... writing circuit, 120... read inhibit signal, 121... output control circuit, 123... (second) address counter, 1
25...readout circuit, 127...control circuit (of the second storage circuit)

Claims (3)

[Claims] 1. A first memory circuit, a second memory circuit, a first address counter that controls a write address of the first memory circuit, and a first address counter that controls a write address of the first memory circuit. a write circuit that generates a write address for a memory circuit; a second address counter that controls a read address of the first memory circuit; and a write circuit that generates a read address for the first memory circuit according to the value of the second address counter. a read circuit that generates a write address and a write data of a second memory circuit, a selector that sequentially and alternately stores a write address and write data of a second memory circuit in a first memory circuit, the selector, the first address counter, and the write circuit. an input control circuit that controls the address register of the second memory circuit, a data register of the second memory circuit, and a write address and write address of the second memory circuit read out alternately from the first memory circuit in order. 1. A storage control device comprising an output control circuit for sequentially and alternately storing data in an address register and a data register of a second storage circuit. 2. The storage control device according to claim 1, wherein the output control circuit of the first storage circuit includes a read inhibit circuit, and a read inhibit signal to the read inhibit circuit inhibits reading of the first memory circuit. A storage control device that enables 3. The storage control device according to claim 1, by adding data size information of the write data and byte position information of the write data to the free area of the write address of the second storage circuit. A storage control device that makes it possible to write write data to a second storage circuit into a designated byte position.