JPS6116364A - Vector data processor - Google Patents

Abstract

PURPOSE:To transfer element data between vector storage means in a high speed by transferring directly element data from the first vector storage means to the second vector storage means having an optional start address. CONSTITUTION:A vector data processor is provided with vector registers 100 and 101, read address registers 110 and 111, write address registers 120 and 121, read address selecting circuits 130 and 131, write address selecting circuits 140 and 141, and an element data input selecting circuit 200. Vector registers 100 and 101 hold plural sequenced element data respectively, and element data read out from the vector register 100 or 101 are transferred successively to the vector register 101 or 100. In this case, write address registers 120 and 121 set optional start addresses.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical field to which the invention pertains The present invention relates to a vector data processing device that transfers element data between vector registers.

(2) Prior art A conventional vector data processing device is disclosed in U.S. Patent No. 41238.
Reference can be made to Publication No. 80. Referring to FIG. 2, according to this publication, vector registers 10 and 11, read/write
It is composed of write address registers 20 and 21, an element data input selection circuit 30, an element data output selection circuit 40, and an arithmetic unit 50.

Each of the vector registers 10 and 11 holds a plurality of element data, and usually a plurality of vector registers are provided. Read/Write Address Registers 20 and 21
is used to designate the location of the element data held in the vector registers 10 and 11, and is cleared to "0" in the initial setting, and has a +1 count function.

When performing a partial vector operation on element data held in one vector register, it is necessary to transfer part of the element data held in this vector register to another vector register.

For this purpose, a method is used to transfer element data using a store/load instruction between a micro register and a main memory, or a method is used to transfer element data using a shift instruction.

In the former method, the element data held in the vector register 10 is sequentially stored in the main memory by the vector length specified by the store instruction t-b, and part of the stored element data is loaded into the vector register 11. Ru. First, in response to the designation of the transfer source vector register 10 and the transfer vector length in a store instruction, the read/write address register 20 is initialized to @0''. 1
Location code of element data held in 0
is output to the element data output selection circuit 40, and as the read/write address register 20 counts up, the element data are output in sequence. The outputs of the vector register 10 applied via the element data output selection circuit 40 are sequentially transferred to the main memory. Next, in response to the load start address of the element data necessary for partial vector operation in the load instruction, the load destination vector register 11, and the vector length designation, the vector is transferred from the main memory according to the instructions of the read/write address register 21. Element data is sequentially loaded into the register 11.

In the latter method, the element data held in the vector register 10 is shifted by 91 words by a shift command and transferred to the vector register 11.

When the shift command specifies the vector register 10 that holds the element data to be shifted, the vector register 11 that transfers the shift result, the shift amount and vector length, as the read/write address register 20 counts up, the vector register 10 The held element data is sequentially output from location 0 to the element data output selection circuit 40.

The output of the vector register 10 provided via the element data output selection circuit 40 is sent to the arithmetic unit 50. The arithmetic unit 50 performs a shift operation in response to the output of the element data output selection circuit 40 and the shift amount specified by the command.

The shift amount is usually specified as a one word shift to the right. By shifting the element data to the right by one word and outputting it, the arithmetic unit 5
The output of 0 is transferred to the vector register 11 via the element data input selection circuit 30 in a format shifted by one word.

The read/write address register 21 also has a +1 count function and sequentially specifies the location of element data output from the element data input selection circuit 30.

By repeating this shift operation, the predetermined element data transfer is completed. Therefore, since both methods require a main memory or an arithmetic unit, the performance of element data transfer is low, and there is a disadvantage that there is contention when a subsequent instruction requires the main memory or an arithmetic unit.

(3) Object of the Invention The object of the present invention is to transfer element data directly from the first vector storage means to the second vector storage means starting at an arbitrary address, thereby enabling high-speed transfer of element data between vector storage means. An object of the present invention is to provide a vector data processing device that can transfer element data.

(4) Configuration of the Invention The vector data processing device of the present invention includes a first vector storage means for holding ordered element data;
A transfer means for sequentially transferring the element data read from the first vector storage means to a second vector register, and an arbitrary write start address of the second vector storage means is set when the element data is transferred by the transfer means. and address setting means.

(5) Examples of the invention Next, the present invention will be explained in detail with reference to the drawings.

Referring to FIG. 1, one embodiment of the present invention includes a vector register 100 and a 101% read address register 1.
10 and 111. Write address register 120 and 121% read address selection circuits 130 and 13
1, write address selection circuits 140 and 141, and element data input selection circuits 2 million.

The operation of this embodiment is as follows.

A plurality of vector registers, two vector registers 100 and 101 in this embodiment, each hold a plurality of ordered element data, and each holds a plurality of ordered element data, such as a calculation result output from an arithmetic unit or a load output from the main memory. Store data. When performing a partial vector operation on element data held in one vector register, it is necessary to transfer part of the element data held in this vector register to another vector register.

The vector register 100 is the transfer source that holds the calculation result output from the arithmetic unit or the load data output from the main memory, and the vector register 100 is the vector register 100.
The transfer destination register to which part of the element data stored in l/register 100 is transferred is vector register 1.
01,! :, the number of the source vector register 100 and the number of the destination vector register 101 are specified by the instruction. The read start address to the transfer source vector register 100 is input to the read address selection circuit 130 as a command or instruction accompanying information, but if it is not specified by the command, @0'' is input.

Similarly, the write start address of the transfer destination vector register 1 is input to the write address selection circuit 141 as a command or instruction accompanying information, but if it is not designated by a command, 101 is input.

Note that the setting paths for these start addresses are not shown.

On the other hand, if the source vector register number specifies vector register 101 and the destination vector register number specifies vector register 100, then the read start address of the source vector register is the instruction or The information is input to the read address selection circuit 131, and the write start address of the transfer destination vector register is similarly input to the write address selection circuit 140 as an instruction or instruction accompanying information. In these cases as well, IO'' is input if it is not specified by the instruction.

Note that the setting paths for these start addresses are also not illustrated.

The maximum element data length that can be held in vector registers 100 and 101 is 64 pieces each, and when transferring 32 pieces of element data from vector register 100 to vector register 101, L% is first specified by an instruction that specifies the vector length as 132''. Specify the source vector register number as vector register 100, the destination vector register number as vector register 101, and set the read start address of vector register 100 as "3".
2". The read start address specified by the instruction is input to the read address selection circuit 130, selected, and the value of w321 is stored in the read address register 110. At the same time, the write start address is specified by the instruction. Therefore, I o 1 is input to the write address selection circuit 141. This is selected and 101 is initialized to the write address register 121. The vector register 100 stores the element data at the location specified by the read address register 110. is outputted to the element data input selection circuit 200.The read address register 110 has a +1 count function in order to sequentially read out the element data. The element data held in the vector register 100 for the specified vector length is read out at the counted location and output to the element data input selection circuit 200.Element data input selection circuit 2
00 selects and instructs the element data read from the vector register 100 to be input into the vector register 101.

On the other hand, the vector register 101 starts writing element data to the location specified by the write address register 121 at the time when the first element data is output from the element data input selection circuit 200. Like the read address register 110, the write address register 121 also has a +1 count function for sequentially writing element data, and the next location after location O is counted as location 11, followed by location 2. Element data output from the element data input selection circuit 200 is written to the counted location by the amount specified by the vector length. This operation ends when the number of element data transferred reaches 132'', that is, equal to the vector length specification.

When the read start address of the transfer source vector register is defined as m, if a value of 64-(m-1) or more is specified by the vector length specification, the following will occur. That is, the read address register 110 is the vector register 100.
When the location reaches 63, the next location is designated as 0, and the function is to sequentially count by the designated number of vector lengths.

Assume that another instruction specifies the transfer source vector register number as vector register 100, the transfer source vector register number as vector register 101, and specifies the write start address of vector register 101 as 32. Since the read start address is not specified by the instruction, I o l is input to the read address selection circuit 130 , this is selected, and 101 is initialized in the read address register 110 . The write start address designated by the command is input to the write 7'' address selection circuit 141, selected, and a value of 132'' is stored in the write address register 121.

The read address register 110 has a +1 output count function. In response to the address from this register 11o,
Element data is sequentially read from location 0 of vector register 100 and output to element data input selection circuit 200. The write address register similarly has a +1 counter function, and starts writing when the element data input selection circuit 200 outputs the first element data, that is, the element data read from the 0 case O of the vector register 100. .

This operation ends when the number of transferred element data reaches 1321, that is, when it becomes equal to the vector length designation. Also, when the write start address of the transfer destination is m, if a value of 64-(m-1) or more is specified in the vector length specification, the write address register register 2
1, the location of the vector register 101 is 163
When the count reaches 1, the -to-next hocation returns to 0, and it has a function of sequentially counting by the specified number of vector lengths.

Furthermore, in another instruction, the transfer source vector register number is set to vector register 100. Specify the transfer destination vector register l as vector register 1o1, and transfer it to vector register 100.
Assume that the read start address of the vector register 101 is designated as '32', and the write start address of the vector register 101 is designated as '32'.

Read Ll? Since both the address and the write start address are specified by the instruction, the read address selection circuit 1
The start address 1321 is input to 30 and write address selection circuit 141, and 2 is selected, and the start address 1321 is input to read address register 110 and write address register 1.
21. The read address register 110 is +
Since it has a single input count function, vector register 1
The +i-order vector data is read from the location 32 of 00 and output to the element data input selection circuit 200. The write address register 121 also has a +1 output count function, and the element data input selection circuit 200
The output from the vector register 1
The data is sequentially written starting from location 32 of 01. This operation ends when the number of transferred element data - 4 ("32") is reached, that is, when it becomes equal to the vector length specification. Also, when the read start address and write start address are m and n, respectively. , if the vector length designation is greater than 64-(m-1), the contents of the read address register return from 63 to 0 and continue counting.

If the vector length designation is greater than 64-(n-1), the contents of the write address register return from 63 to 0 and continue counting.

In this embodiment, the number of vector registers is two, but the present invention is not limited to two, and the element data transfer source is the vector register 100, and the transfer destination is the vector register 101. It is not limited to , and can be specified arbitrarily by a command.

(6) Effects of the Invention The present invention provides means for setting an arbitrary read start address of the second vector storage means, and a means for transferring element data between the vector storage means. This has the advantage that transfer can be realized at high speed from any write start address.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention, and FIG. 2 is a diagram showing a conventional example. 10.11, 100, 10"1...Vector register, 20.21...Read/write address register, 30, 200...Element data input selection circuit, 4o01000. Element data output selection circuit, 50/beat/arithmetic unit, 110, 111...
...Read address register 120.121...
...Write address register, 130°131...
...Read address selection circuit, 140, 141...
...Write address selection circuit. ti+suIj1%# 工L/>) DEra 1N force*#E]! Each fI time! tsu￥＼ top

Claims (1)

[Claims] a first vector storage means for holding ordered element data; a transfer means for sequentially transferring the element data read from the first vector storage means to a second vector storage means; A vector data processing device comprising: address setting means for setting an arbitrary write start address of the second vector storage means.