JPH06318162A - Memory device - Google Patents

Abstract

PURPOSE:To provide a memory device by which a fetch address can be managed, and in which burden on software can be reduced, and with small address space for the storage of the fetch address. CONSTITUTION:This memory device is provided with counters 1, 2 which count the number of times of access on a RAM 4 when it is performed, and the write of the fetch address on the RAM 4 and the readout of it from the RAM 4 can be performed according to the contents of the counters.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device having a fetch address storage unit.

[0002]

2. Description of the Related Art In order to know the history of memory access, there is provided a fetch address storage unit for storing a large number of accessed addresses, that is, fetch addresses.

[0003]

For this purpose, a shift register of the required number of words (for example, 32) is used, and the storage and the shift are sequentially performed, but for reading, the address in the shift register is used. It is necessary to manage, the management of software is troublesome, and it has been a place where most of the address space is occupied by this shift register.

The present invention has been made in order to solve the above-mentioned problems of the prior art. By using a counter, the load of software management is reduced and the address space required for the fetch address is obtained. It is an object of the present invention to provide a memory device that can reduce

[0005]

According to another aspect of the present invention, there is provided a memory device having a fetch data storage unit for storing a fetch address, comprising two counters for counting signals related to access to the fetch data storage unit. The fetch data is written in the fetch data storage unit by using the content of one counter as an address, and the content of the fetch data storage unit is read by using the content of the other counter as an address.

A memory device according to a second aspect of the present invention is a memory device having a fetch data storage unit for storing a fetch address, which is provided with a counter for counting a signal relating to access to the fetch data storage unit, and uses the content of the counter as an address. It is characterized in that the contents of the fetch data storage unit are read out.

[0007]

In the first aspect of the invention, the counter is incremented or decremented each time the fetch address storage unit is accessed, and writing to the fetch address storage unit is performed according to the content of one counter, and the content of the other counter is also written. The contents of the fetch address storage unit are read in accordance with.

In the second invention, writing is performed in the shift register as in the conventional case, but reading is performed according to the contents of the counter.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings showing its embodiments. FIG. 1 is a block diagram showing a first embodiment of the present invention. In the figure, 7 is a CPU, 6 is a memory, and CP
The address when the U 7 accesses the memory 6, that is, the fetch address is given to the RAM 4 provided as the fetch address storage unit. When the CPU 7 accesses the RAM 4, the address designating the RAM 4 is output, and this is supplied to the write address counter 1 and the read address counter 2. Both of these counters 1 and 2 are given the address of the RAM 4, and writing (writing address counter 1) or reading (reading address counter 2) to the RAM 4 is performed.
Is counted up (or countdown)
I am supposed to do it.

The counting targets of these counters 1 and 2 are
It may be a chip select signal of RAM 4. One of the count contents of the counters 1 and 2 is selected by the address selector 3 and given to the RAM 4 as its write address or read address. The CPU 7 outputs a signal for selecting the counters 1 and 2 to the address selector 3. Register 5 is RAM
It is for storing the fetch address read from No. 4.

In the device of the present invention as described above, the CPU 7
Accesses the RAM 4 each time the memory 6 is accessed,
At this time, the address selector 3 is caused to select the write address counter 1. Then, the fetch address is written in the RAM 4 with the contents of the counter 1 at that time as an address. Since the write address counter 1 is incremented (or decremented) each time the memory 6 is accessed, recording of the memory 6 access is automatically performed.

On the other hand, if you want to read the contents of RAM 4, use CP
U 7 accesses RAM 4 and address selector 3
Is supplied with a signal for selecting the read address counter 2. Then, the fetch address written in the address corresponding to the contents of the counter 2 is read from the RAM 4 to the register 5.

FIG. 2 shows a case where a ring buffer type RAM 4 is used, the write address counter 1 is configured as an up counter, and the read address counter 2 is configured as a down counter. With such a configuration, the fetch address can be read from the most recently written one, that is, the most recently written one.

FIG. 3 is a block diagram showing an embodiment of the second invention. This uses a shift register 8 as a fetch address storage unit in the same manner as in the past, and a fetch address is given each time the CPU 7 accesses the memory 6, and writing and shifting are sequentially performed by a fetch signal. It is the one. However, in order to read the fetch address from the shift register 8, the counter 20 corresponding to the read address counter 2 is provided, and the CPU 7 gives a predetermined signal to the counter 20 each time the fetch address is read, and counts up this. (Or countdown)
Let The selector 9 selects the parallel output of the shift register 8 and reads the output of the corresponding stage to the register 5 according to the contents of the counter 20.

[0015]

As described above, in the device of the present invention, the writing and reading of the fetch address are executed by the hardware, the burden of software management is eliminated, and the fetch address storage unit occupies a large address space. The present invention has excellent effects such as no occurrence.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a first invention.

FIG. 2 is a conceptual diagram of a RAM.

FIG. 3 is a block diagram of an embodiment of the second invention.

[Explanation of symbols]

 1 write address counter 2 read address counter 3 address selector 4 RAM 6 memory 7 CPU 8 shift register 9 selector

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Hitoshi Maehara 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Limited

Claims (2)

[Claims] 1. A memory device comprising a fetch data storage unit (4) for storing a fetch address, comprising two counters (1), (2) for counting signals related to access of the fetch data storage unit (4). In order to write the fetch data to the fetch data storage unit (4) using the content of one counter (1) as an address, and to read the content of the fetch data storage unit (4) using the content of the other counter (2) as an address. A memory device characterized by being made. 2. A memory device comprising a fetch data storage unit (4) for storing a fetch address, comprising: a counter (20) for counting a signal relating to access of the fetch data storage unit (4). ) Is used as an address to read the contents of the fetch data storage section (4).