JPH01290052A - Cache memory - Google Patents

Cache memory

Info

Publication number
JPH01290052A
JPH01290052A JP63119353A JP11935388A JPH01290052A JP H01290052 A JPH01290052 A JP H01290052A JP 63119353 A JP63119353 A JP 63119353A JP 11935388 A JP11935388 A JP 11935388A JP H01290052 A JPH01290052 A JP H01290052A
Authority
JP
Japan
Prior art keywords
block
data
instruction
operand
block data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP63119353A
Other languages
Japanese (ja)
Other versions
JPH0727490B2 (en
Inventor
Yasuaki Kamiya
Kenji Nishikubo
Original Assignee
Nec Corp
Koufu Nippon Denki Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Corp, Koufu Nippon Denki Kk filed Critical Nec Corp
Priority to JP63119353A priority Critical patent/JPH0727490B2/en
Publication of JPH01290052A publication Critical patent/JPH01290052A/en
Publication of JPH0727490B2 publication Critical patent/JPH0727490B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PURPOSE: To set an optimum block size by storing the operand block data and the instruction block data in the form of set addresses.
CONSTITUTION: A cache memory 3 includes a data buffer 31, an address tag memory part 32, a valid information memory part 33, and a block information memory part 34. The buffer 31 uses an N-byte data block as its basic component block and the part 32 contains an address higher rank part in response to the basic block in 1:1. The part 33 has a single valid bit for each basic block and folds these valid bits for each block size (22 times as much as the operand block data) of the instruction block data and can read and write said bits at one time. The part 34 has the information of a single bit for each instruction block data and discriminates the instruction block data from the operand block data. Thus an optimum block size can be set.
COPYRIGHT: (C)1989,JPO&Japio
JP63119353A 1988-05-18 1988-05-18 Cache memory Expired - Lifetime JPH0727490B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63119353A JPH0727490B2 (en) 1988-05-18 1988-05-18 Cache memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63119353A JPH0727490B2 (en) 1988-05-18 1988-05-18 Cache memory

Publications (2)

Publication Number Publication Date
JPH01290052A true JPH01290052A (en) 1989-11-21
JPH0727490B2 JPH0727490B2 (en) 1995-03-29

Family

ID=14759392

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63119353A Expired - Lifetime JPH0727490B2 (en) 1988-05-18 1988-05-18 Cache memory

Country Status (1)

Country Link
JP (1) JPH0727490B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006510992A (en) * 2002-12-17 2006-03-30 インターナショナル・ビジネス・マシーンズ・コーポレーション Memory that can selectively change the line width

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006510992A (en) * 2002-12-17 2006-03-30 インターナショナル・ビジネス・マシーンズ・コーポレーション Memory that can selectively change the line width
JP4741844B2 (en) * 2002-12-17 2011-08-10 インターナショナル・ビジネス・マシーンズ・コーポレーション Memory that can selectively change the line width

Also Published As

Publication number Publication date
JPH0727490B2 (en) 1995-03-29

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