JPS6067990A - Picture information processor having density converting function - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to an image information processing device, particularly a storage device, having an image information density conversion function.

Prior Art and Problems Generally, image information is obtained by scanning a screen in the X and Y directions, storing the scanned output in a memory, and reading out the memory for recognition and other processing. In this case, as the scanning line density increases and the number of pixels per scanning line increases, the resolution increases, but the image information increases accordingly, and the image information memory that stores this increases. Generally, addressing is performed by simply stepping the address in both the X and Y directions, so the capacity of the memory increases as image information increases. If the image information is binary white/black information, the memory will be 1 bit per pixel, but if it contains shading or color information, the memory will be 1 byte per pixel.
The memory capacity will be enormous.

Purpose of the Invention The present invention aims to reduce the memory capacity for image information by controlling the access address of the image information memory, thereby making it possible to reduce the image information when writing, and conversely enlarge it when reading. be.

Structure of the Invention The present invention provides an image information memory that stores image information two-dimensionally, an address counter that specifies each address in the X direction and Y direction of the memory, and an address cursor in the X direction and the Y direction, respectively. In an image information processing device that includes a circuit that provides a step clock and a microprocessor that controls writing and reading to the memory, the step clock is sent to the circuit that provides the step clock once every plurality of times. The present invention is characterized by adding a function of inhibiting the output of 1 to 1, reducing the image information when writing to the memory, and enlarging it when reading 2. This will be explained in detail with reference to.

Embodiment of the Invention FIG. 1 is a schematic explanatory diagram of the present invention, in which A is a post computer and B is an image information processing device. The image information processing device B is
It includes a microprocessor unit (MPU) a, and writes (or reads) image information from a computer A into an image information memory h through an interface i. At this time, the address in the X direction of the memory h is controlled by the register b and the counter C1 address counter d, and the address in the Y direction is controlled by the register e, the counter f, and the address counter g to perform density conversion.

In this way, if the address in the X direction and the address in the Y direction are incremented normally, the image data will be written to the memory h without being lost, and will be read out without duplication, so there will be no change in density. doesn't happen. However, this requires a memory capacity equal to the amount of image information. On the other hand, if you stop advancing the address in the X direction every few times, the image data (
(1 bit or 1 byte) is overwritten, and the screen becomes
As a result, the memory capacity is reduced. The same goes for the Y direction; if you stop the address increment every few times, the X direction data group (scanning line) will overwrite the previous one every few times, and the screen will be overwritten. is reduced in the Y direction, reducing memory capacity.

Conversely, when reading, the same data is read twice from the stopped address.
By reading the image once, the screen is enlarged by that amount and returns to the original screen size. The reduction rate and enlargement rate are specified by MPU a, and numerical values corresponding to the rates are set in registers b and e. Each time the count value of counters c and f matches the value of registers b and e, address counter d1g
The step clock given to address counter d1g is stopped to temporarily stop the step of address counter d1g. A specific example will be explained below.

FIG. 12 shows details of an image information processing device showing an embodiment of the present invention, where ① is an MPU, 2 is a register (RE G) in which the address increment/stop rate in the X direction is set, and 3 is a register in the X direction. Counter (CNT) that counts the step clock XuP, '4
is ant game 1, 5 is the address counter in the X direction (X
-ADR), 8 is a register in which the Y-direction address increment/stop rate is set, and 9 is a Y-direction step clock (XCR).
A counter that counts 81 (logical product output of Y and XuP), 1
o is an AND gate, 11 is an address counter in the Y direction,
12 is an image (IM: image information) memory.

Only one row of image data WD in the X direction of the image memory 12
If you write , it will be as follows. First, REG from MPU1
2 is the number that stops the address increment in the X direction at a rate of once every arbitrary number of times. For example, if it is stopped at a rate of once every three times, its three's complement is written, and that number is further written to the p counter 3.
is set to

X direction address clock (CLK) input XuP
is inputted continuously, the XuP and the output of the counter 3 (output of the inverter 2o) are ANDed at the gate 4, and then inputted to the X-direction address counter 5. The clock XuP is counted by the counter 3, and there is no carry output (TC) until the counter 3 counts the set value 3, so the output of the inverter 20 is 1'', and the ant game 1
・Open 4th floor. Therefore, the clock XuP is Antogame-1.4
When the output of gate 4 is 1, address counter 5 increments, and the counted value becomes the write address of image memo IJ12. In this way, the Rye I data (picture information) WD is sequentially written to consecutive addresses in the X direction of the image memory 12. When the counter 3 reaches the set value 3 by the if number, it produces a carry output, which is inverted by the inverter 20 and closes the AND gate 4. Gate 4 output is O
At this time, the address counter 5 stops advancing, but since the clock XuP is separately input to the image memory 12 as a write enable (WE) signal, the image information WD
The next bit or byte is overwritten at the same address in memory 12 immediately before the address increment stops. Note that when overwritten, the stored information in the memory is replaced with new data, so the image information immediately before the address increment stops disappears. Further, at this time, the counter 3 is reset by the output of the inverter 20, and a value for stopping the increment of the address in the X direction is taken in again from the REG2. When the next clock of XuP is input, counter 3 starts counting again, and since there is no carry and AND gate 4 is open, address counter 5 also starts counting, and thus the X address advances, stops, advances, etc.・・・
. . . are repeated, and the image data WD is written to the entire column A of the image memory 12.

However, n pieces of input image data (in this example, one out of every three pieces) are thinned out and stored as image information.

The above is the operation of writing image information in a line in the X direction, but
Repeat this and, for example, store 1 in column A of the image memory 12.
When the image information for the column is written, the carry signal XCRY of the address counter 5 is turned on and inputted to the AND gate 21. Therefore, when the next clock XuP is input, the outputs of anime games 1 to 21 become 1 (until then they are 0), and A
Since this is repeated at each end of the column, B column, . . . , the output of the AND gate 21 becomes 1 nick for Y-direction address counting. Therefore, the counted value of the counting Y address counter 11 becomes the Y address of the image memory 12 by loading this through the Antogame 1-10, and this causes the A
The next image information in the column is written to column B of the memory 12, and so on. Similarly to the X direction, the address step in the Y direction repeats step and stop. Immediately, input a predetermined value from the MPUI to register 8 (a value that stops address increments in the Y direction at a rate of once every arbitrary number of times for image information density conversion).
is written and the value is set in the counter 9. The clock input of the counter 9 (output of the AND gate 21) causes the counter 9 to count, and when the set value is reached, a carry output is generated, thereby closing the AND gate 10 and stopping the counting of the Y address counter 11. Carry output Specifically, its inverted output by inverter 22 resets counter 9 and causes the contents of register 8 to be taken in.

The counter 9 starts counting again at the next clock (output of the anime game 1/21) and repeats the same operation. gate 1
When the output of 0 is 0, the counter 11 stops advancing, and the new one-column fraction information is overwritten on the previous column in the Y direction.

In this way, image information is thinned out and reduced in the Y direction as well.

Even when the image information written in the memory 12 is not read out, the same addressing (stopping of advancement) is performed. Reading is performed every 11 links of the clock XuP, so when the address increment stops, it is read twice, and as a result, the read data RD is the same as the write data WD, as far as the number of pixels (Pips 1 - or number of bytes) is concerned. Match. In this way, memory storage and retrieval can be performed with arbitrary density conversion. When writing and reading, if you change the address increment/stop ratio, the image information is compressed and written, and it is expanded beyond the original image information and #/CII
I can also do Zuko. This is an aid for displaying images, etc.

Effects of the Invention As described above, according to the present invention, image information can be compressed and stored, and as a result, image information memory can be used efficiently, and the output of image information can be enlarged to any size. There is an advantage that it is also possible.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram of the present invention, and FIG. 2 is a block diagram showing an embodiment of the present invention. In the figure, A is a computer, B is an image information processing device, 1, a
is MPU, 2, 8. b, e are registers, 3゜9, c, f
is a counter, 5, 11. d and g are address counters, 1
2. h is an image information memory.

Claims (1)

[Claims] An image information memory that stores image information two-dimensionally, an address counter that specifies each address in the X direction and Y direction of the memory, and an increment in each of the X and Y direction address counters. In an image information processing device that includes a circuit that provides a clock and a microprocessor that controls writing and reading to the memory, the circuit that provides the step clock is provided with the step clock once every plurality of times. An image information processing device having a density conversion function, characterized in that it has an additional function of inhibiting output, and is capable of reducing image information when writing to the memory and enlarging it when reading.