JPS6040053B2 - image storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital memory device, and more particularly to a memory device that enables high speed read/write regardless of the memory read/write speed due to the memory elements.

In general, digital signals such as characters, figures, images, etc. that are processed by an information processing device such as an electronic computer (hereinafter simply referred to as a computer) are converted into analog signals by a digital-to-analog converter (hereinafter simply referred to as a DAC). In order to display the digital signal on a TV display device, the digital signal is first stored in a buffer memory, and then the image memory is synchronized with the TV and displayed on the TV display device. etc., but the Japanese standard method T
A V display device can display 512 pixels horizontally by 512 pixels vertically. Therefore, if the gradation of one pixel is 8 bits, an image memory of 25 bytes is required.

In addition, when displaying a color image on a color TV display device using image information of the three primary colors of red, green, and blue, 25 thigh bytes x 3 = 76
A large-capacity image memory of approximately one byte is required. Further T
The effective horizontal display time of the V display device is 53.5 microseconds or less, and the display time of one pixel is 100 nanoseconds or less, so display information is stored in the image memory for 100 nanoseconds or less.
It is necessary to read out data at high speeds of nanoseconds or less. That is, a high-speed and large-capacity memory is required as an image memory. Nowadays, memory devices are becoming denser and
Although it has become faster and cheaper, it is clear that if the above-mentioned image memory is constructed from memory elements with a cycle time of 100 nanoseconds or less, it will become a very expensive memory equivalent to that of a large computer. Conventionally, as a means to solve this problem, for example, an image memory of 25 bytes is configured from one memory card with a memory capacity of 1 byte, and the data at a specified address is simultaneously output from each memory card in parallel and sent to the outside. Selectively output the output data; that is, perform parallel-to-serial conversion.

By doing this, the number of cycles to the image memory is 11, and it is possible to use a very inexpensive memory element, but the number of signal lines for the data connected to the outside is 8 to 8 ×
16 = 12 gold coins.

Furthermore, when writing digitized data from a television camera device or the like into an image memory, it is necessary to perform serial-to-parallel conversion externally, contrary to when reading data. Therefore, more than 200 data signal lines are required between the outside and the image memory, including address signal lines, control signal lines, and input/output lines, which increases the complexity of the connection with the image memory, and even parallel −
It has the disadvantage of requiring serial conversion or parallel-to-serial conversion.

An object of the present invention is to provide an image memory that enables high-speed reading and writing without providing external parallel-to-serial conversion or serial-to-parallel conversion.

Another object of the invention is to provide an inexpensive image memory by using high density and relatively slow memory elements.

A further object of the present invention is to provide an image memory that allows not only general reading and writing but also high-speed reading and writing with a simple circuit configuration.

According to the present invention, a signal for selecting a specific memory card (hereinafter referred to as a card selection signal) is generated by decoding a multi-bit card address signal for selecting one memory card from a plurality of memory cards. a read data register which latches the read data of the memory described later by the read data set signal and outputs the contents of the register to the output data bus by the card selection signal, the card selection signal and the write data set signal. a write data register for latching write data by a write designation; a first means for enabling reading of the memory regardless of the card selection signal by a write designation; - A second means for holding a write request by a set signal and enabling writing after a predetermined time; and a second means for enabling reading and writing by the card selection signal when there is no output designation and no write designation. 3, a timing signal (hereinafter referred to as CE signal - chip enable signal) that enables memory reading and writing, and an address signal made up of multiple bits to transfer the stored data from the address specified by the stored data register to the outside of the stored data register. A memory card comprising a memory that outputs the data and writes the contents of the write data register to an address specified by the address signal using the CE signal and a timing signal (hereinafter referred to as WE signal - write enable signal) that specifies writing. An image memory consisting of a plurality of images can be obtained.

The image memory of the present invention is ideal for use in image memorandum of color display devices necessary for conference room processing in digital image processing systems using recent meteorological satellites, resource satellites, etc., and medical-related computers. As the memory which requires a large capacity memory suitable for a computer, a high-density and inexpensive MOSIC memory element can be used, which has a great effect.

Next, the present invention will be explained using the drawings.

FIG. 1 shows the connection with an image storage device 1 consisting of single mother and daughter memory cards 0 to 15 which enable high speed reading and writing using the conventional method.

In the case of reading, data 0 is output from the address specified by the address signal 201 from each memory card 0 to 15.
.about.15 are simultaneously output, input in parallel to the P-S conversion circuit 3, read data 203 designated by the card address signal 200 is selectively output, and parallel-to-serial conversion is performed. If the read data 0 to 15 of each memory card 0 to 15 is 8 bits, the number of signal lines to the P-S conversion circuit 3 is 8 x 1.
6 = 12 dollars, which is a very large number. In case of writing,
Contrary to the case of reading, the S-P conversion circuit 2
02, selects and outputs the write data 0 to 15 specified by the card address signal 200, and when all the write data 0 to 15 to the memory card 0 to 15 are confirmed, the memory specified by the address signal 201 is output. -Written to the addresses of cards 0 to 15. If the write data 0 to 15 is 8 bits, the number of signal lines with the S-P conversion circuit 2 is 8×16.
= 12$ book. In other words, this method has the disadvantage that the number of output data lines and write data lines with the memory is extremely large, 256, and that the P-S conversion circuit 3 and the S-P conversion circuit 2 are provided externally. be. FIG. 2 shows the connection of an image storage device according to the invention. An address signal 201 is sent to the image storage device 1 from an information processing device (not shown) such as a computer.
A card address signal 200 and a control signal 206 are output. The respective signals 200, 2 from the respective circuits 4, 5, 6
01 and 206 are wired-ORed and input to memory card 0 to memory card 15 in the image storage device. The read data signal 203 from the image storage device 1 is wire-ORed with the read data signals 203 of each memory card 0 to 15 within the image storage device 1 and output. In this way, the number of connections of data signals input and output to the image storage device 1 is reduced to 1/16 compared to the conventional method shown in FIG.

FIG. 3 shows an embodiment of a memory card used in the present invention.

A thick line indicates a plurality of signal lines, and a pongee line indicates one signal line. The signal line indicated by a thick vertical line indicates a signal bus commonly connected to each memory card in the image storage device. Address signal 201 from the address bus is connected directly to address terminal A of memory 0. Card address signals 200 from the card address bus (CA3, CA2,
CAI, CAO) are input to inverters 40-43.
The outputs of the inverters 40 to 43 are terminals C3, C2, C1,
It is connected to CO and input to inverters 44-47.

The outputs of the inverters 44 to 47 are at terminals C3, C2, C1,
C river is connected. Each memory card 0-15 is connected to terminals D3-D by a pre-assigned card address.
0 is selectively connected to terminals C3-CO and C3-CO. For example, in memory card 0, terminal 03 is terminal C3,
Terminal D2 is connected to terminal C2, terminal DI is connected to terminal C1, and terminal DO is connected to terminal DCO. As a result, when the card address 200 (CA3 to CAO words) becomes a pre-assigned card address, the card selection signal 100 for selecting one memory card from memory cards 0 to 15 is sent to the AND gate 20. is output from. In the write data register 11, a write data signal 202 is set by the write data set signal 106 gated with an AND gate 22 by the card select signal 100.
In the read data register 12, a read signal 205 from the memory 10, which will be described later, is set by an output data set signal 104, and an output data signal 203 is output from the card selection signal 10 to the output data bus. FF13 is
The Q signal 111 is in a state where it can become "1" due to the write designation signal 101, and the Q signal 111 becomes "1" due to the write data set signal gated by the AND gate 22 and gated by the NAND gate 34. Become. Also D
Since the terminal is always "0", the Q signal 1 1 1 becomes "0" when the CE signal 103 gated by the NAND gate 30 is input to the CP terminal. For example, FF13 is SN7474N manufactured by Texas Instruments.
These operations are well known as digital techniques. That is, when the memory card is selected at the time of write designation, the Q signal 111 of the FF 13 becomes "1" by the write data set signal 106, and becomes "0" by the CE signal 30 gated by the NAND gate 30. Become.

The NAND gate 31 receives the Q signal 111 of the FF 13 as “
1", the upper one is inverted by the inverter 48 D3
When the terminal is “0”, it becomes “0”.

The NAND gate 32 is set when the write designation signal 101 and the read designation signal 102 are "0" and the card selection signal 100 is "0".
1”, it becomes “0”.The NAND gate 33
When the ND gate 31 or the NAND gate 32 becomes "0", it becomes "1", and when the read signal 102 becomes "1", the inverter 50 becomes "0", so the NAND
The D gate 33 becomes "1".

The AND gate 23 turns the NAND gate 32 to "1", thereby enabling memory writing and data output.
The E signal 103 is output as a signal 108 to the CE terminal of the memory.

The WE signal 105 that enables memory writing is AND
The signal is gated by the output of the NAND gate 33 at the gate 21 and input to the WE terminal of the memory 0. memory 10
is the output signal 108 of the AND gate 23, and A
The output signal 109 of the ND gate 21 converts the write signal 204 from the write data register 11 into the address signal 201.
Write to the memory 0 address specified by . Further, when the WE signal 109 is not present, the memory 10 outputs the contents of the address specified by the address signal 201 as a read signal 205 by the CE signal 108. Next, with reference to the time chart of FIG. 4, the operation when specifying a riddle will be explained.

During the period P when the address signal 201 is i, the CE signal 103 is related to the card address signal 200 (CA0, CAI, CA2, CA3) in order to set the output signal 110 of the NAND gate 33 to "1" by the mysterious output designation signal 102. It is input to the CE terminal of the memory 10 of each memory card 0-15. That is, the contents of the i address of the memory 10 specified by the address signal 201 of each memory card 0 to 15 are simultaneously read out, and the output signal 205 is output.
A read data set signal 104 delayed from the CE signal 103 in consideration of the access time of the memory 10 is input to the output data register 2, and the output signal 205 is latched. At this point, each memory card 0~
This means that the contents of the i address of each memory 0 are latched into the 15 read data registers 12. Also, at this point, the card address signal 200 (CA0, CAI
, CA2, CA3) become “0” and the memory card 0
Since the card selection signal 100 becomes “1”, the memory
A read data signal 203 from the read data register 12 of card 0 is output to the read data bus. Clock signal inside the circuit in Figure 2 (not shown in detail)
Therefore, the card address signal 200 becomes "1" at the next time, and the card selection signal 100 of the memory card 1 becomes "1".
”, so the read data signal 203 of memory card 0
is output on the read data bus. Thereafter, the card address signal 200 is sequentially changed to 2, 3, . . . by the clock signal.
...15, memory cards 2, 3, etc.
- A read data signal 203 from each of the 15 logical data registers 12 is output to the logical data bus. Now, while the read data signal 203 when the address signal 201 is "i" is being read, the address signal 201 is "i+".
1", and the CE signal 103 for reading the contents of the "i+1" address is input to the memory 10. At this point, the read data 205 of the "i+1" address is output from the memory 10 of each memory/loader. The read data signal 203 from the memory card 15 is output, and at the same time as the next clock signal, the read data set signal 104 causes the read data register 12 of each memory card to contain the memory ID ''. i+1” address contents are latched, and at the same time card address signal 200 becomes “0”
Then, the read data signal 203 of memory card 0 is output to the read data bus, and the same operation is performed thereafter. In this way, the synchronization P at which each memory 10 operates is one period of the clock signal, so even if the clock signal is 100 nanoseconds, the period P is 1.6 microseconds, and today's IC Memo Kawakoo It is possible to use very low cost and inexpensive memory. Here, in period P, the card address signal 200 is 0, 1, 2...1
5 and the operation that changes in a sequential order has been described, but the card address signal 200 may change in any manner. Next, the operation when writing is specified will be explained with reference to FIG. In period P, write data set signal 10
6 along with card address signals 200 (CA0, CAI
, CA2, CA3) are sequentially 0, 1, 2,...1
It changes to 5.

As a result, the write data signal 202 is sequentially latched in the write data register 11 of each memory card 0-15. Also, the Q signal 1 1 1 of the FF 1 3 becomes "1".

For example, the Q signal 111 of the memory card 2 becomes "1" at the time indicated by the arrow 51, and the Q signal 111 of the memory card 15 becomes "1" at the time indicated by the arrow 52. In the second half of period P, that is, in the period 8 to 15 for card address signal 200, card address signal 200
Since CA3 becomes “1”, the 03 terminals of memory cards 0 to 7 become “0”, and the inverter 48 causes the NAN
One input of the D gates 30 and 31 becomes "1". NA
Since the Q signal 111, which is the other input of the ND gate 31, is "1" as described above, the output voltage of the NAND gate 31 is "0", and the output signal 1 of the NAND gate 33 is "1".
10 becomes "1", and the WE signal 105 and CE signal 103 input to the AND gates 21 and 23 can be input to the memory 10.

At this point, the address signal 201 of the memory 10 is "i", so in the first half of the period P, the memory IJ/card 0~
The write data signal 202 latched in each write data register 11 of 7 becomes the CE signal 1 indicated by diagonal lines in the latter half of the period P.
03, memory cards 0 to 7' by WE signal 105
It is written to the 'i' address and when the write operation is completed, N
At the falling edge of the CE signal 103 indicated by the arrow 61 gated by the AND gate 30, the FFs of memory cards 0 to 7 are
The Q signal of signal 13 becomes "0". On the other hand, in the latter half of the period P, the write data signal 202 is sequentially latched in each write data register 11 of the memory cards 8 to 15, and
The Q signal 111 of F13 becomes "1". next period P+1
In the first half of the period P, the operation is the same as in the second half of the period P, i.e. CA3 of the card address signal 200.
becomes “0”, and the D terminals of memory cards 8 to 15 become “0”.
0”, and the NAND gate 30 is turned on by the inverter 48.
, 31 becomes "1". NAND gate 3
Since the other Q signal input to 1 is "1", the output of NAND gate 31 becomes "0", the output signal 110 of NAND gate 33 becomes "1", and the output signal 110 of NAND gate 33 becomes "1". , 23, the WE signal 105,
The CE signal 103 can be input to the memory 01.
Thus, in the second half of period P, write data signal 2 is latched in write data register 1 of memory cards 8-15.
02 is written to the "i" address of memory 10 of memory cards 8-15 during the first half of period P+1. When the write operation is completed, the arrow 62 gated by the NAND gate 30
When the CE signal 103 falls as indicated by , that is, the writing operation is completed,
The holding of 3 is released and the Q signal becomes "0". Thereafter, the same operation is performed while changing the address signal 201 sequentially.
In this explanation, the card address signal 200 is 0, 1,
Although the case where the signal starts from 2, . In other words, when writing is specified, card address signal 2
00 generates a card selection signal 100, and FF1
A write operation is performed on the memory 1O' only when the Q signal 111 of No. 3 is "1". As is clear from this figure, the period P in which each memory 0 operates is one stitch of the period of the write data set signal 106, so even if the period of the write data set signal 106 is 100 nanoseconds. The period P is 1.6 microseconds. Although the memory 10 in the embodiment is of a type that uses a chip enable (CE) signal, if the CE signal is not required, the output signal of the inverter 48 and the write enable (WE) signal are used as inputs to the NAND 30. In either case, the falling edge of the signal is used as the write operation end signal and serves as a clock to release the holding of the FF 13 and set the Q signal to "0". Now, in recent years, large-capacity image storage devices are used in digital image processing systems, and high-speed data input devices such as TV cameras are used as input devices.

Also, color TV monitors have often been used as non-standard output devices.

According to the present invention, not only can an image storage device suitable for these uses be provided at low cost, but also it can be used as a data buffer for high-speed data transfer.

Brief Description of the Drawings Figure 1 is a connection diagram between a memory and an external circuit to enable high-speed writing and high-speed reading using a conventional method, and Figure 2 is a connection diagram between an image storage device according to the present invention and an external circuit. , FIG. 3 is a diagram showing an embodiment of the present invention, and FIG. 4 is a time chart of the main parts of FIG. 3 in high-speed issue designation.

FIG. 5 shows a time chart of the main parts of FIG. 3 when specifying high-speed writing. In the figure, 1 is an image storage device, 2
is an S-P conversion circuit, 3 is a P-S conversion circuit, 1-0, 1-1...1-15 is a memory card in the image storage device, 11, 12 is a register, 13 is a Flip-flops, 20-23 are AND gates, 30-34 are NAND gates, and 40-50 are inverters.

O diagram O 2 diagram is 3 figures Moth figure 4 is figure 5

Claims (1)

[Claims] 1. In an image storage device for storing image information in an information processing device such as a computer, a decoder receives a signal from a card address bus and generates a card selection signal when the corresponding card address signal is received, and the decoder output signal and a control signal. a circuit that receives the write data set signal of the bus and generates a latch signal; a write data register that receives the latch signal and latches the data signal of the write data bus; and a circuit that receives the write data set signal of the control signal bus and generates a latch signal; A write designation holding circuit holds a write designation by the latch signal and releases the hold by a write end signal of the control signal bus, and generates a write signal by the output signal of the write designation holding circuit and the write enable signal of the control bus. a gate circuit for storing the write data register output signal at an address designated by the address signal on the address bus; and a memory for storing the write data register output signal in the address designated by the address signal on the control signal bus. An image storage device characterized in that a plurality of memory cards including a read data register for setting read stored data and outputting data to a read data bus in response to the data output signal are arranged so that the card addresses are different from each other. Device.