JPS62296278A - Image memory control system - Google Patents

Abstract

PURPOSE:To simplify software for a microprocessor and to speed up processing by bit-developing image data cocurrently fetched from an external device such as a scanner, storing said data in an image memory and making bit development complying with a bit operation instruction unnecessary. CONSTITUTION:An initial address is set to an address counter 22 from a microprocessor through an address data line 2c, and the parallel image data is set to a shift register 21 through a data line 2a. When the microprocessor gives a write command to a control part 23 through a control line 2d, the control part 23 gives to a memory 24 a required memory write signal 2g matching for the write cycle of the memory 24 in synchronization with a shift clock 2f that controls operations to shift the shift register 21. Moreover the control part 23 gives an increment control signal 2h to the address counter 22 and controls increment. In such a way the image data is written in the image memory 24.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention (Field of Industrial Application) The present invention relates to a control system for an image memory in a character recognition device, an image processing device, etc.

(Prior Art) In recent years, it has become possible to realize character recognition devices and image processing devices using 16-bit high-performance microprocessors.

In these devices, when image data is input from an external image scanner, etc., multiple bits (dots) are input in parallel in byte units or word units, and are generally bit-expanded and converted into images using bit manipulation instructions from a microprocessor. Since it was stored in memory, it was an impediment to improving processing speed.

That is, in a character recognition device or the like, first, binarized image data is taken in from an external device such as an image scanner and stored in the image scanner.

Multiple pixel data is given in parallel from the outside as shown in Figure 4(b), but in consideration of subsequent processing, it is bit-expanded and stored in the image memory in a form that can be addressed (referenced) pixel by pixel. There is a need.

When these devices are configured using a microprocessor, it is necessary to expand these parallel image data using shift operations and bit manipulation instructions of the microprocessor. These operations take time, so processing This was an impediment to speed improvement.

(Problems to be Solved by the Invention) The present invention aims to solve these conventional problems in character recognition devices and image processing devices, make image data input efficient, and improve processing speed. This is the purpose.

(Means for Solving the Problems) In order to achieve the above object, the basic configuration of the image memory control method of the present invention is as follows. ! means for loading image data consisting of several bits in parallel and giving it as memory write data one bit at a time while sequentially shifting; means for incrementing memory address information given from the outside in synchronization with the shift operation; The commands control memory writing, address information increment, and shift operations.1. The present invention is characterized by comprising a control section which notifies the outside after writing of predetermined image data is completed;

Further, in another configuration of the present invention, in the method having the above-mentioned basic configuration, an output signal of the means for providing one bit at a time as memory write data is further inputted, and the number of black pixels included in the output signal is counted. It has a configuration in which a means for holding it is added.

Further, according to an embodiment of the present invention, the counting and holding means includes an addition means and a means for holding the addition result, and the addition means supplies the above-mentioned one bit at a time as memory write data. It is characterized in that it is configured to add the output signal of the means and the output signal of the means for holding the addition result.

Furthermore, another embodiment of the present invention: Accordingly, the counting and holding means comprises a memory means for storing the count result, a means for prompting and incrementing the address of the memory means, and a means for accelerating and incrementing the address of the memory means. reading from means;
register means for holding write data; means for setting the number of dots in the horizontal direction and decrementing the number in synchronization with the shift operation;
It is characterized by comprising an adding means for adding the output signal of the means bit by bit as memory write data, and counting the image data while looking at the eyebrows, and storing the result in the memory means.

(Function) Image data consisting of multiple bits supplied in parallel from the outside is sequentially given to the memory one bit at a time by a shift operation, and in synchronization with the shift operation, the write address initially set from the outside is incremented. By controlling the parallel image data to be automatically expanded dot by dot, addressed, and written to the image memory, there is no need for bit expansion using bit manipulation instructions from an external microprocessor, resulting in efficient writing. It is possible.

Further, the present invention can have a configuration in which a means for counting and retaining the number of black pixels in a signal supplied in bits is further added to the above basic configuration, thereby improving the processing speed of the device. Be able to do that.

(Embodiment) FIG. 1 is a block diagram showing a first embodiment of the present invention, in which parallel data is bit expanded and written into an image memory.

The device of this embodiment includes a shift register 21, an address counter 22, a control section 3, and a memory 24. The shift register 21 receives image data consisting of a plurality of bits in parallel from an external microprocessor, and sequentially shifts the data and outputs it bit by bit as memory write data. The address counter 22 is set with the initial value of the memory address by the microprocessor.
The contents are incremented in synchronization with the shift operation of the shift register 21, and memory addresses are sequentially generated. The control section 23 controls operations of various sections such as memory writing, address information incrementing, and shift operations based on instructions from the microprocessor. The memory 24 is an image memory in which image data can be addressed dot by dot.

The operation of the apparatus of this embodiment configured as shown in FIG. A memory 24 for logically storing images in two-dimensional space.
We will explain the case where the data is stored in .

First, the microprocessor sets the Hatsutomo address to the address counter 22 via the address data line 2c,
Parallel image data is set in the shift register 21 via the data line 2a.

Thereafter, when a write command is given from the microprocessor to the control unit 23 via the control line 2d, the control unit 23 shifts the necessary memory write signal 2g in accordance with the write cycle of the memory 24. It is applied to the memory 24 in synchronization with the shift clock 2f that controls the shift operation of the register 21. Roughly, the control unit 23 sends an increment control signal 2h to the address counter 22.
is given to perform increment control. In this way, the image data of a predetermined number of bits input in parallel into the soft register 21 is shifted one bit (one dot) at a time while incrementing the address, from which it is bit expanded and stored in the memory 24. When the writing is completed, the control unit 23 sends a control signal to the microprocessor.
The termination is notified via the l line 2e. Note that the signal notifying this end may be a ready signal notifying the microprocessor of the end of the specified memory access. In this embodiment, image data taken in parallel from an external device such as a scanner can be bit-expanded using a shift register 21 and an address counter 22, and can be efficiently written into a memory.

Next, other embodiments of the present invention will be described.

In a character recognition device or the like, it is sometimes desired to count the number of black pixels in the X direction and Y direction as shown in the fourth ffl(c) in preprocessing/cutting out processing, etc. prior to recognition processing. Overcrowding was done by scanning the image memory after storing the data;
If you can count it, it will lead to a significant improvement in processing speed. An embodiment of the present invention that achieves these is shown in FIGS. 2 and 3.

The embodiment shown in FIG. 2 has the structure of the embodiment shown in FIG.
It has a configuration in which a circuit consisting of an adder 25 and a register 26 that holds the addition result is added. The output of the shift register 21 is given to the memory 24 and at the same time the adder 2
5 is also added to the contents of register 26, and the result is stored in register 26 again. Note that the contents of the register 26 are initially cleared to 0 by the microprocessor. The input of this register 26 is controlled by the control unit 23.
The control line 2k is synchronized with the shift operation of the shift register 21.
Be controlled through. Further, the contents of this register 26 can be opened at any time via the data line 2m when the next write command is issued after the control section 23 notifies the microprocessor of the completion when no shift operation is being performed. It is possible to read/write 1v.

FIG. 3 shows an embodiment in which the number of black pixels "1°1" on the same column as viewed in the Y direction in FIG. 4(c) is counted and the result is stored in the second memory. It shows.

In FIG. 3, a shift register 31, a first address counter 32, a first memory (image memory) 34, and a control section (part) 33 of these are the same as the shift register 21 in the embodiment of FIG. 1 or 2, respectively. , address counter 22, memory 24, control section 23, etc. An adder 35 and a first data register (which is a read register for the second memory) 36 are provided to count the number of black pixels "1'" on the same column as viewed in the Y direction. These correspond to adder 25 and register 26 in the embodiment of FIG. A second data register (write data register for the second memory) 37 that temporarily holds the output of the adder 35 to store the count results of the black pixels, a second address counter 39, a second memory 38, etc. It has a count result memory section consisting of. Further, a counter 40 is provided to monitor the completion of one row (Y direction) of the first memory.

The number of data to be written in the first memory 34 per row is set in the counter 40 via the signal line 3t, and is decremented by the control signal 3s from the control unit 33 in synchronization with the shift operation of the shift register 3. Ru. counter 4
When the content of 0 becomes 0, a signal indicating this from the counter 40, that is, a signal indicating that writing of one row of pixel data to the first memory (image memory) 34 has been completed, is controlled via the control line 3. Department 33 is notified.

Further, in synchronization with the decrement of the counter 40, the control unit 3
The contents of the second address counter 39, which holds the address of the second memory 38, are also updated by the control signal sent from the controller 3 through the control line 3q.

When the control unit 33 receives a signal indicating the end of one row via the control line 3r, it moves to the next line and writes the pixel data to the counter 40 via the control lines 3s and 3q.
, the second address counter 39 is reset.

Writing of the counting result output from the adder 35 to the second memory or reading it to the outside is controlled by the control unit 33 via the control line 3p.

The input control of the first and second data registers 36.37 is also controlled by the control 1all line 31.3k by the control iaf section 33.
It is done through.

When writing of all pixel data to the first memory is completed, the contents of the second memory 38 holding the count results are read out to the external microprocessor via the data line:]u.

According to this embodiment, the first memory (image memory) 34
While expanding and storing parallel pixel data into bits,
Since the number of black pixels in each row is counted at the same time, a significant improvement in processing speed can be achieved.

(Effects of the Invention) The present invention provides a character recognition device and an image processing Pi device.
Image data captured in parallel from an external device such as a scanner can be efficiently bit-expanded and stored in the image memory, eliminating the need for bit expansion using bit manipulation instructions, simplifying microprocessor software and processing The speed will be improved.

Furthermore, the present invention can be configured so that the number of black pixels on the same line can be counted in parallel when the image memory is opened and written to the image memory. Compared to systems that count the number of pixels again after they have been inserted, it is possible to achieve a significant improvement in processing speed.

[Brief explanation of drawings]

Fig. 1 is a block diagram of one embodiment of the present invention, Fig. 2 is a block diagram of another embodiment of the invention, Fig. 3 is a block diagram of yet another embodiment, and Fig. 4 is a detailed diagram of the present invention. In these diagrams, (a) shows a memory logical space in which the addresses of the initial setting area are continuous, (b) shows an example of the structure of input data from the scanner, and (C) shows the image memory. This shows the image inside. 21.31...Shift register, 22.32...Address counter (first address counter), 23+33
...Control unit, 24.34...Memory (first memory)
, 25.35...Adder, 26...Register, 36
...first data register, 37...second data register, 38...second memory, 39...second address counter, 40...counter. Figure 1a Figure 2a

Claims (4)

[Claims] (1) A means of loading image data consisting of multiple bits from the outside in parallel and sequentially shifting it and giving it as memory write data one bit at a time, and a means of incrementing the memory address information given from the outside in synchronization with the shift operation. and a control unit that controls memory writing, incrementing address information, and shift operations based on instructions from the outside, and notifies the outside when writing of predetermined image data is completed, and converts the image data in dot units. An image memory control method characterized by efficiently expanding and writing to an addressable image memory. (2) A means for loading image data consisting of multiple bits from the outside in parallel and giving it as memory write data one bit at a time while sequentially shifting it, and a means for incrementing the memory address information given from the outside in synchronization with the shift operation. and a control means for controlling memory writing, incrementing and shifting of address information according to instructions from the outside, and notifying the outside when writing of predetermined image data has been completed, 1. An image memory control method, comprising means for receiving an output signal of the providing means, and counting and holding the number of black pixels included in the output signal. (3) The counting and holding means includes an adding means;
and a means for holding the addition result, and the addition means is
Claim (2) characterized in that the output signal of the means for providing one bit at a time as memory write data and the output signal of the means for holding the addition result are added. Image memory control method. (4) The counting and holding means includes a memory means for storing the count result, a means for holding and incrementing the address of the memory means, and a register means for holding data read from and written to the memory means. means for setting the number of dots in the horizontal direction and decrementing the number in synchronization with the shift operation; and addition means for adding the output signal of the register means and the output signal of the means for providing one bit at a time as memory write data. 2. The image memory control system according to claim 2, wherein the image data is counted while being developed, and the result is stored in the memory means.