JPS6334795A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To reduce the size of a body and a peripheral device by supplying information relating to the addresses of a storage element which is time-divided into two components or not time-divided and an indication relating to the operation mode of the storage device with time division through address lines. CONSTITUTION:Operation mode information, data input and data output are sent to the address buses 2a with time division from address information A0-AN-1. Namely, the address bus lines for the A0-AN-1 outputs operation mode information, line address information and row address information successively and these information components are triggered at the trailing edge of a CLK 1, the trailing edge of a CLK 2 and the leading edge of the CLK 1 respectively and then applied to the storage device. Thereby, the storage device can execute different operations of 2N based on the mode information. Consequently, the number of input pins of the storage device can be reduced to reduce the size of the storage device and the peripheral device can be simplified and reduced its size.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and particularly relates to an improvement in the time division method thereof.

[Conventional technology]

FIG. 6 shows an example of a conventional semiconductor memory device, in which 64 shows an example of a dynamic RAM input signal. In the figure, 1b is a semiconductor memory device.
M, 2b are address bus lines 64 connected to the dynamic RAM 1b, and are composed of eight lines, Ao''-At. 3b is a clock signal, RAS, CAS
, R/W.

FIG. 7 shows the operating timing of the device shown in FIG. 6, and FIG. 8 summarizes the operating modes of the device shown in FIG.

Further, FIG. 9 shows another example of a conventional semiconductor memory device.
This shows an example of a 4KX4 video RAM input signal.
In the figure, lc is a 64KX4 video RAM which is a semiconductor storage device, 2c is an address bus line connected to a 64KX4 video RAM lc, and A0 to A? It consists of eight books. 3c is a clock signal, which is composed of four trees: RAS, CAS, DTloE, and WB/WE.

FIG. 10 shows the operation timing of the device shown in FIG.
FIG. 1 summarizes the operating modes of the device shown in FIG.

Next, the operation of the apparatus shown in FIG. 6 will be explained based on FIG. 7. In addition, 64 shown in Fig. 6 is a dynamic RA.
M includes 65536-2'' memory elements, and is a device that can read and rewrite information in any memory element among them.

In FIG. 7, first, the upper 8 bits of address information fg
(row address) is output to the address bus line 2b and taken into the storage device 1b at time t0 by the fall of the RAS signal in the clock signal 3b. Next, the address information (column address) of the lower 8 bits is outputted to the address bus line 2b, and taken into the memory t9 device fib at the fall of the CAS signal at time t1. In this way, address information is output to the address bus line 2b in a time-division manner. Further, from time t1 to time t2 when the CAS signal rises, the operation mode can be designated as read if the R/W signal is in the H4gh state, and write if it is in the Low state. This situation is summarized in FIG. In addition, in reality, R/
Although it is not necessary to fix the state of the W signal, this is not directly related to the present invention, so the explanation is simplified.

Next, the operation of the apparatus shown in FIG. 9 will be explained using FIG. 10. The video RAM shown in Figure 9 is equipped with a random access memory (hereinafter abbreviated as RAM) and a memory that can be accessed in series and sequentially (serial access memory: abbreviated as SAM), and can be used for normal reading and writing. In addition to its functions, this device has a write-per-bit function that masks write data, and enables information transfer between a group of storage elements in RAM and SAM.

In FIG. 10, the row address is taken into the memory device "flc" by the fall of the RAS signal at time t3, and the column address is taken into the memory device "flc" by the fall of the Vτ signal at time t4.
By setting both to Low, it is possible to set a variety of operating modes, such as specifying information transfer from SAM to RAM, and this situation is summarized in FIG.

Note that time t is the rise time of CAS, but in reality, DT10E is applied between time t4 and time t.

Although it is not necessary to fix the WB/WE signal, the explanation is simplified since it does not directly relate to the present invention.

[Problem that the invention seeks to solve]

Since conventional semiconductor memory devices are configured as described above, a large number of clock signals are required to implement various operation modes, and the number of input pins of the memory device increases.
There are problems in that the device becomes larger, or the clock signal requires complicated timing control, making the peripheral equipment complex and larger.

This invention was made to solve the above problems, and it is possible to specify many types of modes with a small number of clock signals, and does not require complicated timing control.
The object of the present invention is to obtain a semiconductor memory device whose main body and peripheral devices can both be miniaturized.

[Means for solving problems]

A semiconductor memory device according to the present invention inputs operation mode information and data of the memory device in a time-sharing manner with address information to an address bus connected to the memory device.

It is designed to carry data output.

[Effect]

In the semiconductor memory device of the present invention, since the address bus is configured to carry the operating mode information, data input, and data output in a time-sharing manner with the address information, there is no need to determine the operating mode using complicated timing signals, and the device can be simplified.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, 1a is a storage device, 2a is an address bus line composed of N pieces, and 3a is a line for receiving a timing clock signal. In the figure, an example is shown in which there are two CL devices and CLK2.

FIG. 2 is a diagram showing the operation timing of the apparatus of FIG. 1.

Next, the operation will be explained. In Figure 2, A0 to A
The N-1 address bus line is operational mode information.

Row address information Two column address information are output in sequence, and the operating mode information is triggered by the falling edge of the CL device, the row address information tK is triggered by the falling edge of CLK2, and the column address information is triggered by the rising edge of CLKI. given to storage. The storage device can perform 2N different operations depending on the mode information.

Note that in the above embodiment, the operation mode and row address.

It is assumed that the column addresses are input in order, but it goes without saying that this order may be changed, the time division method of the operation mode information and address information may be changed, and the triggering method by the CL device and CLK2 may be changed. .

FIG. 3 shows, as a modified example, a case in which one type of address information and two types of mode information are given, and each is triggered by the falling edge of CLKI, the rising edge of CLKI, and the rising edge of CLK2. In this example, 22N modes can be set.

Furthermore, more diverse divisions are possible by combining the rising and falling timings of CLKI and CLK2, and by using three or more types of clock signals. FIG. 4(a) illustrates a case where the timing combination is changed, and FIG. 4(b) illustrates a case where three types of clocks are used.

It is also possible to time-divide data input and data output. An example of this is shown in FIG.

〔Effect of the invention〕

As described above, according to the present invention, the operation mode information of a semiconductor storage device is given to the address bus connected to the storage device in a time-sharing manner with the address information, thereby reducing the number of input bins of the storage device. Effects such as the ability to reduce the size of the storage device, the need for no complicated timing signals, and the ability to simplify and reduce the size of peripheral devices can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a semiconductor memory device according to an embodiment of the invention, FIG. 2 is an explanatory diagram showing the operation timing of the device in FIG. 1, and FIGS. 3 to 5 are other embodiments of the invention. 6 is a block diagram showing a conventional semiconductor memory device, FIG. 7 is a diagram showing the operation timing of the device in FIG. 6, and FIG. 8 is an operation mode of the device in FIG. 6. 9 is a block diagram showing another conventional semi-quadramid memory device, FIG. 10 is a diagram showing the operation timing of the device in FIG. 9, and FIG. 11 is a block diagram showing the device in FIG. 9. FIG. 2 is a diagram summarizing the operation modes of FIG. 1a is a storage device, 2a is an address bus line, and 3a is a timing clock signal.

Claims (6)

[Claims] (1) In a semiconductor memory device in which multiple address lines and one or more timing signal lines are connected, information regarding addresses of storage elements that are or are not time-divided into two or more divisions, and A semiconductor memory device characterized in that an instruction regarding an operation mode of the divided or undivided memory device is time-divided and given from the address line. (2) A patent claim characterized in that the timing signal of the timing signal line determines the timing at which the storage device takes in an instruction or data input regarding the operation mode of the storage device, and the timing at which the storage device outputs data. The semiconductor memory device according to item 1. (3) In a semiconductor memory device in which a plurality of address lines and one or more timing signal lines are connected, information regarding addresses of memory elements that are or are not time-divided into two or more divisions, and information from the memory device A semiconductor memory device characterized in that data output and/or data input to the memory device are time-divisionally provided from the address lines. (4) A timing signal on the timing signal line determines the timing at which the storage device takes in an instruction or data input regarding the operation mode of the storage device, and the timing at which the storage device outputs data. 3. The semiconductor memory device according to item 3. (5) In a semiconductor memory device in which multiple address lines and one or more timing signal lines are connected, information regarding the address of a memory element that is or is not time-divided into two or more divisions, and information about the address of a storage element that is divided into two or more divisions. An instruction regarding an operation mode of the storage device that has been or has not been activated, and data output from the storage device and/or data input to the storage device are time-divided and given from the address line. semiconductor storage device. (6) The timing signal of the timing signal line determines the timing at which the storage device takes in instructions and data input regarding the operation mode of the storage device, and the timing at which the storage device outputs data. The semiconductor memory device according to item 5.