JPS58130487A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To decrease the number of terminals, and to make an integrated circuit having many bits small in size, by generating M-kinds of strobe signals from L-kinds of control signals being fewer than M-kinds, when generating M- kinds of strobe signals by dividing a signal of plural N-bits into M-groups. CONSTITUTION:A titled circuit is constituted to receive signals, for instance, by dividing address signals A0-A8 of 9 bits into 3 groups, and dividing them into 3 times at every time decided by 3 kinds of strobe signals Sx, Sy and Sz. Among outputs of a controlling circuit 4 generating strobe signals Sx, Sy and Sz from strobe control signals, one as to the Sx is delayed by a delaying circuit 5', by which the Sy and Sz are obtained. As a result, among necessary strobe control signal only xAS remains strobe control signal applied terminals of a small number are enough. In this way, the integrated circuit is made small in size by a small number of terminals.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit that receives a plurality of N-bit signals and performs some predetermined operation. Relating to a semiconductor integrated circuit having a configuration for receiving the N-bit signal divided into M times at each time determined by the signal, and requiring fewer than M terminals to create the M types of strobe signals. It is something.

A conventional semiconductor integrated circuit of this type has been constructed as shown in FIG. 1, for example. Here, the multiple N hint signals are 9 address signals Ao-As, and these 9-bit address signals are divided into 3 groups and sent at each time determined by 3 types of strobe signals Sx, 'Sy, and Sz. The explanation will be based on the assumption that the information will be received in three installments. 1 is a buffer circuit that generates internal address signals α0 to (1B+no-c18) from the address signal; 2 is a switch circuit that uses a strobe signal to decide whether or not to connect the six internal address signals to the decoding circuit 3; 4 is a strobe control circuit Signal sword <S,
YAE! , strobe signals SX, sy, from ZAS,
A control circuit for creating SZ, 5 a delay circuit for delaying a signal, p1 to p3 are address signal application terminals, and p4 to p6 are strobe control signal application terminals. As for the operation of this semiconductor integrated circuit:
Let X be I II, and αO+”O・
αII ”II (Z2. (Give Z2 to the decoding circuit and generate a 3-bit address signal Ao+A4.
Receive A2. Similar operation with YAS and A3゜A 4 +
A5 and sword [and A6. Perform between A71A8.

Figure 2 shows the relationship between the signal waveform and time T during this time. be exposed.

As mentioned above, conventional semiconductor integrated circuits are configured to require a strobe control signal corresponding to each strobe signal and a strobe control signal application terminal. This has the disadvantage that the semiconductor integrated circuit cannot be miniaturized because the number of terminals must be increased, and furthermore, when the number of terminals is limited, it is impossible to construct a structure that can receive address signals with multiple hints.

In order to solve these drawbacks, the present invention generates a large number of strobe signals from strobe control signals applied to a small number of terminals, and will be described in detail below with reference to the drawings.

FIG. 3 shows a first embodiment of the present invention, in which the output of the control circuit 4 is delayed from Sx by a delay circuit 5' to obtain Sy.

Obtained S2. The only strobe control signal required is XAS, and the number of strobe control signal application terminals is reduced from three to one as compared to the example of FIG.

FIG. 4 shows the relationship between signals and time in the embodiment of FIG. 3, where the first address signal is received at T=T, and T=
The second address signal reception is performed at T2, and the third address signal reception is performed at T-T3.

FIG. 5 shows a second embodiment of the present invention, in which one strobe control signal YAS is used to connect the control circuit 4 and the inverter.
Three strobe signals 3X by combination of AND circuits
+Sy+sz is created. The relationship between signals and time in the example of FIG. 5 is shown in FIG. Three address signal receptions are T = T,.

T2. Each is performed at T3. In this second embodiment, the configuration is such that 5XISZ remains n I I+ for a longer time than in the conventional example or the first example, so the first address signal reception can be performed at a time before T. Yes, and the third address signal reception is possible after T2 and before T4.

Next is the dynamic type M, in which the semiconductor integrated circuit is housed in a 16-pin dual/two-in-one package (hereinafter referred to as DIP).
The case where it is an OS memory will be described. In this case, there are a maximum of nine terminals used for applying address signals, and two terminals used for applying strobe control signals, and the strobe signals include a row address strobe control signal (hereinafter referred to as "official") corresponding to XAS, and Usually, two column address strobe control signals (described below) corresponding to YAS are used, and a maximum 18-bit address signal is received twice by RAS and CAS. The maximum storage capacity is therefore 256 bits.

As a third embodiment of the present invention, when the present invention is applied to the MOS memory stored in the 16-bin DIP, the third embodiment is already applied.
Either the catch or the penalty can be omitted in a manner similar to that described for Figure 5. Therefore, one of the strobe control signal application terminals can be used to apply address signals, and a configuration that can receive address signals of up to 20 bits can be realized, and 1M bits of memory corresponding to 2.
A 16-pin DIP'K can accommodate a large capacity MOS memory. Or use one of the strobe control signal application terminals as a new function bin (256)
MOS memory can be realized. The function bin can be used in a variety of ways, such as as a refresh control signal application terminal, as an input/output register control signal application terminal, and so on.

In the above embodiments of the present invention, a configuration has been described in which all strobe signals are generated using the applied strobe control signal. It is also possible to adopt a configuration in which the detection occurs frequently by detecting the completion of the operation.

As explained above, since the configuration reduces the number of required terminals, it has the advantage of being able to downsize the semiconductor integrated circuit that receives signals from a large number of hits, or that new functional bins can be obtained over the lifespan by adding more terminals.

[Brief explanation of the drawing]

6- FIG. 1 is a configuration example of a conventional semiconductor integrated circuit, FIG. 2 is a diagram showing the relationship between signal waveforms and time of a conventional semiconductor integrated circuit, FIG. 3 is a diagram showing the first embodiment of the present invention, and FIG. The figure shows the relationship between the signal waveform and time in the first embodiment of the invention, FIG. 5 shows the relationship between the signal waveform and time in the second embodiment of the invention, and FIG. 6 shows the signal waveform in the second embodiment of the invention. FIG. 3 is a diagram showing a time relationship. 1...Buffer circuit, 2...
・・・・・・Switch circuit, 3 ・・・・・・Decode circuit, 4 ・・・・・・Control circuit, 5.5'
......Delay circuit, AO-A8...Song address signal, SX, sy, Sz...St o y' times signal XAS, YAS, ZAS...
...Strobe control signal, p1 to p6°°°°°3
゛°°Terminal XaO”-a8, “O”’-”8°°°
°°…Internal address signal. 71 Figure 4 Figure 5 Figure 6

Claims (1)

[Claims] In a semiconductor integrated circuit configured to divide a plurality of N-bit signals into M groups and receive the N-bit signals M times at each time determined by M types of strobe signals,
A semiconductor integrated circuit characterized in that L terminals are provided to which L types of control signals, which are fewer than M types, are provided, and the M types of strobe signals are created using the corresponding types of control signals. . (N, M, L are integers)