GB2217066A

GB2217066A - Data processing apparatus with page mode memory

Info

Publication number: GB2217066A
Application number: GB8903546A
Authority: GB
Inventors: Bernard William Gill
Original assignee: Fujitsu Services Ltd
Current assignee: Fujitsu Services Ltd
Priority date: 1988-04-05
Filing date: 1989-02-16
Publication date: 1989-10-18
Anticipated expiration: 2009-02-16
Also published as: GB8903546D0; GB2217066B; GB8807849D0

Abstract

Data processing apparatus includes a processor 14 and a memory 10 operable in page mode. Each row address from the processor is compared 15, with the preceding row address, held in a register 11. If the row addresses are unequal, a three-beat memory cycle is performed, 12, including a row address strobe, a column address strobe, and one wait state for the processor. If, on the other hand, the row addresses are equal, a two-beat memory cycle is performed, including a column address strobe only. Thus, where consecutive addresses relate to data items in the same row, the memory is automatically accessed in page mode, giving faster access speed. <IMAGE>

Description

DATA PROCESSING APPARATUS WITH PAGE MODE MEMORY.

This invention relates to data processing apparatus with a memory operable in a page mode.

In one known form of semiconductor memory, data items are arranged in rows and columns, and are accessed by means of a row address and column address. These addresses are multiplexed on to a single set of chip terminals, and are loaded successively into the chip by means of control signals referred to as the row address strobe (RAS) and column address strobe (CAS). The normal memory access cycle consists of one RAS followed by one CAS.

It is known for such a memory to be arranged to operate in page mode. In this mode, a row address is first strobed into the chip by RAS, and this is followed by a succession of column addresses, strobed into the chip by a sequence of CAS signals. Since only one RAS is required for several accesses, the overall access time is reduced. Thus, the page mode allows a plurality of data items in the same row to be accessed rapidly.

The page mode has been found useful in situations where it is known in advance that several data items from the same row will be required. In particular, it is useful in the case of a video memory for storing data defining a raster-scanned image, where it is known in advance that the data will be read out sequentially in step with the scanning of the raster.

However, in many applications, data is accessed from the memory in a more random manner, and in this case it has hitherto not been considered possible to take advantage of the page mode facility. One object of the invention is to overcome this limitation.

Summary of the invention.

According to the invention there is provided a data processing apparatus comprising (a) a memory for holding data item s in rows and columns, the memory having a normal mode in which a data item can be accessed by a row address followed by a column address, and having a page mode in which a plurality of data items in the same row can be accessed by means of a row address followed by a plurality of column addresses, (b) a data processor for generating a sequence of addresses for the memory, each address comprising a row address and a column address, and (c) means for comparing each row address with the preceding row address and, if they are unequal, causing the memory to operate in the normal mode and applying a wait signal to the processor to cause it to temporarily enter a wait state and, if they are equal, causing the memory to operate in the page mode without applying a wait signal to the processor.

As will be shown below in more detail, if the processor generates addresses relating to two or more data items in the same row of the memory, the memory operates in page mode, allowing rapid access to the data. If, on the other hand, the processor generates addresses in a more random sequence, such that s ] ccesive data items are in different rows, then the memory reverts to the normal mode, and the processor is forced into a wait state in each memory access cycle, to allow sufficient time for both the row and column to be strobed into the memory.

Brief description of the drawings.

One data processing apparatus in accordance with the invention will now be described by way of example with reference to the accompanying drawings of which: Figure 1 is a block diagram of the apparatus.

Figure 2 is a timing diagram illustrating the operation of the apparatus.

Description of an embodiment of the invention.

Referring to Figure 1, the apparatus includes a memory 10 which receives an address from an address register 11. The address comprises a row address portion and a column address portion. The memory 10 is constructed, in known manner, from dynamic random-access memory (DRAM) chips. Each of these chips has a set of address input terminals, on to which the row address and column address are multiplexed.

The operation of the memory 10 is controlled by a row address strobe signal RAS and a column address strobe signal CAS from a sequencer circuit 12. At the falling edge of RAS, the row address is strobed into the DRAM chips, so as to select one row of data. Then, at the falling edge of CAS the column address is strobed into the DRAM chips, so as to select one data item from the previously selected row. The selected data item can then he writ ten or reas in the convent i on- manner, , way of a data input/output 13.

The memory 10 is operable in normal mode or in page mode.

In normal mode, a data item is accessed by applying a RAS to strobe the row address into the memory, followed by a single CAS to strobe the column address.

In page mode, several data items in the same row can be accessed by first applying a RAS to strobe in the row address, followed by a sequence of CAS signals, to strobe in a sequence of column addresses.

The apparatus also includes a conventional microprocessor 14. The microprocessor has a data input/output, connected to the data input/output 13 of the memory, and has an address output, connected to the address register 11. The address from the microprocessor is latched into the register 11 at the rising edge of CAS.

The apparatus also includes a comparator circuit 15, which compares the row address from the microprocessor 14 with the row address stored in the register 11. The comparator circuit produces an output signal NEQ which goes high if the two row addresses are unequal. NEQ is applied as a control signal to the sequencer 12.

As mentioned above, the sequencer 12 produces the signals RAS and CAS which control the memory access cycles. The sequencer is arranged to produce a memory access cycle of either 2 or 3 beats of a clock signal CLK, according to the value of NEQ at the start of the cycle.

Referring to Figure 2, if NEQ is high at the start of the store access cycle, then the sequencer produces a three-beat cycle (CYCYLE 1) as follows. Both RAS and CAS are initially raised to the high logic level. RAS is dropped at the end of the first clock beat, so as to strobe the row address. CAS is dropped at the end of the second clock beat, so as to strobe the column address. The data is then available for access at the end of the third clock beat. During this three-beat cycle, the sequencer also produces a WAIT signal for the microprocessor. This causes the microprocessor to execute a WAIT state for one clock beat, so as to allow time for both the row and column addresses to be strobed into the memory.

If, on the other hand, NEQ is low at the start of the store access cycle, then the sequencer produces a two-beat cycle (CYCLE 2) as follows. CAS is initially raised to the high logic level and is then dropped at the end of the first clock beat. RAS remains low throughout the cycle. No WAIT signal is produced.

It should be noted from Figure 2 that the addresses from the microprocessor are pipelined, such that the next address is available before the end of the access cycle. If no WAIT is present (as in CYCLE 2) then the next address is produced during the second clock beat of the cycle. However, when a WAIT is produced (as in CYCLE 1) then the next address is delayed by one clock beat, and is produced during the third clock beat. Figure 2 also shows how the address is latched into the address register at the rising edge of CAS, and shows the signal NEQ produced by comparing the current address with the latched address.

The operation of the system is as follows. At the start of each cycle, the current row address from the microprocessor is compared with the preceding row address, which is held in the address register. If these row addresses are unequal (i.e. if the second address relates to a different row) then a three-beat cycle is performed. In this case, therefore, both the row address and the column address are strobed into the memory, so as to access the required data item, and the microprocessor is forced to execute a WAIT state so as to allow time for the memory access.

If, on the other hand, the row addresses are equal (i.e. if the current address relates to a data item in the same row as the preceding address) then a two-beat cycle is performed. In this case, therefore, the row address is not strobed into the memory; only the column address is strobed.

In summary, it can be seen that when the processor produces addresses relating to data items in different rows, the memory operates in normal mode, with each memory cycle occupying three clock beats, if on the other hand, two or more addresses are produced relating to data items in the same row, then the memory operates in page mode, with each memory cycle after the first occupying just two clock beats. Thus, the system automatically takes advantage of the page mode capability whenever this is possible, so as to increase the access speed.

Claims

1. A data processing apparatus comprising (a) a memory for holding data item s in rows and columns, the memory having a normal mode in which a data item can be accessed by a row address followed by a column address, and having a page mode in which a plurality of data items in the same row can be accessed by means of a row address followed by a plurality of column addresses, (b) a data processor for generating a sequence of addresses for the memory, each address comprising a row address and a column address, and (c) means for comparing each row address with the preceding row address and, if they are unequal, causing the memory to operate in the normal mode and applying a wait signal to the processor to cause it to temporarily enter a wait state and, if they are equal, causing the memory to operate in the page mode without applying a wait signal to the processor.

2. Apparatus according to Claim 1 including a sequencer circuit for producing a column address strobe signal and a row address strobe signal for the memory.

3. Apparatus according to Claim 2 wherein the sequencer circuit is operable when the compared row addresses are unequal to produce a first memory access cycle comprising a row address strobe signal followed by a column address strobe signal, and is operable when the compared row addresses are equal to produce a second memory access cycle comprising a column address strobe signal on3v.

4. Apparatus according to Claim 3 wherein said first memory access cycle occupies three clock beats and said second memory access cycle occupies the two clock beats.

5. Appartus according to Claim 3 or 4 wherein said wait signal is produced during said first memory access cycle but not during said second memory access cycle.

6. Apparatus according to any one of Claims 2-5 including an address register for storing each row address in turn from the processor, and a comparator for comparing the row address held in the register with the current row address from the processor, to produce a control signal for said sequencer circuit.

7. Apparatus according to Claim 6 wherein the column address strobe signal controls loading of the address register.

8. Apparatus according to any preceding claim wherein the processor is arranged to produce a next address before completion of the current memory access cycle.

9. Data processing apparatus substantially as hereinbefore described with reference to the accompanying drawings.