GB2217066B - Data processing apparatus with page mode memory - Google Patents

Data processing apparatus with page mode memory

Info

Publication number
GB2217066B
GB2217066B GB8903546A GB8903546A GB2217066B GB 2217066 B GB2217066 B GB 2217066B GB 8903546 A GB8903546 A GB 8903546A GB 8903546 A GB8903546 A GB 8903546A GB 2217066 B GB2217066 B GB 2217066B
Authority
GB
Grant status
Grant
Patent type
Prior art keywords
data processing
processing apparatus
page mode
mode memory
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
GB8903546A
Other versions
GB2217066A (en )
GB8903546D0 (en )
Inventor
Bernard William Gill
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Services Ltd
Original Assignee
Fujitsu Services Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Grant date

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/0215Addressing or allocation; Relocation with look ahead addressing means
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39Control of the bit-mapped memory
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1018Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
    • G11C7/1021Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
GB8903546A 1988-04-05 1989-02-16 Data processing apparatus with page mode memory Expired - Fee Related GB2217066B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB8807849A GB8807849D0 (en) 1988-04-05 1988-04-05 Data processing apparatus with page mode memory

Publications (3)

Publication Number Publication Date
GB8903546D0 GB8903546D0 (en) 1989-04-05
GB2217066A true GB2217066A (en) 1989-10-18
GB2217066B true GB2217066B (en) 1992-01-08

Family

ID=10634527

Family Applications (2)

Application Number Title Priority Date Filing Date
GB8807849A Pending GB8807849D0 (en) 1988-04-05 1988-04-05 Data processing apparatus with page mode memory
GB8903546A Expired - Fee Related GB2217066B (en) 1988-04-05 1989-02-16 Data processing apparatus with page mode memory

Family Applications Before (1)

Application Number Title Priority Date Filing Date
GB8807849A Pending GB8807849D0 (en) 1988-04-05 1988-04-05 Data processing apparatus with page mode memory

Country Status (1)

Country Link
GB (2) GB8807849D0 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105190757A (en) * 2013-03-15 2015-12-23 高通股份有限公司 System and method to dynamically determine a timing parameter of a memory device

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2028085A1 (en) * 1989-11-03 1991-05-04 Dale J. Mayer Paged memory controller
GB2242294B (en) * 1990-03-19 1993-12-22 Apple Computer Memory architecture using page mode writes and single level write buffering
JPH0682339B2 (en) * 1990-08-31 1994-10-19 インターナショナル・ビジネス・マシーンズ・コーポレイション Memory access system and method
US5694143A (en) 1994-06-02 1997-12-02 Accelerix Limited Single chip frame buffer and graphics accelerator
JPH10502181A (en) * 1994-06-20 1998-02-24 ネオマジック・コーポレイション Memory interface without graphics controller integrated circuit
US6449193B1 (en) * 2000-12-28 2002-09-10 Texas Instruments Incorporated Burst access memory system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105190757A (en) * 2013-03-15 2015-12-23 高通股份有限公司 System and method to dynamically determine a timing parameter of a memory device
CN105190757B (en) * 2013-03-15 2017-08-22 高通股份有限公司 A timing system and method for dynamically determining the parameters of the memory device

Also Published As

Publication number Publication date Type
GB8807849D0 (en) 1988-05-05 grant
GB2217066A (en) 1989-10-18 application
GB8903546D0 (en) 1989-04-05 grant

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Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee

Effective date: 20050216