GB2246650A - Digital memory access system - Google Patents

Abstract

An addressing system for a multiport interleaved memory array having a plurality of memory banks 1, 2, 3, 4 comprises an address pipeline 20 with twice as many stages 22 as there are banks. The address pipeline recirculates through an address incrementer 24. After each circulation the row address is incremented and after the row address reaches its maximum value the column address is incremented. Addresses for the different access ports can recirculate behind one another in the pipeline (Figure 3). <IMAGE>

Description

DIGITAL MEMORY ACCESS SYSTEM Background of the Invention This invention relates to a system for accessing a multiport interleaved memory array.

In video signal processing it is known to split a framestore into for example four sections or banks and to load successive pixels of a video signal cyclically into the banks. More generally, a memory can be split into a plurality of banks of memory elements and the stored data written cyclically into the banks such that the data is written and read in an interleaved fashion. The memory banks may for example be DRAMs (dynamic random access memories). Such an arrangement allows higher data rates to be achieved than can be handled by one single DRAM. However existing systems require many latches, counters and multiplexers to store the different addresses and supply them to the banks, particularly if the memory array has a plurality of access ports.Presettable counters store the addresses from the different access ports, and multiplexers route the column and row addresses to each bank of memory.

United States Patent 4,581,721 describes a memory array suitable for storing data for a video image display using a 64K RAM broken up into four memory circuits. The circuits are addressed in a repeating cycle including addressing two or more sites having the same row address but different column addresses. The first row address component is stored until all columns required on the row have been accessed.

Summary of the Invention The invention in its various aspects in defined in the independent claims appended hereto, to which reference should now be made, and advantageous features of the invention are defined in the appendent claims.

The use of an address pipeline in accordance with the invention greatly simplifies the construction and operation of the memory array.

Brief Descrlption of the Drawings The invention will be described in more detail by way of example with reference to the accompanying drawings, in which: Figure 1 is a block diagram of a bank of DRAM memory with its addressing system embodying the invention; Figure 2 shows the format of an address received at the address ports; Figure 3 (which extends onto two sheets) is a timing diagram showing the addresses circulating through the pipeline of Figure 1; Figure 4 is a block diagram illustrating the operation of the address incrementer 24 of Figure 1; and Figure 5 is a schematic diagram illustrating the data flow through the memory array, when there are two data access ports to the array.

Detailed Descrintion of the Preferred Embodiment Figure 1 shows a memory 10 comprising four DRAM banks of memory elements 1, 2, 3 and 4. Each memory bank has a data input/output 12, and row/column address input 14, a row address strobe (RAS) input 16, and a column address strobe (CAS) input 18.

The memory bank only responds to data at the row/column address input when one or other of the RAS and CAS are high. When RAS is high the data at the row/column address input is taken to be a row address, and when CAS is high the data at the row/column address input is taken to be a column address. To address a particular memory location the RAS and CAS are applied sequentially.

The memory banks 1, 2, 3, 4 are used in an interleaved fashion, that is, consecutive data elements are written into the memory banks cyclically, with the first data element going into bank 1, the second into bank 2, the third into bank 3, the fourth into bank 4, the fifth back into bank 1 and so on. More generally, the (4n + i)th data element is applied to the i th data bank.

The addresses are suppled by an address pipeline 20 comprising a series of eight latches 22 connected in cascade and looped together with the output of the last latch being connected through an address incrementer 24 to the input of the first latch.

The address incrementer also receives the output of the first latch.

A start address can be introduced into the pipeline from a host processor by a latch 26. Clock signals ClkAddr are applied to each of the latches 22 and a clock signal IncAddr is applied to the address incrementer 24. A load timing signal is applied to the latch 26. As is seen, there are eight stages in the pipeline represented by the eight latches 22 so as to accommodate the row address and column address for each of the four memory banks.

The start addresses received via the latch 26 are in the form shown in Figure 2. Each address comprises an n-bit column address, an m-bit row address, and a 2-bit bank select portion.

The bank select port of the address is only used to determine the first bank to access, and thus controls the strobe signals applied to the memory banks.

The row and column addresses are applied successively through the pipeline. Thus each bank receives the same row and column address until those addresses have been applied to all four banks. After leaving the last latch 22 they are applied to the address incrementer 24, in which the row address is incremented by one. The next data element is then read from each bank. This continues as necessary until either enough data has been accessed, or the row address has reached its maximum value. On the next circulation through the address incrementex, the row address is then reset to zero, and the column address incremented by one.

Thereafter the data is read from successive rows of the next column.

Thus in summary, as the address is incremented, the next access is to the next bank along and so on until bank 4 is reached.

Now the row part of the address is incremented, with the column address remaining unchanged. The banks are now cycled with the new address. The address generator increments the row address after cycling through all the banks. The column address is incremented after the row address rolls over.

Figure 3 is a timing diagram showing the flow of the address through the pipeline during a sequence of accesses. Starting addresses for the two access ports are initially written through the host access port into the pipeline. The position in the pipeline which an address occupies depends on the starting banks of the two access ports. The addresses are also split into its row and column components when they are loaded, with the column address following the row address in the pipeline. If the ports both access the same bank, one is made to wait and its address placed behind the other in the pipeline. Apart from that, they may begin to access the different banks simultaneously. The timing diagram shows port one accessing bank 1 and port two accessing bank 4 initially.The access cycles begin with RAS being generated for bank one and bank four followed by ClkAddr toggling, which shifts the column addresses to their respective banks. CAS is then generated for bank 1 and bank 4 to latch the column addresses into their respective banks of DRAM. Port two will now access bank 1 while port one will access bank 2. The row address for port two is incremented while the address for port one remains unchanged.

Another access cycle is now performed. Access cycles continue until halted by the host.

The address incrementer 24 of Figure 1 may be constructed of two 4-bit adders 30, 32 as shown in Figure 4. For example, the address 30, 32 may each be type No. 74F283 as indicated. Figure 5 shows the data flow through the array, as opposed to the addressing shown in more detail in Figure 1. Input latches 34, 36 enable the two access ports 38, 40 to share the same data input bus 11 to the DRAM banks 1-4, in time-division multiplex. Two output latches 42, 44 likewise enable two output data ports 46, 48 to share the same output data bus 12. A read and write operation may occur simultameously on separate DRAM banks through the two access ports 38, 40. However, if both ports simultaneously request a read or write, the accesses from the ports need to be offset in time, as will be well understood by those skilled in the art.

Thus it is seen that a multiport interleaved memory can be used in a video framestore to allow simultaneous access to different banks of the dynamic memory (DRAM) array by different digital video data ports. Each frame of digital video data is stored as consecutive words of data. The banks of DRAM are arranged so that consecutive addresses select the different banks. Therefore when a frame of digital video is accessed by a port, the banks of DRAM are accessed in turn. The different addresses are generated for each bank of DRAM from the different ports, given the start addresses, using relatively simple hardware.

Claims (9)

1. An addressing system for an interleaved memory array having a plurality of memory banks, each bank having its own data port and address port, and comprising a recirculatory address pipeline having twice as many stages as memory banks, means for applying a start row address and a start column address to the pipeline, and address incrementing means in the address pipeline for incrementing the row address after each cycle and for incrementing the column address when the row address has reached a maximum value.

2. An addressing system according to claim 1, having a plurality of access ports and in which addresses for the different access ports recirculate successively in the address pipeline.

3. An addressing system according to claim 1 or 2, in which the incrementation proceeds one address at a time so that adjacent addresses are addressed in sequence.

4. An interleaved memory array, comprising a plurality of memory banks, each bank having its own data port and address port, a recirculatory address pipeline coupled to the address port of each of the memory banks and having as many stages as memory banks, means for applying a start address to the pipeline, and address incrementing means in the pipeline, the address incrementing means incrementally altering the address after each cycle of the recirculatory address pipeline.

5. An interleaved memory array, comprising a plurality of memory banks, each bank having its own data port and address port, a recirculatory address pipeline coupled to the address port of each of the memory banks and having as many stages as memory banks, means for applying to the pipeline a start row address and a start column address, and address incrementing means in the pipeline, the address incrementing means incrementing the row address after each cycle of the recirculatory address pipeline.

6. A memory array according to claim 5, in which the address incrementing means increments the column address when the row address has reached a maximum value.

7. A memory array according to claim 5 or 6, having a plurality of access ports and in which addresses for the different access ports recirculate successively in the address pipeline.

8. A memory array according to claim 5, 6 or 7, in which the incrementation proceeds one address at a time so that adjacent addresses are addressed in sequence.

9. An addressing system for an interleaved memory, substantially as herein described with reference to the drawings.