JPS6299973A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To increase the speed of a serial cycle, by transferring the signals of a data line in parallel by dividing them into plural shift registers and outputting in serial the output signals of main amplifiers provided to each shift register in prescribed order. CONSTITUTION:A memory section RAM is composed of four sets of memory arrays, a sense amplifier, and address decoder circuit. Signals of complementary data lines at the memory arrays are transferred in parallel through switching MOSFETs Q1-Q4. Shift registers SR1 and SR2 perform shifting operations upon receiving clock signals phi and the inverse of phi which are produced by 1/2-frequency dividing shift clock signals supplied from an external terminal CLK by means of a timing controlling circuit TC. Output signals of main amplifiers MA1 and MA2 installed to the output terminals of the shift registers SR1 and SR2 are outputted in serial to a common external terminal Ds through output circuits OB1 and OB2 having try state output functions which perform complementary operations by means of the clock signals phi and the inverse of phi.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a semiconductor memory device, for example,
RAM (Random Access Memory) for image processing
It is related to technology that can be used effectively.

[Background technology]

As a RAM for image processing to display characters and figures on the screen of a CRT (cathode ray tube), for example, the serial access RAM described in Nikkei McGraw-Hill, February 11, 1985, Nikkei Electronics J, pages 219 to 229 Memory (dual port RAM) is well known. In this RAM, data lines of a memory array are connected in parallel to a data register via a switch circuit, and data is serially output between the data register and an external terminal. As a result, the storage information of the memory cell connected to the selected word line is outputted serially, so that pixel data can be easily retrieved in synchronization with the rask scan timing of the CRT.

In this case, the signal propagation delay time in the main amplifier that amplifies the signal from the shift register makes it difficult to speed up the operation.

[Purpose of the invention]

An object of the present invention is to provide a semiconductor memory device having a high-speed serial output function.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, the signals on the data lines constituting the memory array are divided into a plurality of shift registers and transferred in parallel, and the output signals of the main amplifier provided for each of the shift registers are serially output in a predetermined order. .

〔Example〕

FIG. 1 shows a block diagram of one embodiment of the invention. Each circuit block in the figure is formed on a 1(l!) semiconductor substrate such as, but not limited to, single-crystal silicon using known semiconductor integrated circuit manufacturing techniques.

Although the semiconductor memory device of this example is not particularly limited,
The basic configuration is a dynamic RAM that is accessed in units of 4 bits (x4 bit configuration), and an internal circuit for performing image processing operations at high speed as described below is added. Although not particularly limited, the memory section R in the figure
The AM consists of four sets of memory arrays, sense amplifiers, and address decoder circuits. -Memory array section RA
M is a matrix-arranged address selection MOSF
It includes a dynamic memory cell consisting of an ET (insulated gate field effect transistor) and a capacitor for storing information. MOS for address selection of the above memory cells
The FET has its gate coupled to a corresponding word line and its drain coupled to one corresponding data line.

The configuration of such a memory section RAM is similar to that of a known dynamic RAM with a ×4 bit configuration, so
A detailed explanation thereof will be omitted. RA with the above x 4 bit configuration
The reason M is used is to allocate red, blue, green, and luminance signals to respective bits in order to form color pixel data.

Signals on complementary data lines in the memory array are connected to switches MOS FETQ1 to exemplarily shown, respectively.
Shift register SRI divided into two via Q4 etc.
and each bit of SR2 in parallel. These shift registers SRI and SR2 are provided for each of the four sets of memory arrays, for a total of eight shift registers. Although not particularly limited, among the addresses assigned to the complementary data lines, signals of odd-numbered data lines are connected to the switches MOS FETQ 1 to Q3.
The signals on the even-numbered data lines are transferred in parallel to the shift register SR2 via the switch MOSFETs Q2 to Q4. These MO3FETs QI to Q4 are turned on by a timing signal φS commonly supplied to their gates, and perform the above-mentioned signal transfer operation.

The two divided shift registers SRI and SR2 receive clock signals φ and φ, which are formed by dividing the shift clock signal supplied from the external terminal CLK into 1/2 by the timing control circuit TC, respectively. , respectively perform a shift operation. The above shift registers SRI and SR2
The output terminals are the main amplifiers MAI and M, respectively.
A2 is provided. The output signals of these main amplifiers MAI and MA2 are serially output to a common external terminal Ds via output circuits OBI and OB2 having a tri-state output function that operate in a complementary manner with the clock signals ψ and φ. Ru. The operations of the output circuits OBI and OB2 are controlled by clock signals having a phase opposite to the clock signals of the corresponding shift registers SRI and SR2.

The function of dividing the stored information for one word line in the memory array into two shift registers SRI and SR2 and reading them out in parallel, and serially outputting a signal consisting of a total of 4 bits, is the rask scan of a color CRT. This is convenient for generating red, blue, green, and luminance graphic data that constitute color pixels to be displayed in synchronization with timing.

Row address buffer R-ADB receives timing signal φr generated by row address strobe signal RAS.
Takes in external address signals AXO-AXi in synchronization with
Forms an internal complementary address signal to be transmitted to the row address decoder. The row address decoder included in the memory section RAM decodes the address signal and selects a predetermined word line and dummy word line in synchronization with the word line selection timing signal.

Column address buffer C-ADH receives external address signal A in synchronization with timing signal -0 formed by column address strobe signal CAS that is supplied with a delay.
Takes YO=AYi and transmits it to the column address decoder. The column address decoder included in the memory section RAM decodes the address signal and performs a data line selection operation in synchronization with the data line selection timing signal.

In order to perform the blue filling in units of 4 bits, the data input circuit IB consists of a total of 4 sets of circuits, and when it is put into the operating state by the operation timing signal φin, the external terminal Di
The 4-bit signals supplied from (D) are each amplified and transmitted to the input/output line I10 of the memory section RAM. As a result, a write operation is performed on each of the four memory cells selected by the address selection circuit.

In order to perform a read operation in units of 4 bits, the data output circuit OB consists of a total of 4 sets of circuits, and when activated by the operation timing signal φop, the corresponding input/output line 10 of the memory section RAM is activated. A total of 4 bits of signals are each amplified and sent to the external terminal Do (D).

The timing control circuit TC receives address strobe signals RAS and CAS supplied from the outside, a write enable signal WE, and a clock signal CLK for operating the shift register SR, and identifies the operating mode and outputs various timing signals accordingly. Form.

The refresh control circuit REFC includes, but is not particularly limited to, a refresh address counter circuit that forms a refresh address signal. The refresh address counter circuit receives the refresh signal φrf generated by detecting that the column address strobe signal CAS is set to low level prior to the row address strobe signal RAS by the timing control circuit TC, and outputs the signal RAS. In the refresh operation mode, in which the step (counting operation) is performed for each low level of , the refresh address signal formed by the refresh control circuit REFC is input to the row address buffer R-ADB. The data is then supplied to the row decoder of the memory section RAM through the row address decoder R-ADB.

Next, an example of the operation of the semiconductor memory device of this embodiment will be explained according to the timing chart shown in FIG.

For example, although not shown, the row address strobe signal R
AS is changed from high level to low level, address signals AXO to AXi are taken in, and a row-related selection operation is performed. As a result, one word line selection operation and a sense amplifier operation are performed, and a signal according to the storage information of the selected memory cell appears on each data line. For example, once the clock signal CLK is set to low level, , the timing control circuit TC generates the timing signal φS. As a result, the above switch MOS FETQl-Q
4 is turned on to transfer the signal on the data line to the shift registers SRI and SR2.

Next, when the shift clock signal CLK is changed,
The timing control circuit TC generates clock signals φ and φ whose frequency is divided by 1/2.

The shift register SRI performs a shift operation in synchronization with the rising edge of a non-inverted clock signal φ.

The output signals dll, d12, d13, etc. serially transferred from the shift register SRI are sent to the main amplifier MAL.
The amplified output signals D1, D12, D
I3... is formed.

The shift register SR2 is a shift register S that performs a shift operation in synchronization with the rising edge of an inverted clock signal φ.
Output signals d21 and d22 serially transferred from R2
, d23 . . . are amplified one after another by the main amplifier MA2, and the amplified output signals D21 . ．． D22, D23, . . . are formed.

Main amplifier M compatible with the above shift register SRI
The amplified output signals Dll, 012, D13, etc. of the AI are sent to the output terminal D via the output circuit OBI which is activated by the clock signal φ having the opposite phase (inversion) to the clock signal φ.
Sent from s.

That is, at the timing when the clock signal φ rises to a high level, a shift operation and an amplification operation of its main amplifier MAI are performed in the shift register SRI, and the timing when the clock signal φ changes from a high level to a low level, in other words, the clock signal φ changes to a high level or a low level. The output circuit OBI is activated during the second half period of the signal φ. As a result, the output circuit U is delayed by a half period of the clock signal φ.
When BI is activated, one output signal Dll, Di2, D13, .・All output terminals Ds
to be sent to.

Furthermore, the amplified output signals D21D22, D2'3 of the main amplifier M A 2 corresponding to the shift register SR2 are
... is sent out from the output terminal Ds via the output circuit OB2 which is activated by a clock signal φ having an opposite phase (non-inverted) to that of the clock signal φ. That is, at the timing when the clock signal φ rises to a high level, the shift operation and its main amplifier M are performed in the shift register SR2.
The timing when the amplification operation of A2 is performed and the clock signal φ changes from high level to low level, in other words, during the second half period of the clock signal φ, the output circuit OB2
is activated. As a result, when the output circuit OB2 is activated with a delay of half a period of the clock signal φ, the output signals 021, D22 of the main amplifier MA2,
Since D23... has already been formed, the output circuit OB2
together with its operating state and its output signal D21. D22
, D23... are sent to the output terminal Ds.

By the above operation, signals from the two shift registers SRI and SR2 are alternately output every cycle in synchronization with the shift clock signal CLK supplied from the external terminal. Above shift registers SRI and SR
2 is 1772 with respect to the shift clock signal CLK.
It operates using frequency-divided clock signals φ and φ. Therefore, the frequency of the shift clock signal CLK can be increased to twice the operating speed of the shift registers SRI, SR2 and their main amplifiers MAL, MA2. This makes it possible to speed up the operation.

〔effect〕

The signal on the data line of memory layer 1 is divided and transferred to multiple shift registers in parallel, and the shift operation of the shift register is controlled by a clock signal obtained by dividing the clock signal supplied from an external terminal. '), the frequency of the shift clock (a) can be increased.In addition, each of the shift registers is provided with a main amplifier, and synchronized with the shift order of the plurality of shift registers. The signal delay in the main amplifier can be substantially ignored by outputting the output signal of the main amplifier that has been processed.Thereby, the effect of speeding up the serial cycle can be obtained.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, the shift registers SRI and SR2 may have a write function in which data is serially supplied from the external terminal Ds and data is written in parallel to the data lines of the memory array. In addition, the signal on the data line of the memory array is divided into -4 shift registers and transferred in parallel, so that the shift operation of the shift register is performed using a clock signal whose frequency is divided by 1/4. The number of registers, main amplifiers, and output circuits can be varied in various embodiments. The memory section may have a ×1 bit configuration. In this case, it can be used to serially output an image signal consisting only of a pixel signal or a luminance signal of one of the three primary colors.

Furthermore, the memory array may be constructed of static memory cells, and the output circuit may be operated by a clock that is formed independently of the clock signal that operates the shift register. Good too.

[Application field]

The present invention can be widely used in semiconductor memory devices having a serial output function.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a timing diagram showing an example of its operation. RAM...Memory section, Rt'=DB...Row address buffer, C-ADB...Column address buffer, OB
・・Data output circuit, IB・・Data input circuit, TC・
・Timing control circuit, REFC... Refresh control circuit, SRI, SR2... Shift register, MAl, M
A2...Main...

Claims (1)

[Claims] 1. A plurality of shift registers in which signals on data lines constituting a memory array are divided into a plurality of groups and transferred in parallel, and a plurality of main units that respectively amplify the signals from the plurality of shift registers. A semiconductor memory device comprising: an amplifier; and an output circuit that serially outputs output signals of the plurality of main amplifiers in a predetermined order. 2. The semiconductor memory device according to claim 1, wherein the output of the output circuit is performed in synchronization with the shift operation of the shift register. 3. The memory array described in claim 1 is characterized in that the memory array is provided with a selection circuit and an input/output circuit that randomly write and read data in units of one or more bits. Semiconductor storage device. 4. The above-mentioned shift register consists of two parts, which perform shift operations alternately using a 1/2 frequency divided signal of the serial clock signal supplied from the outside, and the above-mentioned output circuit has its output terminal shared, and the above-mentioned Claims 1, 2, or 3 are characterized in that they are comprised of two tristate output circuits that operate complementary to each other with a 1/2 cycle delay with respect to the shift operation of the shift register. semiconductor storage device.