JPS59168983A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor memory device having small number of terminals by converting an address and data inputted serially from the outside to parallel and transmitting the data to the inside and converting the data read out parallelly from the inside to serial and outputting to the outside. CONSTITUTION:An input shift register 201 consists of a shift register of 11-bit that converts an address input to parallel and a shift register of 8-bit that converts a data input to parallel. An output shift register 202 converts a data read out to 8-bit parallelly to a serial output and outputs the data serially from a data output terminal 205 synchronizing with a clock signal 207. Thus, a semiconductor memory device can be made with small number of terminals and the lowering of mounting density can be prevented.

Description

[Detailed description of the invention] The present invention relates to a semiconductor memory device.

Figure 1 shows a conventional semiconductor layout device, 2 words
It is a 16-bit random access memory with an 8-bit configuration.

In a conventional device such as this example, addresses and data from outside the semiconductor storage device are input in parallel. For this reason, the semiconductor memory device that receives and receives this information requires a number of terminals equal to the number of input addresses and data.

In FIG. 1, 109 and 110 are address terminals to which address information is input, and 111 is a data input/output terminal through which data is input/output. In this example, 11 terminals are required for address and 8 terminals are required for data input/output, and the total ratio of address terminals and data input/output terminals to all terminals is as high as 80. It becomes more noticeable as the number increases.

Incidentally, an increase in the number of terminals results in an increase in the size of the package for mounting the semiconductor memory device. In fact, as the capacity of State 9 random access memory increases from 4 to 16 to 64, the packages also increase from 18 pins to 300 mils, 24 pins to 600 mils, and 28 pins to 600 mils.
Mills are becoming larger. Increasing the size of the package leads to a decrease in packaging density, which reduces the effect of pattern miniaturization.

This problem becomes more serious as the capacity increases (25/iK, IM, etc.).The present invention aims to eliminate this problem. Therefore, it is an object of the present invention to provide a semiconductor r storage device which requires fewer terminals for address input and data input/output.

The present invention has a built-in circuit that converts addresses and data that are serially input from the outside into parallel data and transmits the data to the inside, and a circuit that converts data that is read internally and in parallel into serial data and outputs the data to the outside. It is a semiconductor storage device.

The present invention will be described in detail below based on examples.

FIG. 2 shows a semiconductor memory device of the present invention. 204 is an address and data input terminal. 20111 is an input shift register. This shift register consists of an 11-bit shift register that converts address input into parallel data and an 8-bit shift register that converts data input into parallel data. In these shift registers, selection of address input and data input is performed by a control signal output from a 2030 control circuit. Further, address and data input is performed in synchronization with a signal 207 serving as a shift clock for the shift registers 201. This is a shift register for converting 202 8-bit parallel read/output data into serial data output. 8-bit parallel data read out from inside is input to an output shift register 202 and serially outputted from a data output terminal 205 in synchronization with a clock signal 207.

FIG.SFI is a timing chart showing the basic operation of the semiconductor memory device of FIG. 2.FIG. This is the n signal that controls the selection or non-selection of 301 devices.When this signal is low, it is in the selected state, and when it is high, it is in the non-selected state.

302 #-t This is an A/D signal that switches between address input mode and data input/output mode. When this signal is )・i, it is the address input mode, and when it is low, it is the data input/output mode. 303 Fi R/'W signal for switching between write state and read state in data input/output mode; when this signal is low, it is in the write state, and when it is high, it is in the read state. 304 input shift register and output shift register shift clock signal. This is a signal input to the terminal of 305 and 204, and 306 tl
This is a signal output from the terminal 205. 307 Ff
This is an address set cycle. 0 to low, A/D
After setting to high, input 11 pulses of shift clock,
Address information is input for each pulse. As a result, address information is set in the shift register 201, which performs the transformation of the address input.

308 is a data write cycle. n to row,
After setting the A/D to low, eight pulses of the shift clock are input, and data is input for each pulse. As a result, data is reset to the shift register 201 that converts the data input into parallel data. Writing/writing to/from the internal memory is performed at the rising edge of the n signal.

309 is data read cycle 2. Go to low,
After setting A/'D to low, input 5-8 pulses of shift clock. Reading from the inside to the shift register 202 is performed at the falling edge of the input/output signal, and data is outputted from this shift register to the outside in response to each pulse of the shift clock.

In such a semiconductor memory device, address input and data input/output terminals, which conventionally had 19 terminals, are reduced to two terminals: address/data input and data output.

Therefore, it is possible to suppress an increase in the number of terminals due to an increase in memory capacity. The number of terminals can be reduced by inputting addresses and data serially from the outside and converting them to parallel data inside the semiconductor storage device, and by converting the parallel data from the inside into serial data inside the semiconductor storage device and outputting it to the outside. A semiconductor memory device can be manufactured, thereby preventing a decrease in packaging density.

The present invention is fully effective when used with a CPU having a small number of output pins in a portable device or the like.

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[Brief explanation of drawings]

Figure 1 shows a conventional semiconductor storage device. 101... Memory cell array 102... Row decoder 105... Sense amplifier 104... Column decoder 105.106... Address buffer 107.
...Input/output circuit 108... Chip control circuit 109,
110...Address terminal 111...Data input/output terminal 112...Control terminal 113...Power terminal FIG. 2 shows a semiconductor memory device of the present invention. 201... Input shift register 202...
... Output shift register 203 ... Control circuit 204 ... Address and data input terminal 20
5... Data output terminal 206... Control terminal 207... Clock terminal. FIG. 3 is a timing chart showing the basic operation of the semiconductor memory device of the present invention. 301...CE 302...A/D 303...R/w 304...Clock 305...Address and data input signal 306
...Data output signal 307...Address set cycle 308...
. . . Write cycle 309 . . . Indicates a read cycle. Applicant Suwa Seikosha Co., Ltd. Patent attorney Tsutomu Mogami

Claims (1)

[Claims] (1) In a semiconductor memory device having a multi-bit configuration in which address information is input and data is written, read and written, addresses and data input serially from outside the semiconductor storage device are converted into parallel data. What is claimed is: 1. A semiconductor storage device comprising a circuit for transmitting data to the inside of the semiconductor storage device and a circuit for serially converting data read out in parallel from inside the semiconductor storage device and outputting the converted data to the outside of the semiconductor storage device.