JPS6273862A - Data input and output memory - Google Patents

Abstract

PURPOSE:To attain high speed data processing and asynchronizing data input/ output by applying read of a data from the 2nd shift register in time division and applying signal input/output of data simultaneously and asynchronizingly. CONSTITUTION:A video data by one line inputted serially is split and stored into a memory array 1 in parallel, and the video data stored splittingly is read sequentially in parallel to be outputted as the serial video data by one line, then the storage and write of the video data to the memory array 1 is executed in high speed. Since the storage/read to/from the memory array 1 are executed in time division, the read is executed at the interval of storage to the memory array 1 and the serial output of the video data are attained simultaneously with the serial video data input. Thus, high speed data processing is attained and asynchronizing data output to the data input is attained.

Description

[Detailed description of the invention] 〔Technical field〕 The present invention can simultaneously and asynchronously input data.

Concerning data input/output that allows access to output data.

More specifically, the present invention relates to a data input/output memory capable of converting the frequency of a video signal, synchronizing timing, performing N-time delay, and the like.

[Prior art]

For example, the video signals of laser beam printers that record images by scanning laser light, and the video signals of televisions, which have a large amount of data, are transmitted using serial signals that break down the image into serial signals for each line and transfer the data. The transmission method is common.

For example, when transferring data to a laser beam printer, when the sending host computer sends a video signal to the laser beam printer, it has a buffer φ memory for synchronization, and the laser −
It is necessary to transfer the video signal using a serial transmission method in accordance with the rotation of the rotating mirror of the beam printer. Also, the size of the image is changed by changing the frequency of the video signal. Such a buffer memory is also used for so-called scaling processing.

Such buffer memories include first-in first-out memory (FIFO memory),
A static RAM capable of high-speed operation is used. The former type of memory has a simpler circuit configuration, but because it does not have high speed or large capacity, it can only be used for synchronizing several dozen pieces of data at most. Match.

Although it is highly variable in magnification and highly versatile, it has the disadvantage that it requires an address counter, selector circuit, etc., making the peripheral circuit configuration for memory operation complicated.

〔the purpose〕

An object of the present invention is to provide a data input/output memory with a new configuration that solves the drawbacks of the above-mentioned memory, and
The purpose is to provide a data output memory that operates well without a complicated external control configuration even for high-speed data input/output, and that does not allow simultaneous and asynchronous data output. An object of the present invention is to provide a data input/output memory having a configuration suitable for being made into a multi-chip.

〔Example〕

The present invention will be explained in detail below based on Examples.

FIG. 1 is a diagram showing an example of a block configuration of a memory provided with the present invention.

Memory array 1 is configured to read and read multiple data Φ bits.
This is memory that allows write operations.

The memory φ timing control block 2 is a block that controls the timing of the read φ write operation of the memory array l, the address of the memory array, and the like.

The shift Q register 3 has a data length of 128 bits, and is a register for converting the video input data signal DIN serially sent from a video φ data generation source such as an image scanner into a parallel signal, and converts the converted video data signal DIN into a parallel signal. The data signal is sent in parallel to buffer register 4, which is a buffer when writing to memory array 1.

Buffer register 4 has a capacity of 136 bits, and simultaneously stores 8-bit control data including line length data of the video signal sent from memory write control block 5, and stores 128-bit control data in memory array l. Video-
Write in parallel with the data signal.

The memory write control block 5 converts the write array address signal and line length data of the memory array I into a line interval signal indicating a valid interval of one line of the video input data signal DIN inputted from the video conference data source. Generate based on WDEt.

Buffer register 6 has a capacity of 136 bits and is used when reading memory array 1. The data read out in parallel from the memory array I undergoes parallel-to-serial data conversion via the buffer register 6, in which the video data is converted into a 128-bit shift signal that generates the video output data signal DOUT. • Control data is sent to the register 7 and also to the memory read control block 8.

The memory read control block 8 inputs from the buffer register 6 the read address array Φ address signal of the memory array 1 and the line interval signal RDEt indicating the valid interval of one line of the video output data signal DOUT. Based on the data, e.g.
It is generated in synchronization with the input of the lead fist start signal RDSt from an image processing device such as a printer.

CLR unreliable second signal e.g. from video-data source=
One screen worth of video - entered at the start of data entry,
These are signals used to initialize the block, and the WCK signal and RCK signal are the video data generated from the video data source and the image processing device during write and read operations, respectively.
This is a data clock signal. Note that the symbol at the end of the signal name in this embodiment indicates that the signal is an active low signal. In this way, serially input video data is converted into parallel data, stored in the memory array 1, read out in parallel and output serially, and the storage and read operations are independently and asynchronously executed at high speed. .

2 to 4 are timing charts for explaining circuit operation.

Figure 2 shows a case where the data length of one video line is 512 bits, the data length of shift registers 3 and 6 is 128 bits, and memory array 1 has a 136 x 8 bit configuration (the number of arrays is 8). is assumed. in this case,
Memory write control block 5 and buffer register 4
The number of control data signal lines between the memory read control block 8 and the buffer register 6 is 7 bits (1
There are a total of 8 bits: 28-bit count signal) and 1 bit (line continuation signal). Note that the data length of one video line does not need to be an integral multiple of the data length of shift register 3.6, and the data length of one video line does not need to be an integral multiple of the data length of shift register 3.6. It may change to

The timing chart in Figure 2 shows that after the circuit is reset using the CLR1 signal, the video and clock WCK are used to reset the circuit.
A timing example is shown for application to frequency conversion in which video data is written and, at the same time, a read operation is performed using a video clock RCK that is faster than the video clock WCK at the time of writing. Also, W in the figure. -W7°R0 to R7 each indicate the array address of the memory array 1 for reading at the time of writing. As is clear from FIG. 2, the video conference data for l lives input serially is divided and stored in parallel in memory array 1, and when read, it is divided into memory array l and stored. The video data is read out multiple times in parallel and output serially. Therefore, since the video data for one life is stored in the memory array 1 intermittently, the video data stored in the memory array 1 cannot be read when the storage operation is interrupted. , thereby simultaneously serially inputting video data and serially outputting video conference data at different frequencies.

Next, FIGS. 5 to 9, which show configurations for achieving the operations shown in the timing conflict chart shown in the second figure, will be explained using timing charts.

FIG. 5 shows a specific example of the circuit configuration of the memory write control block 5.

Write address-counter IO is memory array IO
This is a counter that counts the array address at the time of writing, and in this embodiment, as described above, the memory
Since the number of arrays in array 1 is 8, a 3-bit counter is used. The write array address signal, which is the count output of the write address number counter 10, is sent to the memory timing control block 2 as shown in FIG. 7, and is used as a write address for write data.

In this embodiment, the write address counter 10 is a synchronous fist counter, and the CLR2
When the write-array number address signal is cleared to ViO and the enable terminal E is 1, the write clock W
The count φ is increased by inputting CK.

The write bit reference counter 11 counts the WCK signal during the output period of the WDE main signal.
In this embodiment, the data length of the shift register 3.7 is 128 bits, so a 7-bit synchronizer is used. Use an eggplant up counter. The write bit e count signal of the count value is a CLR customer.

WRQ! It is reset to the value O by the signal, and the ripple carry output RC becomes 1 when all bits become the value 1. This l carry output RC is used as the enable signal E of the write array counter 10 and as the input of the flip-flop 14. Further, the write φ bit count signal is stored in the memory array 1 together with the video data via the buffer register 4, as shown in FIG. Thereby, the length of the video data stored in each memory array is stored in association with the video conference data as a read bit count signal.

D-type flip-flop 12 and AND gate 13
is a circuit for detecting the rear end of the WDEt signal,
A VEND signal as shown in the timing chart of FIG. 3 is generated. The VEND signal is logically summed by the OR gate 16! It is used as a signal to end the input of video data for the life, and becomes the enable signal E of the write array contention counter 10 and the input of the flip-flop 14. Also, MWDE!, which is delayed by one clock from the WDEt signal due to the WCK signal! The signals are stored in memory array 1 via buffer register 4 as shown in FIG.

The MWDE main signal is a line continuation signal and is used for reproducing one line of the video signal during a read operation, that is, for determining the end of reproduction of one line when reproducing the RDE main signal.

The output WRQ signal of the D-type flip-flop 14 is used as a data write signal to the buffer or register 4 as shown in FIG. 8, or as a write request signal to the memory timing control block 2 as shown in FIG. used as.

FIG. 6 shows a specific example of the circuit MIi of the memory pot read control block 8.

The lead fist address counter 20 is stored in the memory array 1.
This is a counter that counts the array address when reading. Similar to the write address counter 10, it is a synchronizer that outputs a 3-bit linear Φ array address signal to the memory timing control 2 as shown in FIG. It is an eggplant fist up counter. The read address and counter 20 are cleared to a value of 0 by the CLR customer signal, and are counted up by inputting the read clock RCK when the enable terminal E is 1.

The read bit reference counter 21 receives the read address -
This is a 7-bit synchronous down counter for counting the enable signal E of the counter 20 and the bit length for generating the RDE attack signal. The read contest bit counter 21 receives a video signal from the memory array 1.
Leading with data. RCK clock for loading the read bit count signal (= write bit count signal - indicating the bit length of the read video data) by the RLD signal and serially outputting the video data from the shift register 7. A count φ is down for each input, and when the count value reaches 0, the ripple number carry signal RRC becomes 1. Therefore, the RRC signal is 1
When this happens, the serial output of the video conference data from the shift register 7 ends.

D type flip red flop 22, AND gate 23
, JK type clip prop 24 is an MRD read with video meeting data from memory array.
RD by E main signal (-MWDE main signal) and RLD signal
This is a circuit for generating the E main signal. That is, the flip red flop 24 is set by the RLD signal by inputting the RDS main signal, and thereby the RDE signal becomes low. After that, MRDE! in the data read from memory array 1! Shift of video data with signal 1 - RRC after completion of serial output from register 7
The signal resets flip-flop 24. In this way, from the input of the RDS main signal from the video data output light (for example, a laser m-beam printer) until the serial output from the video data shift register 7 when the MRDE customer signal is 1 is completed. , RDE* signals can be formed. Therefore, the RDEt signal indicating the input data length of one line can be formed in accordance with the data read clock frequency.

D type-Furi Ruff-Flotsub 29, NOR game) 30
is the RDS as shown in the timing chart of Figure 4.
Signal for read start from t signal, RTOPI
This is a circuit for generating a signal.

SR flip contest flop 25. D type - The flip-flop 26 and the AND gate 27 set the first data from the IJ array 1 to the buffer register 4 using the first WRQ signal after the input of the CLR signal.
This is a circuit for generating a Q signal. This FRRQ signal becomes an RRQ signal via an OR gate 28. After this circuit operates, a request to read the data e set of the buffer register 4 is made by the RTOP signal and the RRC signal. That is, the output RRQ signal of the OR gate 28 makes a data skew set request to the memory timing control block 2, and in response, the memory timing control block 2 outputs the RDLD signal. Furthermore, F.R.R.
The Q signal is used to store video data to be output first in the buffer register 6 in order to enable serial output of video data when the RDS zero signal is first input. It will be done.

FIG. 757 is a diagram showing the exchange of signal lines in the memory timing control block 2.

Memory timing control block 2 receives the WRQ signal, R
In response to the RQ signal, it outputs an array address signal, WR signal, and RD signal to control data read and write operations for the memory array 1.

When the WRQ signal is received, a write operation is performed using the write array address signal from the write address conflict counter 10 shown in FIG. The read operation is performed using the array φ address signal from the illustrated address counter 2o, and RD LD which is the data and latch signal to the buffer register 6 when reading data.
Output a signal.

Incidentally, when the WRQ signal and the RRQ signal are generated at the same time, priority is given to the signals so that either read or write operation can be accepted.

Figure 8 shows shift register 3 and buffer register 4.
FIG. 3 is a diagram showing the exchange of peripheral signal lines.

The video input data signal DIN is serially written into the shift register 3 by the clock WCK signal. W
The DEt signal is used as a shift operation permission signal.

Buffer register 4 is a D-type flip-flop, and latches parallel data from shift register 3 in response to the WRQ signal, which becomes write data to memory array l.

Figure 9 shows buffer register 6 and shift register 7.
FIG. 3 is a diagram showing the exchange of peripheral signal lines.

Contrary to FIG. 8, parallel read data from memory array 1 is latched into buffer register 6, which is a D-type clip flop, by the RDLD signal.

The latched data is stored in the memory read control block 8.
, and are sent to shift register 7, respectively.

The RLD signal is used as a signal to load data into the shift register 7.

As described above, one line of serially input video data is divided and stored in parallel in the memory array L, and the divided and stored video data is sequentially read out in parallel. Since the video data is output as serial video data, storage and writing of video data to the memory 7 ray 1 can be executed at high speed.

In addition, since storage and reading from the memory array are performed in one time division, reading can be performed between storage into the memory array, thereby allowing serial video data to be input at the same time. Serial output of video number data becomes possible.

Furthermore, since the video data storage and read operations of the memory array I are operated by WCK and RCK, respectively, and are operated independently, the storage and read operations can be performed asynchronously.

In this embodiment, input data and output data each have a 1-bit memory configuration, but the shift register 3,
Buffer contention register 4. Memory array 1, buffer
By increasing the register 6 and shift register 7 by the necessary number of bits, it becomes possible to convert to other bits.

Further, the data to be processed is not limited to video fist data, but may also be serial data output from a word processor, computer, etc., and can be used as input/output data for various data.

In addition, as can be seen from the timing chart in Figure 2, the read/write interval to the memory φ array l becomes longer, so the slower memory array is used even for high-speed serial input/output of video data. It is available for use.

In addition, even when dynamic memory is used as memory array 1, there is a margin in timing, so it has a built-in self-refresh function and pseudo-metallic RA.
M operation becomes easily realizable.

Furthermore, the line length of written data can be reproduced simply by inputting a read start timing signal, eliminating the need for a line length counter during readout, which was previously required, and making this memory application device It becomes possible to simplify the circuit configuration.

Furthermore, for the same reason, it becomes possible to deal with signals having different data lengths for each line.

〔effect〕

As explained above, according to the present invention, a shift register for data input and a shift reference register for output of memory cells are provided, and these shift registers are operated in a time-division manner.
Since data input/output operations are performed, high-speed data processing is possible, and data output can be performed asynchronously with respect to data input. In addition, the memory configuration is simple, making it suitable for one-chip integration.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of a block configuration of a memory according to the present invention. FIGS. 2 to 4 are timing conflict charts for explaining circuit operation. FIG. 5 is a memory write control diagram of FIG. 1. FIG. 6 is an explanatory diagram showing a configuration example of the block 5; FIG. 6 is a diagram showing a configuration example of the memory e-read control block 8 in FIG. 1; FIG. 7 is a diagram showing a configuration example of the memory φ timing control block 2 in FIG.
8 is a diagram showing an example of the structure around the shift register and buffer register 4 in FIG. 1, and FIG. 9 is a diagram showing an example of the structure around the shift register and buffer register 4 in FIG. FIG. 3 is a diagram showing an example of a peripheral configuration. In the figure, 1 is a memory array, 2 is a memory timing control block, 3 and 7 are shift registers, 4 and 6 are buffer registers, 5 is a memory write control block, and 8 is a memory read control block. be.

Claims (1)

[Claims] It has a first shift register for inputting data and a second shift register for outputting data, and writes data in the first shift register to memory cells and writes data from the memory cells in a time-sharing manner. A data input/output memory characterized in that a data read operation to the second shift register is performed in a time-division manner, and a data serial input/output operation is performed simultaneously and asynchronously.