JPS62249574A - Video memory - Google Patents

Abstract

PURPOSE:To allow one kind of a video memory to correspond to an NTSC system and a PAL system by stopping the writing of data in a memory cell when a write address reaches a previously fixed constant value. CONSTITUTION:The video memory 100 initializes an address obtained from a write address generating circuit 111 based on an external reset signal inputted from a terminal 104, changes an address value and writes serial data in a sequential memory cell 110. At the time of detecting the write address reaches a certain constant value, a writing stop signal generating circuit 130 generates a writing stop signal. Thereby, the writing operation of data in the memory cell 110 is stopped. The writing stop state is released by the succeeding external reset signal. Consequently, one kind of the video memory can be allowed to correspond to both the NTSC and PAL systems.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a specially designed memory suitable for performing image signal processing.

[Conventional technology]

In digital video equipment, line memo IJ IC (
Lines indicate horizontal scan lines. ) is one of the important devices used in image signal processing, such as comb filters, vertical spatial filters, or interpolators.

As an example of this line memory IC, [Nikkei Electronics J January 27, 1986 issue, NO, 387, PP]
, 92-94, a line memory IC dedicated to the NTSC system and a line memory IC dedicated to the PAL system, which are discussed in the paper titled "Dynamic memory dedicated to approximately 1 x 8 bits of images focused on the standard television system". There is. Each has a resolution of 8 bits and a sampling frequency of 4 fsc.
(fsc is the frequency of the color subcarrier) can store one horizontal scanning line of video signal sampled, and the memory capacity is 8 x 910 bits and 8 x 1135 bits, respectively.
It's a bit. It inputs and outputs serial data asynchronously, and has built-in address generation circuits for writing and reading, respectively. This address circuit is controlled by three external signals, clock, reset, and enable, for writing and reading, respectively. The address value is initialized by a reset signal and advances by one each time a clock is input. Therefore, by controlling these signals, it is possible to obtain a maximum delay amount of 910 clocks or 1155 clocks.

[Problem that the invention seeks to solve]

In the above conventional technology, NTs with different numbers of data in one scanning line
In order to support the two systems, the SC system and the PAL system, two types of Memo+7 ICs are required, each of which is dedicated to the two systems.

An object of the present invention is to provide a video memory that is compatible with both the NTSC system and the PAL system.

[Means for solving problems]

In order to achieve the above object, the video memory of the present invention initializes the write address with an external reset signal, then changes the address value and sequentially writes serial data to the memory cells, so that the address value is set in advance. It detects that a certain value has been reached, and after that, all data lines or word lines in the memory section are put into a non-writing state, thereby stopping the writing operation of data to the memory cell. The state will be canceled by the next external reset signal.

[Effect]

For example, in a video memory having a memory capacity equivalent to about one line of the NTSC system, after data corresponding to the memory capacity is written, writing is stopped until the next external reset pulse is input. As a result, video data for the video display period can be stored for PAL video signals, and NT
A video system compatible with the SC system and the PAL system can be constructed.An embodiment of the present invention will be described below with reference to FIG. In FIG. 1, 100 is a video memory according to the present invention;
101 is a video input signal Din terminal, 102 is a video output signal Dout terminal, and 103 is a write clock signal WCLK.
Input terminals, 104, write reset signal WIR input terminal, 105, read clock signal RCLK input terminal, 10
6 is a read reset signal RRBS input terminal, 107 is a power supply terminal, 108 is a ground terminal, 110 is a memory cell array, 111 is a write address generation circuit, 112 is a write column address decode circuit, 113 is a write row address decode circuit, and 114 is a write circuit. 115 is a latch circuit, 121 is a read address generation circuit, 122 is a read column address decode circuit, and 125 is a read row address decode circuit.

124 is a read switch circuit, 125 is a latch circuit, 1
50 is a write stop signal generation circuit.

In this embodiment, it is assumed that the video signal is quantized into n bits (n is an integer). Therefore, it is assumed that there are n video input signal Din terminals 101 and n video signal output Dout terminals 102, respectively. It is assumed that the memory cell array has a capacity of, for example, n x 1024 bits. That is, video data for 1024 pixels quantized to n bits can be stored. Each memory cell has a structure having two sets of data lines and word lines, one for writing and one for reading, so that writing and reading of data can be performed independently. An example of this memory cell is shown in FIG. Further, FIG. 3 is a timing chart for explaining the write operation of the embodiment of FIG. 1.

The operation of this embodiment will be explained below. In the write address generation circuit 111 and the read address generation circuit 121, each time the write clock signal WCLK from the input terminal 103 and the read clock signal RCLK from the input terminal 105 are input, the value of each write and read address is set to 1. Proceed step by step. These address values are initialized by a write reset signal WRES and a read reset signal RRES from input terminal 104, respectively. In this embodiment, the memory section has a capacity for 1024 pixels, so the write and read addresses are 10.
It's bit. These address generation circuits 111 and 1
Specifically, 21 can be constituted by, for example, a 10-bit counter circuit. The write address is divided into a column address and a row address, and each write column address decode circuit 1
12 and a write row address decode circuit 113. The video input signal Din of the write row address is latched in the latch circuit 115 by the write clock WCLK.

There is. Write column address decode circuit 112 decodes the write column address. In the write switch circuit 114, data is written into the memory cell specified by the latch circuit based on this decoded output. Data read operations are performed in the same way as write operations. The read address generated by the read address generation circuit 121 is sent to the latch circuit 1 through the read column address decode circuit 122 and the read row address decode circuit 123, the read switch circuit 124, the latch circuit 125, and the latch circuit 1 through the switch circuit 124.
25 and is latched by the read clocks RCI and RCI, K, and then output from the output terminal 102.

Through the above operations, serial data can be input and output. The amount of signal delay caused by this video memory can be controlled by the input timing and period of write and read reset signals WEtES, RRES and clock signals WCLK, RCLK.

The write stop signal generation circuit 130 detects that the value of the write address has reached a certain constant value, and generates a write stop signal D1.
occurs. In this embodiment, this address value will be explained as, for example, the 1024th address value after reset, but the present invention is not limited to this. If the write address counter 111 is composed of a 16-bit counter, a carry signal indicating that this counter has counted 1021 times after being reset may be used as a timing signal for generating the write stop signal n. In addition to using the carry signal of the counter, the address value may be decoded and this decoded pulse may be used as a timing signal for generating the write stop signal D1. The generated write stop signal is canceled by the write reset signal WIES. This write stop signal generation circuit 130 can be easily realized with a circuit configuration such as an R8 type flip-flop. Before this write stop signal, the write column address decode circuit 112
and stops the decoding operation during the write stop period.

FIG. 4 shows an embodiment of the write column address decode circuit 112 and the write switch circuit 114. In Fig. 4, 401, 402, 407 are inverters, 403°4
℃4, 405, 4C16 are AND circuits %408~4
15 is a MOS switch. In FIG. 4, in order to simplify the explanation, the write column address is 2 bits and the write data is 1 bit, but the present invention is not limited to these.

The write column address from the write address generation circuit 111 is guided to inverters 401 and 402 to invert the level. The signal of each bit of the write column address or its inverted output signal and the write stop signal from the write stop signal generation circuit 130 are connected to AND circuits 405 , 404 ,
405 and 406. When the write stop signal 1 is at high level, the column address is decoded, and the output of any one of AND circuits JQ3, 404, 405, and AO6 becomes high level, turning on the write switch connected thereto. Write data and its inverted signal are led to each write switch by a write common line, which is further connected to each write data line. When any one of the write switches is turned on, the write data line and the write common line connected to that switch are connected, and write data is written. When the write stop signal is at a low level, the AND circuit jLQ5, A(14).

405, all outputs of AO6 are at low level, all write switches are turned off, and no write data is written.

An example in which this embodiment is used as a one-line delay line for a video signal of the NTSC system (910 dots/line) will be explained using the timing chart of FIG. 5(a). In this embodiment, it is assumed that circuits such as counters and latches operate in synchronization with the falling timing of the clock signal. The video input signal Din input from the video signal input terminal 101 is latched at the falling timing of the write clock WCLK. When the write reset signal wags is inputted at the timing shown in the figure, the write address 3a is generated at the timing shown in the figure. In this figure, the initial value of the address is 1, and the address value increases by one each time a clock is input. However, the present invention is not limited to this. Write reset signal WRES
is input at 910 clock cycles. Therefore, after the reset, addresses after the 911th address will not be generated, and therefore no write stop signal will be generated, so all input video signals Din will be written into the memory cells.

Next, this example is based on the PAL method (1135 dots/line).
An example of use as a one-line delay line for a video signal will be explained using the timing chart of FIG. 3('b). The write reset signal WRES is input at 1135 clock cycles as shown in the figure.

Of the input signals Din, 1o24 after inputting the reset signal
The video data of the clock period is written to the memory cells designated by the write address values 1 to 1024, respectively.

After the 1024th address is generated, the write stop signal 3b is generated and the write operation is stopped for 111 clock periods until the next reset signal WRES is input. Therefore, data for 1024 dots of PAL system can be stored.

As described above, in the case of the NTSC system and the PAL system, it is sufficient to input the write clock signal WCLK with a dot cycle and the write reset signal W RES with a 1 line cycle as write system control signals. The PAL system can be supported using the same control method as in the case.

In the embodiment shown in FIG. 4, the circuit configuration is such that the gate circuits 40!1 to 406 that switch whether or not to stop writing are combined with the gate circuits 403 to 406 that decode column addresses.
Another way to stop writing by setting all the write data lines to high level is to configure the AND circuits 403 to 406 that decode column addresses as three-state circuits, and to pull up the output of these circuits to stop writing. There are two ways to control this using the stop signal 1, a method where a switch is provided on each pull-up write data line and all of them are turned off by the write stop signal 6b, and a method where the write common line is set to 70 when writing is stopped. Conceivable.

Furthermore, all write word lines in the write row that selects the write word line may be turned off. This write stop means can also be used for the write enable function. A terminal for inputting a write enable signal may be provided, and the write enable signal and the write stop signal may be logically summed so that either one of the signals causes the write stop state.

It is also conceivable that the address generation circuits 111 and 121 are constructed of shift registers in addition to counters. in this case,
An address decoding circuit becomes unnecessary. Further, although the clock signal and the reset signal are provided in separate systems for writing and reading, the present invention can also be applied to an input/output synchronous type video memory in which these signals are combined into one system.

When there is one system of reset signal and one system of clock signal, it is necessary to provide a certain offset between the write address and the read address in order to compensate for the amount of delay caused by the latch circuits 115 and 125.

For example, assume that the external reset signal resets the read address generation circuit, detects that successive addresses have reached a certain value, and uses this detection pulse as a reset signal for the write address generation circuit to reset the two addresses. It becomes possible to have an offset in between. In this case, after the external reset signal is input, at the timing of the first read sea address detection pulse,
By releasing the write stop signal port, desired write stop can be performed without malfunction.

Further, in this embodiment, the memory capacity is 1024 dots, but the present invention is not limited to this. For example, if a memory cell array with a memory capacity of approximately m horizontal scanning lines (m is an integer) is divided into several regions,
Writing may be stopped each time writing to each area is completed.

[Effects of the Invention] According to the present invention, it is possible to configure a video memory that is compatible with both the NTSC system and the PAL system with one type, and it is possible to reduce development costs and production costs.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a video memory according to the present invention, FIG. 2 is a circuit diagram showing an embodiment of a memory cell used in the video memory according to the present invention, and FIG. 3 is an embodiment of the video memory according to the present invention. FIG. 4 is a circuit diagram showing an embodiment of a write column address decode circuit and a write switch circuit used in a video memory according to the present invention. 100... Video memory, 110... Memory cell array. 111...Write address generation circuit, 112, N3.
...Write address decoding circuit, 114...Write switch circuit, 121...Read address generation circuit, 122.123
. . . Read address decoding circuit, 124 . . . Read switch circuit, 130 . . . Write stop generation circuit.

Claims (1)

[Claims] 1. Storage means capable of storing digitized n-bit (n is an integer) video data for at least about one horizontal scanning period, n input terminals, n output terminals, and input terminals from the n input terminals. means for writing the n-bit video signal into a storage area in the storage means; means for reading the n-bit video signal from the storage area and guiding it to the n output terminals; and addresses for writing and reading to the storage area. and means for inhibiting writing of the video signal by stopping selection of a storage element in the storage area based on the writing address, and further comprising means for inhibiting writing of the video signal by stopping the selection of a storage element in the storage area based on the writing address, and when the writing address reaches a certain value, A video memory characterized in that writing of the video signal to the storage area is stopped during a period until address initialization is performed.