JPH0393090A - Video memory - Google Patents

Abstract

PURPOSE:To output the data on a new address immediately after the address is reset by adding a serial-parallel conversion circuit, a reset address data buffer register, a write control means and a read control means. CONSTITUTION:Data of m-bits are inputted to the serial-parallel (S/H) conver sion circuit 8b one bit by one by a signal from the write control means 45, and they are held in the reset address data buffer register 16. Subsequent data are inputted to the S/H conversion circuit 8a one bit by one and m-bits are collectively written into a memory array 10 through an input buffer register 9. Data of m-bits are outputted from the register 16 one bit by one through an output change over switch 25 by a signal from the read control means 46. Then, data are outputted from an H/S conversion circuit 12 one bit by one through the switch 25 in a written order. The control means 45 and 46 input and output data to and from a video memory 1 immediately after the address is reset.

Description

[Detailed description of the invention] [Industrial application field] TECHNICAL FIELD The present invention relates to video memory.

[Conventional technology]

FIG. 10 is a diagram showing a basic example of a conventional video memory, in which 1 is an integrated video memory, 2 is a data input terminal, 3 is a data output terminal, and 4 is a write clock input for data input. terminals, 5 is a write address setting signal input terminal that controls the setting timing of the write address, 6 is a read address setting signal input terminal that controls the setting timing of the read address, 7 is a read clock input terminal that controls data output, and 8 is a read address setting signal input terminal that controls the setting timing of the read address. a serial-to-parallel conversion circuit for converting serially input m-bit data (m is an integer) into parallel data, 9 an input buffer register circuit, 10 a dynamic memory cell array, 11 an output buffer register circuit, 12 is a parallel-to-serial conversion circuit that converts the input m-bit serial data into input serial data by the serial-to-parallel conversion circuit 8, and 13 controls the timing of data transfer of the video memory 1. In the control circuit, 14 is an address input terminal for inputting a write address arbitrarily, and 15 is a terminal for inputting a read address arbitrarily.

One of the reasons why the video memory 1 has such a structure is that the data period of the video signal is shorter than the cycle time of the DRAM.

In other words, serial-parallel conversion 8 is performed at the input, parallel-serial conversion 12 is performed at the output, and the memory cell array 10
DR by accessing m bits at once.
Access to AM corresponds to m times the cycle.

Another reason is that while a normal DRAM cannot perform writing and reading at the same time, video signal processing requires simultaneous input and output processing.

Further, it is necessary to perform a flash refresh on the DRAM. Therefore, it is necessary for the memory cell array ↓O to perform read, write, and refresh cycles every time m bits of data are input/output. The number m of parallel data is set to be a sufficient number to perform the three cycles.

In addition, buffers 9 and 11 are provided at the input and output of the memory cell array 10 so that each cycle can be performed in a time-sharing manner.
Simultaneous input and output is possible by temporarily storing data.

Examples of this type of video memory include Nikkei Electronics, ``LM chips exclusively for field memory to be released all at once for VTRs/TVs'', May 18, 1987 issue,
Examples include those described in pl47-162.

[Problem to be solved by the invention]

The above conventional technology has the following problems.

FIG. 11 is a timing chart showing an example of the operation of the video memory shown in FIG. A is a read address setting signal, and a new read address is set at the falling edge of this signal. B indicates what cycle the memory cell array 0 is executing, R indicates a read cycle, W indicates a write cycle, and Rf indicates a refresh cycle.

C is the data content of the output buffer register circuit 11, D
is the data of the output buffer register circuit 11 in parallel.
This is a signal to be transferred to the serial conversion circuit 12, and is transferred at the rising timing.

E is the output of the parallel-serial conversion circuit l2, that is, the data output. The parallel-serial conversion circuit 12 outputs data l bits at a time in synchronization with a read clock (not shown).
! After outputting up to n bits, at time te, the data at address (K-1) held in the output buffer register circuit l1 is transferred to the parallel-serial conversion circuit fl12.

When the data transfer is completed, a read cycle starts from time t2, data at address (K) is read, and the read ends at time t, and the output buffer register circuit 1
Keep it at 1.

Next, at time t4, an address setting signal is input, and the read address is set to a new address (address O). At this time, since the W cycle is being executed in the memory cell array 10, after the W cycle ends, that is, from time t, address 0 is read, and at time 1, the output buffer register circuit l1
will be forwarded to.

Then, at time t. The data is transferred to the parallel-to-serial conversion circuit 12 and output.

Here, after the read address reset command is input at time t4, time t. The time it takes to obtain data output is determined by the memory cycle margin (the time from when the address setting input is input until the memory cell array 10 reads data and the output buffer register circuit 11 holds the data read from the new address). ) is required, and because it is difficult to use unless the time until new data is obtained after reset is constant, it is set to m clocks, which is the same as the number of bits of serial-to-parallel conversion. However, from the perspective of the user of the video memory, it is more convenient and user-friendly to output the setting signal immediately after inputting it than to outputting the m-th bit after the address setting signal is inputted.

That is, there is a problem in that after address reset, there is a delay of several tens of clocks before data at a new address is output.

SUMMARY OF THE INVENTION An object of the present invention is to provide a video memory capable of outputting data at a new address immediately after address reset.

[Means to solve the problem]

The above purpose is to provide a first serial-to-parallel conversion circuit that inputs serial data and outputs m-bit parallel data, and a second serial-parallel converter that inputs serial data and outputs parallel data to m-bit 1. a conversion circuit, an input buffer register that holds the output of the first serial-parallel conversion circuit, a reset address data buffer register that holds the output of the second serial-parallel conversion circuit and outputs serial data, and an input buffer. A dynamic memory cell array that stores register output data, an output buffer register that holds data read from the memory cell array, and a parallel memory cell that receives m-bit data transferred from the output buffer register and outputs it in series.
A serial conversion circuit, an output data changeover switch that selects and outputs either the output data of the reset address data buffer register or the output of the parallel-serial conversion circuit, a write address generation circuit that provides a write address, and a read address that provides a read address. An address generation circuit, an address selection switch that selects whether the address given to the memory cell array is a write address or a read address, a write power counter that generates the write request timing, and a read request and a write request that occur simultaneously on the time axis. When the write control signal changes from the first state to the second state, the second
The serial data of m bits is input bit by bit into the serial-to-parallel conversion circuit of the 1 bit at a time, and is held in the reset address data buffer register, and the write address generation circuit is reset. 1 serial-to-parallel conversion circuit, and is controlled so that it is sequentially written to the memory cell array via the input buffer register circuit every time m bits are fetched, and the read control signal is
When the state changes from the state to the second state, data is output bit by bit from the reset address data buffer register via the output data changeover switch, the read address generation circuit is reset, and the output buffer register is output from the memory cell at the reset address. The data is held in the parallel-to-serial conversion circuit via the parallel-to-serial conversion circuit. After reading the m-bit data of the reset address data buffer register, the data is output from the parallel-to-serial conversion circuit via the output data changeover switch, and the data read out in the order written to the memory cell array is then converted from parallel to serial. This is achieved by controlling the output from the circuit.

[Effect]

When the write control signal is in the first state, the input data is input bit by bit to the first serial-to-parallel conversion circuit, counted by the write counter, and then sent to the first serial-to-parallel conversion circuit. When the captured data reaches m bits, the write counter outputs a write request, and at the same time transfers the m bits of data to the input bus register, the write address generation circuit writes it to the memory cell array at the address to be generated. The operations are repeated and written sequentially. When the write control signal changes from the first state to the second state, the write counter and write address generation circuit are reset, and the data is taken in one bit at a time into the second serial-parallel conversion circuit, and the m-th bit is When data is captured, it is transferred to the reset address data buffer.

Thereafter, the data is taken into the first serial-to-parallel converter circuit again starting from the (m+1)th bit, and sequentially written from the first address of the memory cell array via the input buffer register in units of m bits.

Furthermore, when the read control signal is in the l-th state, the read address generation circuit reads m from the address generated.
Bit data is taken into a parallel-serial conversion circuit via an output buffer register, and output bit by bit via an output data changeover switch. Further, the read counter operates to output a read request to the memory cell array when all m-bit data of the parallel-serial conversion circuit is output.

Next, when the read control signal changes from the first state to the second state, the read counter is reset to 1, and at the same time the output data changeover switch selects the reset address data bath output, and the reset address data Data is output from the buffer one bit at a time.

Also, at the same time as the read control signal changes from the first state to the second state, the read address generation circuit is also reset, a read request is output to the memory cell array, and the m-bit data of the first address is output to the buffer register. Keep it in.

Next, when the output of m bits from the reset address data bus sofa is completed, the output data changeover switch is turned to select the output of the parallel-to-serial converter circuit, and the m bits of data are transferred from the output buffer register and output one bit at a time. Thereafter, m bits are sequentially read out from the memory cell array according to the address generated by the read address generation circuit.

Because the operation is as described above, the first data is output immediately after the read control signal changes from the first state to the second state, and thereafter data can be output in the order in which they were written. It is possible to eliminate the time delay until the is output. [Examples] Examples of the present invention will be described below with reference to the drawings.

FIG. 1 is a configuration diagram showing a first embodiment of a video memory according to the present invention, in which 1 is an IC (integrated circuit) video memory, 2 is an input terminal for write data, and 3 is a read data terminal. 4 is a write clock input terminal, 7 is a read clock input terminal, 26 is a write address reset input terminal for setting the write address to address O, and 27 is a read address for setting the read address to address O. Reset input terminal, 7 is a write address generation circuit that automatically increments the write address and generates it sequentially, 22 is a read address generation circuit that automatically increments the read address and generates it sequentially, 18 is a write address generation circuit that generates the serial data for writing. a write clock gate circuit that outputs input timing; 21 a read clock gate circuit that outputs read serial data output timing; 19 a write counter that generates the timing of a write request to the memory cell array 10;
20 is a read counter that generates the timing of a read request for data in the memory cell array 10; 45 is a write control means; 46 is a read control means; 23 is a read request and a write request to the memory cell array 10 that occur simultaneously on the time axis. 24 is an address selection switch for selecting whether the address of the memory cell array 10 is read or written; 8a is a priority circuit for inputting write data in series; The first serial-to-parallel conversion circuit 8b is composed of an m-bit shift register and outputs it as m-bit parallel data.When the write address reset signal is input, the first serial-to-parallel conversion circuit 8b inputs the write data serially and outputs it as m-bit parallel data. A second serial-to-parallel conversion circuit includes an m-bit shift register for output; 9 is an input buffer register for holding the output data of the first serial-to-parallel conversion circuit 8a; and 11 is for storing data read from the memory cell array 10. output buffer register to hold,
12 is a buffer register 1 that outputs m-bit parallel data.
A parallel-to-serial conversion circuit consisting of an m-bit shift register that takes in data from 1 and outputs it in series according to a control signal, 16 holds the output data of the second serial-to-parallel conversion circuit 8b, and the read address water set input signal is A reset address data buffer register outputs serial data when input, and an output switch 25 selects either the output data of the parallel-serial conversion circuit 12 or the output data of the reset address data buffer register 16 and outputs the data. It's a switch.

Next, the operation will be explained using FIG. 2.

FIG. 2 is a timing chart showing an example of the operation of FIG. 1, in which A is a write address reset signal, B is a read address reset signal, C1 is input data to the first serial-parallel conversion circuit 8a, C2 is an input to the second serial-parallel conversion circuit 8b. data, D is the count value of the write counter 19, E1 is the data acquisition signal of the input buffer register 9, E2 is the data acquisition signal of the reset address data buffer register 16, F is the content of the data of the input buffer register 9, and G is the reset address. Data content of data buffer register l6, H is reset address data buffer register 1
6 output data, ■ is the parallel-serial conversion circuit 12
, J is the selection signal of the output changeover switch 25, and K is the data output to the data output terminal 3.
The write operation will be explained using FIGS. 1 and 2.

When m-bit data is input to the first serial-parallel converter 8a at time te, the write counter 19 generates a capture signal E1 to the input buffer register 9.
The data is held as m-bit parallel data in the input buffer register 9, and then written to address K (K is an integer) of the memory cell array 10.

At time t2, the write address reset signal falls, the address is reset, and write counter 1
9 is reset, and the second serial-to-parallel converter circuit 8
b outputs a write request for address 1 of the memory cell array 10 at the same time as starting to take in input data.

At time t, the value of the write counter 19 indicates m, and data is transferred to the reset address data buffer register 16.

Next, after time t3, the input data is input to the first serial-parallel conversion circuit 8a, and when m bits are input at time t6, the data capture signal E1 to the input buffer register 9 is outputted, and the input data is input to the input buffer register 9. The data is transferred and written to address l of the memory cell array 10. Thereafter, each time m-bit data is taken into the first serial-parallel conversion circuit 8a, it is sequentially written into the memory cell array 10 via the input buffer register 9.

Next, the read operation will be explained.

When the read address reset signal falls at time t4, the output changeover switch 25 selects the output data selection signal J.
By setting ``high level (H)'', the data in the reset address data buffer register 16 is selected, and at the same time, the data in the reset address data buffer register 16 is set to ``high level (H)''.
outputs data while shifting it one bit at a time.

Also, when a read address reset is input, a read request for the data at address 1 from the memory cell array 10 is issued, and the data is sent to the parallel-to-serial converter circuit 1 via the output buffer register 11 by m clocks after the reset.
Read it out to 2. After that, at time t, when the address data at address O (data in the reset address data buffer register 16) has completed outputting m bits, the data at the continuous address 1 is output by setting the output data selection signal J to ljL''. The output of the parallel-to-serial conversion circuit 12 is selected by the output changeover switch 25 and output.

Thereafter, m bits are read out from the memory cell array 10 in the order in which they were written, and outputted from the parallel-serial conversion circuit 12 via the output buffer register 1l. As explained above, in this embodiment, it is possible to output data at address O immediately after resetting the read address. FIG. 3 is a diagram showing an embodiment of the write counter 19 for generating the timing to take in data to the input buffer register 9 and the reset address data buffer register l6 of FIG.
- Binary counter (hereinafter referred to as .BC) with input function; 31 is a D flip-flop with clear input (hereinafter referred to as .BC);
DFF), 32a and 32b are inverter circuits, 3
3a and 33b are AND circuits. 34a and 34b are power supply circuits.

FIG. 4 is a timing chart showing the operation of FIG. 3, in which the value of m is set to 32. here. Wrsq
I is a timing signal for the input buffer register 9 to take in data from the first serial-to-parallel conversion circuit 8a, and Wreq n is a timing signal for the reset 1 to address data buffer register 16 to take in data from the second serial-to-parallel conversion circuit 8b.
represents the timing signal for capturing the data.

When the write address reset signal is not input,
The CO output of BC30e starts when the counter counts 32 (
From time te and tz), the eclock portion IIH I+ is output. At this time, if the Q output of DFF31 is "IIH", Wreq I output by AND (logical OR) of the CO output of BC30e and the Q output of DFF31 is BC
The same signal as the Go output of 30e is output. Also, B
AN of CO output of C30e and Q output of DFF31
Wreq■ output at D remains at "L". When a write address reset is input at time t, the DFF 31 is cleared and Q becomes II L It.

At this time, the counter is reset at the same time.

When the counter value reaches 32 at time t4, the C of BC30e
The O output becomes the eclock portion it H II.

At this time, Wreq I is output as "L", and Wreq II is outputted as II H I+ corresponding to the electric current.

Thereafter, at time t5, the Q output of the DFF 31 becomes It H I+ due to the fall of the CO output of the BC 30e. After this, the counter continues to operate, and every time the count value reaches 32, BC30eCo is output, and the same operation as at time t4 and time t2 is performed.

Due to the above operations. Wreq E is output every 32 clocks, and a write counter can be realized in which a write address reset signal is input and Wreq (2) is generated at the 32nd clock.

FIG. 5 is a diagram showing an embodiment of the read counter 20 necessary for outputting the read address shown in FIG.
36a to 36e are binary counters with reset input, 3
8a to 38c are DFFs.

Rreq is data read request No. 42, Outpu
tSel is a switching signal of the output changeover switch 25 in FIG.

FIG. 6 is a timing chart showing the operation of FIG. 5, in which Rreq is output every 32 clocks like time t1+t2 unless a read address reset signal is input.

Therefore, when the read address reset signal is input at the time, the DFFs 38a and 38b and the AND circuit 5
0, the reset signal is detected at the clock rise time t4 closest to the reset signal input, and the reset signal is detected at the clock rise time t4, which is the closest to the reset signal input.
4 to 1 clock width signal is output.

This signal is outputted as Rreq via OR (logical sum) 51.

BC36aC at time t, 32nd clock from time t4
o is output, and thereafter B C 3 6 e Co is output every 32 clocks unless a reset signal is input.

Output S el becomes “H II” from time t4 to time t6, which is 32 clocks.

By the above-described operation, a read counter capable of generating a read data output switching signal and a data read request at address reset can be realized.

FIG. 7 is a block diagram of a second embodiment of the video memory according to the present invention, in which 16a is a first reset address data buffer register that holds parallel data from the second serial-parallel conversion circuit 8b.

16b is a second reset address data buffer register composed of an m-bit shift register. When a read address reset signal is input, data is taken from the first reset address data buffer register 16a and serially outputted while shifting one bit at a time. It has a function.

As explained in the embodiment of FIG. 1, the following description will be made assuming that data is taken into the second serial-to-parallel conversion circuit 8b by the write address reset, and the data is held in the first reset address data buffer register 16a. do.

FIG. 8 is a time chart showing the operation of the embodiment shown in FIG.
At time tx), the second reset address data buffer register 16b takes in data from the first reset address data buffer register 16a and outputs it bit by bit.

Eventually, the output is completed at time t2, and the data of the next address 1 is output. Note that the operation of the output selection signal for outputting each data is the same as in the embodiment shown in FIG.

Next, when the read address is input again at time t, the same operation as at time t1 is performed as described above, and the data at address O is output.

Thereafter, the operation from time te to time t is performed every time the read address reset is input.

As described above, according to this embodiment, the same effects as the embodiment shown in FIG. 1 can be obtained, and the data at address 0 can be read multiple times. FIG. 9 is a block diagram of a third embodiment of the video memory according to the present invention, in which 40 is a write enable input terminal for inputting a control signal for inhibiting data writing to the memory cell array 10, and 41a and 4lb are write enable input terminals. The data input from the write enable input terminal is input in series.
Write enable circuits 42a and 42b output data in parallel bits, and m three-state buffer circuits 1, 41c, and 41d restrict data writing to the memory cell array 10 and the second reset address data buffer register 16b in bit units. This is a write enable circuit that provides a control signal to the three-state buffer circuits 42a and 42b. Write enable circuits 41a, 4l
b takes in the data of the write enable input terminal 40 in synchronization with the first serial-parallel converter circuit 8a and the second serial-parallel converter circuit N8b, respectively, and when m bits are input, the data is sent to the write enable circuits 41c and 41d as parallel data. The signal is taken in and given as a control signal to the three-state buffer circuits 42a and 42b.

Each bit 1/output of the input buffer register 9 in parallel is input to the memory cell array 10 via the three-stit buffer circuit 42b in l-bit units.

It is assumed that the output control signal of each bit of the three-state buffer circuits 42a and 42b outputs an input when it is in the "Lp+" state, and the output becomes high impedance when it is "H".

When 11 L I+ is input to the write enable input terminal 40, the first serial-parallel conversion circuit 8a
The data taken in is transferred and written to the memory cell array 10, and the data taken in when #H #l is input is not transferred and written to the memory cell array 1o.

The operation of the three-state buffer 7 circuit 42b can similarly prohibit data from being written into the second reset address data buffer register 16b. As described above, it becomes possible to inhibit writing of data in bit units to the memory cell array 10. [Effects of the Invention] As explained above, according to the present invention, it is possible to output new data immediately after resetting the address of the video memory.
A video memory that is easy to use can be obtained, and a video memory with excellent functions can be provided, except for the problems of the prior art described above.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a first embodiment of the video memory according to the present invention, FIG. 2 is a timing chart showing an example of the operation of FIG. 1, and FIG. 3 is an implementation of the write counter 19 of FIG. 1. A block diagram showing an example, FIG. 4 is a timing chart showing the operation of FIG. 3, FIG. 5 is a block diagram showing an embodiment of the read counter 20 of FIG. 1, and FIG. 6 is a timing chart showing the operation of FIG. 7 is a block diagram of the second embodiment of the video memory according to the present invention, FIG. 8 is a time chart showing the operation of the embodiment of FIG. 7, and FIG. 9 is a diagram of the second embodiment of the video memory according to the present invention. FIG. 10 is a diagram showing a basic example of a conventional video memory, and FIG. 11 is a timing chart showing an example of the operation of the video memory of FIG. 10. Engineering: video memory, 2: data input terminal, 3:
...Data output terminal, 8a...First serial-parallel conversion circuit, 8b...Second serial-parallel conversion circuit, 9...Input buffer register, 10...Memory cell array, 11...Output Buffer register, 12.
... Parallel-serial conversion circuit, 19... Write counter, 20... Read counter, 16... Reset address data buffer register, 25... Output changeover switch. Shinshin-゛

Claims (1)

[Claims] 1. first and second serial-to-parallel conversion circuits that are supplied with serial data and output m-bit parallel data;
an input buffer register that holds the output data of the first serial-to-parallel conversion circuit; a reset address data buffer register that holds the output of the second serial-to-parallel conversion circuit and outputs data in series; and the input buffer register. a memory cell array that stores the output data of the memory cell array, an output buffer register that holds the data read from the memory cell array, and a parallel-serial system that holds the m-bit data transferred from the output buffer register and outputs the data in series. a conversion circuit;
an output data changeover switch that selects and outputs one of the output data of the parallel-serial conversion circuit and the output data of the reset address data buffer register;
In a video memory comprising a data write control means having a write address generation circuit and a data read control means having a read address generation circuit, the second serial
Input m-bit data one bit at a time to the parallel conversion circuit and hold it in the reset address data buffer register, input subsequent data one bit at a time to the first serial-parallel conversion circuit, and convert the m bits at once into the above data. 1 from the reset address data buffer register via the output data changeover switch according to the write control means for writing to the memory cell array via the input buffer register and the signal from the read control means.
Data input/output to the video memory is performed by the read control means, which outputs m-bit data bit by bit, and thereafter outputs data bit by bit from the parallel-serial conversion circuit in the order in which it was written, via the output data changeover switch. A video memory characterized in that the address reset is performed immediately after the address is reset.