JPH04259984A - Memory access method - Google Patents

Abstract

PURPOSE:To present the memory access method to prevent noise from entering by centralizing an access current and to reduce the size of wiring for a power supply circuit and a memory circuit concerning the memory access method in the case of parallelly reading a lot of data in an image memory or the like and using these data after converting them into serial data. CONSTITUTION:At the memory access method to read the plural data to be converted into the serial data from plural memories (1, 2, 3 and 4), the plural memories (1, 2, 3 and 4) are read out at different timing according to plural memory strobe signals (SASq and SAS2) at different timing.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory access method for reading out a large amount of data in parallel from an image memory, etc., and converting the read data into serial data for use.

0002

2. Description of the Related Art Image data tends to increase due to the demand for higher image quality, and there is also a demand for faster image processing. For this reason, the capacity of the image memory has increased, and access when reading the image memory must also be devised.

FIG. 5 shows data for four pixels being read out simultaneously, converted to serial data, and displayed on a display section (not shown).
FIG. 6 is a block diagram of an image memory and its peripheral circuits, and a timing chart for explaining its operation. In the figure, 1, 2, 3, and 4 are dual-port image read/write memories (hereinafter referred to as VRAMs), and data of four adjacent pixels are stored at the same address. The field data can be stored. The SAS (serial access memory strobe) signal generation circuit 11 uses a dot clock C that determines the display timing of each pixel in the display section.
SAS signal (Figure 6 (1)) synchronized with LK (Figure 6 (1))
2)) and store it in VRAM1, 2, 3, 4 and P
/S (parallel/serial) Provided to conversion control circuit 12. In synchronization with this SAS signal, VRAM1, 2, 3, and 4 output the data at the address determined by the address signal (not shown) (Fig. 6 (3) to (6)), and send this to the P/P.
S input to the conversion circuit 13. P/S conversion circuit 13
is the read data input simultaneously to the dot clock CL.
Serial data that follows the display pixel order according to K (Figure 6
(7)). Note that the numbers in (3) to (7) in FIG. 6 represent pixel numbers.

0004

[Problems to be Solved by the Invention] In the conventional memory access method as described above, the four VRAMs 1, 2, 3,
4 are accessed simultaneously, the access current concentrates at the rising timing of the SAS signal, causing noise to be mixed into the read data. Also, appropriate consideration had to be given to the wiring. The present invention has been made to solve these problems, and makes it possible to disperse access currents, prevent noise intrusion due to concentration of access currents, and reduce the size of wiring for power supply circuits and memory circuits. The purpose is to provide a memory access method.

[0005]

[Means for Solving the Problems] The memory access method of the present invention provides access to a plurality of memories (1, 2, 3, 4) using a plurality of memory strobe signals (SAS) having different timings.
) are read out at different timings.

[0006]

[Operation] By performing the access as described above, the access current can be distributed by the number of memory strobe signals, and problems caused by access current concentration can be avoided.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to drawings showing embodiments thereof. FIG. 1 is a schematic block diagram showing a memory peripheral circuit for implementing the method of the present invention, and FIG. 2 is a time chart illustrating its operation. The configuration and data storage state of VRAMs 1, 2, 3, and 4 are exactly the same as the conventional one shown in FIG. 5, and data of four adjacent pixels are stored at addresses accessed by the same address signal. The SAS signal generation circuit 5 generates two SAS signals SAS1 and SAS2 (
Figure 2 (2), (3)) is created, and the former is stored in VRAM1, 2.
The latter is given to VRAM3 and VRAM4. Also, both SAS signals SAS1 and SAS2 are shown in Figure 2 (1).
It is a signal that is high for two periods and low for two periods in synchronization with the dot clock CLK shown in FIG. 1, and the latter is delayed by one clock from the former.

FIG. 3 is a block diagram of a SAS signal generation circuit, which includes two D flip-flops, one JK flip-flop, and the like. Mask signal MSK that is at high level during reading from a memory read control circuit (not shown)
is applied to the AND gate 54, and the other input of the AND gate 54 is the Q-bar output of the D flip-flop 51. The output of the AND gate 54 is input to the data terminal D of the D flip-flop 51, and the dot clock CLK is input to the clock terminal CK. D
The Q output and Q bar output of the flip-flop 51 are input to input terminals J and K of a JK flip-flop 53, respectively. The dot clock CLK is given as a trigger to the JK flip-flop 53. JK flip flop 5
The Q output of 3 becomes the SAS signal SAS1, and is input to the data terminal D of the D flip-flop 52. The dot clock CLK is this D flip-flop 5
2 is similarly input to the clock terminal CK. D
The Q output of the flip-flop 52 is the SAS signal SAS2
It becomes.

The memory read control circuit generates a reset signal and applies it to three flip-flops 51, 52, and 53. D flip-flop 51 and JK flip-flop 53
In combination with this, the dot clock CLK is divided into four, and the SAS signal SAS1 is created. This is used as the data input.The D flip-flop 52 receives the SAS signal SA.
By delaying S1 by one dot clock CLK, the required SAS signal SAS2 is obtained. VR by such SAS signals SAS1 and SAS2
The data read from AM1, 2, 3, 4 is the data read from VRAM1, 2 by the former, and the data read from VRAM3 by the latter.
, 4 by one dot clock CLK (see FIG. 2 (4) to (7)). The data read in this way is input to the selector 6 which functions to convert parallel data to serial data, and is shown in FIG. 2 (8).
The data is converted into serial data synchronized with the dot clock CLK as shown in FIG.

FIG. 4 shows the configuration of the selector 6. VRAM
Each data from 1, 2, 3, 4 is AND gate 61,
There is one input each for 62, 63, and 64. S.A.S.
The signal SAS1 serves as an input to each of AND gates 65 and 66, and also serves as a low active input to each of AND gates 67 and 68. SAS signal SA
S2 serves as an input to each of the AND gates 66 and 67, and also serves as a low active input to each of the AND gates 65 and 68. Each output of AND gates 65 to 68 is AND gate 6
1 to 64, and the AND gate 61
The outputs of .about.64 are input to the data terminal D of the D flip-flop 70 via the OR gate 69. A dot clock CLK is applied to the clock terminal CK of the D flip-flop 70, and this Q output is applied to the display section.

Next, the access method of the present invention will be explained together with the function of the selector 6. SA created as described above
When the S signal SAS1 is applied to the VRAMs 1 and 2, data is read from the address corresponding to the address signal applied at that time at its rising timing. During the period when the SAS signal SAS1 is at high level and SAS2 is at low level, only the output of AND gate 65 is at high level, so the data read from VRAM1 is sent to D flip-flop 7 via AND gate 61 and OR gate 69.
It will be given to 0. Next dot clock CLK
At the timing of SAS signals SAS1, SAS2
Since both are at high level, only the output of AND gate 66 is at high level, and the data read from VRAM2 is passed through AND gate 62 and OR gate 69.
A D flip-flop 70 is provided. On the other hand, at the rising edge of the SAS signal SAS2, VRAM3 and VRA
M4 is accessed and data at the corresponding address is read.

At the next clock timing, the SAS signal SAS1 goes low, so only the output of the AND gate 67 goes high, and the data read from the VRAM3 is passed through the AND gate 63 and the OR gate 69 to the D flip-flop 70. given to. Then, at the next clock timing, both SAS signals SAS1,
Since both SAS2 are at low level, AND gate 68
Only the output becomes high level, and the data read from VRAM 4 is applied to D flip-flop 70 via AND gate 64 and OR gate 69. The D flip-flop 70 latches input data one by one using the dot clock CLK and outputs it to the display section. Note that the numbers in (4) to (8) in FIG. 2 represent pixel numbers.

[0013] In the above explanation, it is assumed that the data read out from each of VRAMs 1 to 4 by one SAS signal is 1 bit, but if the data has a multiple bit configuration, it is shown surrounded by a dashed line in FIG. , AND gates 61-64
, an OR gate 69, and a D flip-flop 70 for the number of bits. In the above embodiment, the VRAM has a four-layer structure and two types of SAS signals are used, but the present invention is not limited to this, and can also be implemented by using two or more types of SAS signals for a memory with a multilayer structure. .

[0014]

According to the present invention as described above, access currents are distributed by the number of SAS signals (two in this embodiment), and therefore the number of access currents flowing simultaneously is reduced. Therefore, the possibility of noise intrusion is reduced. Further, the present invention has excellent effects such as being able to reduce the size of wiring in power supply circuits, memory circuits, etc., and reducing the burden thereof.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a memory peripheral circuit according to the method of the present invention.

FIG. 2 is a timing chart of the method of the present invention.

FIG. 3 is a block diagram of a SAS signal generation circuit.

FIG. 4 is a block diagram of a selector.

FIG. 5 is a block diagram of a conventional memory peripheral circuit.

FIG. 6 is a timing chart of a conventional method.

[Explanation of symbols]

1, 2, 3, 4 VRAM

Claims (1)

[Claims] Claim 1: In a memory access method for reading a plurality of data to be serial data from a plurality of memories (1, 2, 3, 4), a plurality of memory strobe signals (SAS1, SAS2) having different timings are used. A memory access method characterized by reading a plurality of memories (1, 2, 3, 4) at different timings.